In my previous post I introduced the first two steps of a three step process for calculating the required op amp bandwidth for your transimpedance amplifier. In this post I’ll explain the final step and introduce a design example using this process.
Step 3: Calculate the required op amp gain bandwidth product.
A basic stability analysis will reveal the logic behind this step, but if you just want the calculation you can skip to equation 5. Figure 1 shows the TINA-TI™ circuit used for the analysis. The feedback loop is broken with a large inductor (L1) and a voltage source is ac coupled to the loop through a large capacitor (C1). The loop is broken at the op amp output so that the effects of the input capacitance are included in the analysis. An ac transfer characteristic is performed and the post-processor is used to generate the open-loop gain (AOL) and noise gain (1/β) curves (Figure 2).
Figure 1: Breaking the feedback of a transimpedance amplifier and generating AOL and 1/β curves.
Figure 2: AOL and 1/β plot for a typical transimpedance amplifier circuit.
On the 1/β curve there are 3 points of interest. First, there is a zero at the frequency:
Above this frequency, the 1/β curve will increase a rate of 20dB per decade. Next, there is a pole, at the frequency:
which will cause the 1/β curve to “flatten out.” Finally, the 1/β curve intersects the AOL curve at the frequency:
In equation 5, fGBW is the unity gain bandwidth of the op amp. In order to maintain stability, the AOL curve must intersect the 1/β curve when the 1/β curve is flat (assuming a unity gain stable op amp). If the AOL curve intersects the 1/β curve when the 1/β curve is rising, as shown by the dashed line in Figure 4, the circuit may oscillate. This gives us the rule:
Inserting the equations for fI and fp into this rule and solving for unity gain bandwidth, we arrive at a useful equation:
Equation 5 eliminates one of the mysteries when selecting an op amp for your transimpedance amplifier design. Choosing an op amp with adequate bandwidth not only ensures you have sufficient signal bandwidth, but also helps to avoid potential stability headaches!
Now I’ll apply this process to a design example and compare the performance of the circuit using two op amps. One op amp will meet the gain bandwidth requirements we calculate and the other will not. The requirements for this design example are given in table 1.
Table 1: Example performance requirements for a transimpedance amplifier
To start, we calculate the maximum feedback capacitance for the circuit to be stable and still meet our bandwidth goal:
Next, we determine the capacitance at the inverting input of the amplifier. Because we haven’t selected an op amp yet for our circuit we do not know the values of CD and CCM2. Remember that I suggested 10pF as a reasonable guess for this capacitance in Part I.
Finally we can calculate the gain bandwidth requirements for the op amp:
For this example, I’ll compare the two op amps shown in table 2:
Table 2: Gain bandwidth product comparion of two op amps for the design example.
From our previous calculations, we know that one of these op amps, the OPA313, does not have sufficient bandwidth for our circuit. But how does this actually affect the operation of the circuit?
Read part 3 which is coming soon to find out!
The theory looks good. You are taking an interesting view on how to solve the transimpedance amplifier issue, which I like.
I am looking at the components that you are suggesting and the value of Cf <= 1.59pF looks a little awkward. I know the feedback resistor parasitics along with the PCB parasitics would be ~ 0.5pF to 1.5 pF. In this case, these parastics would be added to your Cf. Would this whole scenario be difficult to implement in a real circuit?
I've built transimpedance amplifiers for high speed applications that are compensated with <1pF, you just have to get a little creative. For example placing a few feedback resistors in series reduces their parasitic capacitance and removing the ground plane around these portions of the circuit is an absolute must. Because the relative permittivity of FR4 is only about 4-5 it actually takes a fair amount of copper to get 1 pF of parasitic capacitance (an even more for controlled dielectric materials such as Rogers which has a permittivity around 3). I personally think the 1-2pF of parasitic capacitance is a conservative engineering rule of thumb but is by no means set in stone if layout is carefully considered. According to Vishay, the typical parasitic capacitance of an 0603 resistor is 40 fF which can be significant in high speed applications (they have a great app note titled "Frequency Response Characteristics of Thin Film Resistors").
For <1pF compensation the absolute biggest headache is the tolerance of the feedback capacitor. RF capacitors with tight tolerances tend to be rather expensive!
Thanks for taking this interesting application and describe it in compact yet detailed why.
Commenting on Bonnies remark, I do agree with John that compensating with ~1pf should be no issue. There is another appnote from Vishay 'Resistors in Microwave Applications' which point this out. Needless to say that special care should be taken on lay-out level as well. The surrounding of the feedback element is very important as there is also the distributed parasitics to be considered. It's not only the end of the component (resistor in this case) that is a single capacitor but could be modeled as an integral of RC-combinations (or low passes) over the length of the component. This distributed capacitance is not related to the terminals but to the environment which could lead to larger unexpected delay times. To counter this special trimming techniques have been developed, like pulse trimming. Lately there is also a discussion that the lacquer finish contributes.
Nice blog. Can you please tell me from where L1 inductor,C3 capacitance and VG1 source came? What have been modelled as these three extra circuit components?
L1, C1 and voltage source VG1 form a very common method for stability analysis. Inductor L1 breaks the feedback loop at AC but keeps the loop closed at DC to allow convergence in SPICE simulators. Capacitor C1 isolates voltage source VG1 for DC convergence and then AC couples it into the loop for AC analysis. By breaking the loop with inductor L1, injecting a signal with VG1, and measuring the output at point Vout, the loop gain and phase can be plotted to confirm stable operation.
Oh fine. Thank you for instant reply
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