Tools InsiderYour development toolbox! Get the latest design tips, trends and advice on development tools and software for TI embedded processors.https://e2e.ti.com/blogs_/archives/b/toolsinsider/atomTelligent Community (Build: 11.1.7.15705)2015-07-17T10:44:00ZChanges to TI Tools Insider bloghttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/changes-to-ti-tools-insider-blog2017-12-21T14:40:00Z2017-12-21T14:40:00Z<p><img src="/cfs-file.ashx/__key/communityserver-components-sitefiles/images-blog_2D00_headers/toolsinsider.banner.jpg" style="float:left;" width="200" height="125" alt=" " /></p>
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<p></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=669982&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Allie Hopkins1https://e2e.ti.com:443/members/6164617From the Experts: Perform cyclic redundancy checking using linker-generated CRC tableshttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/from-the-experts-perform-cyclic-redundancy-checking-using-linker-generated-crc-tables2017-02-27T15:00:00Z2017-02-27T15:00:00Z<div><b>Other Parts Discussed in Post: </b><a href="https://www.ti.com/tool/CONTROLSUITE" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">CONTROLSUITE</a></div><p>To verify code and/or data integrity, TI’s microcontroller (MCU) Code-Generation Tools (CGTs), including the C2000™ MCU CGT, the MSP430™ MCU CGT and the TI ARM CGT, support cyclic redundancy checking (CRC). This method can greatly enhance the performance of your embedded design and is easy to use, once you understand the basics of how CRC works. The focus of this blog post will be CRC with the C2000 MCU CGT; for more detailed information about CRC with the MSP430 MCU CGT and ARM®-based CGTs from TI, see the <i>Additional Resources</i> section below.</p>
<p>Designers use CRC to detect errors that might occur during data transmission. For a given section of code or data in an output file, the originator of the data – also known as the sender – applies a specific CRC algorithm to the content in that section to produce a CRC value, which is stored at a separate location in the output file. The consumer of the data – known as the receiver – knows what algorithm was applied to the section and can apply that same CRC algorithm to the code or data transmitted. If the CRC value computed by the receiver does not match the one computed by the sender, then the receiver may conclude that some error occurred during transmission and take appropriate action to address the problem, such as requesting that the sender retransmit the data.</p>
<p>You can check out a simple demonstration running on Code Composer Studio™ (CCS) software of how to perform CRC at run time using linker-generated CRC tables in the video, “<a href="https://www.youtube.com/watch?v=1NgqmoukFes&feature=youtu.be">Performing CRC with linker-generated CRC tables</a>.”</p>
<p><a href="https://www.youtube.com/watch?v=1NgqmoukFes&amp;feature=youtu.be">www.youtube.com/watch</a></p>
<p><b></b><b>Linker-generated CRC tables</b></p>
<p>The C2000 MCU linker supports an extension to the linker command file (LCF) syntax, the crc_table() operator, that generates a CRC value for a given initialized section of code or data. If a crc_table() operator is attached to the specification of a region (an output section, a GROUP, a GROUP member, a UNION or a UNION member), then the linker will compute a CRC value for that region and store that CRC value in target memory such that it is accessible at boot or run time.</p>
<p>Consider as an example a section of data that gets written to flash memory. Within the LCF, you would specify a crc_table() operator to be associated with the data section like this:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/2772.Figure-1.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/2772.Figure-1.jpg" alt=" " /></a></p>
<p>In the above snippet of the LCF, the crc_table() operator instructs the linker to generate a CRC table data object called crc_table_for_2b. Using the C2000 MCU linker, this would result in a data object that looks like this:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0211.Figure-2.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0211.Figure-2.jpg" alt=" " /></a></p>
<p>The crc_tbl.h file located in the Include subdirectory where your C2000 MCU CGT is installed provides the formal specification of the CRC_TABLE and CRC_RECORD data structures. CRC_TABLE is a header for a vector of one or more CRC_RECORDs. Besides the location and size of the region of memory to check, each CRC_RECORD also identifies the CRC algorithm applied to that memory region to arrive at the “crc_value.” By default, when a user specifies a crc_table() operator with a single argument, the C2000 MCU linker will use what it refers to as the CRC32_PRIME algorithm. This corresponds to the CRC32 polynomial 1 (= 0x04C11DB7) CRC algorithm that C28x plus Viterbi, complex math and CRC unit (C28x+VCU) devices support in hardware. However, the linker also allows users to select a different CRC algorithm as a second argument to the crc_table() operator.</p>
<p>The complete syntax for the crc_table() operator is:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/2376.Figure-3.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/2376.Figure-3.jpg" alt=" " /></a></p>
<p>The C2000 MCU linker recognizes the values in Table 1 as valid crc_algorithm_id arguments. You can specify either the linker name or linker ID.</p>
<table style="background:#d9d9d9 none repeat scroll 0% 0%;" cellspacing="0" cellpadding="0" border="1">
<tbody>
<tr style="height:14.7pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:14.7pt;border:1pt solid #404040;" width="142" valign="top">
<p><b>Linker name</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:14.7pt;" width="90" valign="top">
<p><b>Linker ID</b></p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:14.7pt;" width="395" valign="top">
<p><b>Equivalent CRC algorithm on C28x plus VCU hardware</b></p>
</td>
</tr>
<tr style="height:15.5pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:15.5pt;" width="142" valign="top">
<p><b>CRC32_PRIME</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:15.5pt;" width="90" valign="top">
<p>0 (default)</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:15.5pt;" width="395" valign="top">
<p>CRC32 polynomial 1 (= 0x04C11DB7)</p>
</td>
</tr>
<tr style="height:14.7pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:14.7pt;" width="142" valign="top">
<p><b>CRC16_802_15_4</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:14.7pt;" width="90" valign="top">
<p>1</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:14.7pt;" width="395" valign="top">
<p>CRC16 polynomial 2 (= 0x00001021)</p>
</td>
</tr>
<tr style="height:15.5pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:15.5pt;" width="142" valign="top">
<p><b>CRC16_ALT</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:15.5pt;" width="90" valign="top">
<p>2</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:15.5pt;" width="395" valign="top">
<p>CRC16 polynomial 1 (= 0x00008005)</p>
</td>
</tr>
<tr style="height:14.7pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:14.7pt;" width="142" valign="top">
<p><b>CRC8_PRIME</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:14.7pt;" width="90" valign="top">
<p>3</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:14.7pt;" width="395" valign="top">
<p>CRC8 polynomial (= 0x00000007)</p>
</td>
</tr>
<tr style="height:15.5pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:15.5pt;" width="142" valign="top">
<p><b>CRC32_C</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:15.5pt;" width="90" valign="top">
<p>11</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:15.5pt;" width="395" valign="top">
<p>CRC32 polynomial 2 (= 0x1EDC6F41)</p>
</td>
</tr>
<tr style="height:15.5pt;">
<td style="padding:0in 5.4pt;width:106.75pt;height:15.5pt;" width="142" valign="top">
<p><b>CRC24_FLEXRAY</b></p>
</td>
<td style="padding:0in 5.4pt;width:67.55pt;height:15.5pt;" width="90" valign="top">
<p>12</p>
</td>
<td style="padding:0in 5.4pt;width:295.9pt;height:15.5pt;" width="395" valign="top">
<p>CRC24 polynomial (= 0x005D6DCB)</p>
</td>
</tr>
</tbody>
</table>
<p>As you will see later, it is critical that the CRC algorithm selected at link time to compute the CRC value for a region is the same CRC algorithm that the application uses to CRC the region at run time.</p>
<p></p>
<p><b>Generating a single CRC table for multiple regions</b></p>
<p>Before discussing how to do an actual CRC on a region at run time, let’s consider another LCF example in which a single CRC table can check multiple regions. There are two ways to create a single CRC table that applies to multiple regions. In crc_ex1.cmd, the crc_table() operator is applied to multiple output sections using the same user_specified_table_name argument for each section:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0638.Figure-4.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0638.Figure-4.jpg" alt=" " /></a><br /><br />In this case, the linker generates a single CRC_TABLE data object, flash1_crc_table, that contains three CRC_RECORDs, one for each of the output sections to which a crc_table() operator was attached:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/7167.Figure-5.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/7167.Figure-5.jpg" alt=" " /></a></p>
<p>By collecting all three CRC_RECORDs into the same table, your application can perform CRC on all three output sections simultaneously by passing the address of the CRC_TABLE, flash1_crc_table, to the CRC routine. <br /><br />Using separate crc_table() operators for each output section has a couple of benefits:</p>
<ul>
<li>You can indicate a separate CRC algorithm for each output section.</li>
<li>The memory placement of each output section is independent from the other output sections that will be checked via the CRC_TABLE.</li>
</ul>
<p>This snippet of crc_ex2.cmd shows how the application of a crc_table() operator to a GROUP specification creates a single CRC_TABLE, flash1_crc_table, for the three output section members of the GROUP:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/8233.Figure-6.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/8233.Figure-6.jpg" alt=" " /></a></p>
<p>Like the previous LCF example, the linker will create a single CRC_TABLE, flash1_crc_table, containing a vector of three CRC_RECORDs, one for each member of the GROUP:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/7585.Figure-7.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/7585.Figure-7.jpg" alt=" " /></a></p>
<p>The linker must create a separate CRC_RECORD for each member of the GROUP because there may be gaps between members of the GROUP containing unknown values. As in the previous LCF example, because the CRC table includes all three output sections, a CRC on all three of the output sections can happen at the same time.</p>
<p>While the crc_ex2.cmd example only requires a single crc_table() operator specification, there are a couple of caveats associated with applying a crc_table() operator to a GROUP:</p>
<ul>
<li>You can only indicate one CRC algorithm, which will be used for CRC on each output section represented in the CRC table.</li>
<li>The memory placement of the output section members of the GROUP is ordered and contiguous according to the placement instructions attached to the GROUP.</li>
</ul>
<p><b>How to perform CRC at run time</b></p>
<p>Now that you know how to get the linker to generate a CRC_TABLE data object for one or more regions on which you want to perform CRC at run time, you will need to include a software routine in your application that can read and process a CRC_TABLE to perform the actual CRC. Below is an example of a function, my_check_CRC(), that can read and process a linker-generated CRC_TABLE data object:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4024.Figure-8.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4024.Figure-8.jpg" alt=" " /></a></p>
<p>In this example function, the crc_tbl.h header file provides declarations for the CRC_TABLE and CRC_RECORD data structures, along with definitions of the available CRC algorithm IDs. Assume that the declarations of the calc_crcXXXX() functions are available in vcu_crc_functions.h. The CRC algorithm ID from each CRC_RECORD tells the run-time application which CRC algorithm function to call. As I mentioned earlier, the C2000 MCU linker allows you to specify one of six different CRC algorithms to use in calculating the CRC value. For example, if a CRC_RECORD identifies the CRC32_PRIME algorithm for a given region of memory, then the calc_crc32p1() function is called. The application will need to supply the calc_crc32p1() function definition. If no hardware support for CRC is available, then the algorithm can be computed in a C function. However, if the application is running on a C28x+VCU device, then the calc_crc32p1() function can use the special CRC instructions available on the device to calculate the CRC value so that it matches the crc_value stored in the CRC_RECORD.</p>
<p>The core of such a calc_crc32p1() function is a repeat block (RPTB) loop that spins through the memory region to be checked and uses the VCRC32L_1 and VCRC32H_1 instructions to calculate the CRC value for the region using the CRC32 polynomial 1:</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/3365.Figure-9.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/3365.Figure-9.jpg" alt=" " /></a></p>
<p>You can find full examples using the CRC hardware support on C28x+VCU devices in the <a href="http://www.ti.com/tool/controlsuite">controlSUITE™ software package</a>, accessible from the controlSUITE software download page on TI.com. If you have CCS installed, you can also access the controlSUITE software package from the CCS App Center. The controlSUITE software package contains example CCS projects that demonstrate the use of linker-generated CRC tables. Assembly language source is provided for functions that use CRC hardware support on C28x+VCU devices to calculate CRC values (look in the directory where you have controlSUITE software installed at controlSUITE/libs/dsp/VCU).</p>
<p><b>Additional resources</b></p>
<p>To learn more about linker-generated CRC tables in the C2000 MCU CGTs, see Section 8.9 and the appendix of the “<a href="http://downloads.ti.com/docs/esd/SPRU513/">TMS320C28x Assembly Language Tools User’s Guide</a>.”</p>
<ul>
<li>Chapter 2 of the “<a href="http://www.ti.com/lit/ug/spruhs1a/spruhs1a.pdf">TMS320C28x Extended Instruction Sets Technical Reference Manual</a>” discusses hardware support for CRC in C28x+VCU devices.</li>
<li>To learn more about linker-generated CRC tables in MSP430 MCU CGTs, see Section 8.9 and the appendix of the “<a href="http://downloads.ti.com/docs/esd/SLAU131/">MSP430 Assembly Language Tools User’s Guide</a>.”</li>
<li>To learn more about linker-generated CRC tables in TI ARM CGTs, see Section 8.9 of “<a href="http://downloads.ti.com/docs/esd/SPNU118/">ARM Assembly Language Tools v16.12.0.STS User’s Guide</a>.”</li>
<li>Read more <a href="/tags/FromTheExperts">“From the Experts”</a> blogs on <i>Tools Insider</i></li>
</ul><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=669435&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Todd Sniderhttps://e2e.ti.com:443/members/27743Data blocking in the C2000 MCU compiler explainedhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/data-blocking-in-the-c2000-mcu-compiler-explained2016-11-17T18:06:00Z2016-11-17T18:06:00Z<p style="text-align:left;">At some point, <a href="http://www.ti.com/c2000">C2000<sup>TM</sup> microcontroller</a> (MCU) compiler users might have encountered scenarios where holes are observed within memory sections, or the linker is unable to place a section even though the available memory is larger than the section. These are likely a result of data blocking<a>[1]</a>, which is a side-effect of data page pointer (DP) load optimization – an optimization automatically performed by the compiler. Before explaining DP-load optimization and data blocking, it might be helpful to explain how the compiler supports direct accesses to scalar-type variables and members of aggregate-type variables.</p>
<div style="text-align:center;">
<p style="text-align:left;">In direct addressing mode, an instruction is able to directly access data memory within the current 64-word data page stored in the DP register. The compiler generally prefers direct addressing mode over other addressing modes because direct accesses free up the other CPU registers for use by other instructions. </p>
<a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-1.JPG"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-1.JPG" width="487" height="240" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a><strong>Figure 1: Direct and Indirect addressing modes for accessing a[10]</strong></div>
<div style="text-align:center;"><strong> </strong></div>
<div style="text-align:left;"></div>
<div style="text-align:left;"></div>
<div style="text-align:left;"></div>
<div style="text-align:left;"></div>
<div style="text-align:left;">Consider the following sample C source that includes two accesses to the global “<i>array1</i>”.</div>
<div style="text-align:left;"><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-2.JPG"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-2.JPG" width="440" height="233" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></div>
<div>
<p align="center"><strong>Figure 2: Sample source with constant accesses to array "array1"</strong></p>
<p align="center"><strong> </strong></p>
</div>
<div></div>
<div></div>
<div></div>
<div>Without DP-load optimization, the compiler will conservatively issue a DP-load instruction before each direct access to (members of) a global variable.</div>
<div><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Presentation1.jpg"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Presentation1.jpg" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></div>
<div>
<p align="center"><strong>Figure 3: Assembly file generated after compiling Figure 2 with DP-load optimization disabled (using compiler option --disable_dp_load_opt)</strong></p>
<p align="center" style="text-align:left;">However, additional DP-load instructions are unnecessary when the current DP is still valid. Unnecessary DP-loads negatively impact code size and performance. Consider the (simplistic and probably unlikely) case of consecutive direct accesses to 64 words that are allocated on the same data page. These accesses will cost 63 bytes of redundant DP-load instructions in the .text section and 63 unnecessary cycles executing these redundant load instructions. These costs will increase proportionally with the number of direct accesses. </p>
<p align="center" style="text-align:left;"><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-4.JPG"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-4.JPG" width="624" height="302" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p align="center"><strong>Figure 4: Assembly file generated after compiling Figure 2 with DP-load optimization enabled (default behavior of the compiler)</strong></p>
<p>Our compiler mitigates these performance costs by blocking global variables. Blocked variables must either fit entirely within a data page, or be page-aligned (i.e., start on a page boundary). Given this restriction, the compiler knows that direct accesses to the first 64 words of a blocked variable are valid using the same DP. A combination of data blocking and knowledge about relative placement of variables allows the compiler to ascertain whether an existing DP is valid for a new direct access and issue DP loads only when necessary. Reducing the number of DP-loads saves code size and improves performance. However, the compiler must adjust placement of variables to satisfy blocking requirements. In particular, the compiler must align variables that span multiple pages to the start of a new page. This restriction on the placement of blocked variables can introduce holes within data sections and deciding the order to allocate a set of variables to minimize holes is a difficult problem. Currently, the C2000<sup>TM</sup> MCU compiler attempts to limit the holes by sorting variables by increasing size. If you examine the map file of a program with global variables, you will observe that smaller variables get allocated before larger ones. Note that the assembler sets the layout of variables within a section. The linker is unaware of these holes; therefore, it is unable to fill the holes.</p>
<p>In addition, the linker must also respect section blocking requirements when placing blocked sections in memory. Sections containing blocked variables must be blocked. That is, the section must either fit entirely within a data page, or be page-aligned. Blocking relevant sections guarantees the validity of assumptions that the compiler made while optimizing DP-loads. That is, the variables contained within blocked sections will not span a page boundary except when the variable is larger than a page. Blocked sections can cause a linker placement failure even when you have sufficient memory.</p>
<p>The C2000 MCU compiler performs data blocking and DP-load optimization by default. You can verify that a variable or section is blocked by examining the .bss and .usect directives in the assembly listing file and checking that the blocking flag is set. The blocking flag is documented in the <a href="http://www.ti.com/lit/pdf/spru513" title="tidoc:spru513">TMS320C28x Assembly Language Tools User's Guide</a> under "Uninitialized Sections".</p>
<p>While blocking offers opportunities for optimization of DP-loads, the data memory penalties might be too costly for your application. In such cases, we offer the following options for limiting the degree of data blocking or disabling it altogether:</p>
<ol>
<li>Use #pragma DATA_SECTION or #pragma SET_DATA_SECTION to place one or more global variables in separate user-defined sections. Variables in the same section will still be blocked and can benefit from DP-load optimization. The pragmas must appear at every definition and declaration of the variables that they apply to. Keep in mind, however, that DP-load optimization is not possible across sections. This approach will allow you decide on how much optimization/blocking is performed and give the linker better opportunities to reduce fragmentation. For examples on using the DATA_SECTION and SET_DATA_SECTION pragmas, please see the <a href="http://www.ti.com/lit/pdf/spru514">TMS320C28x Optimizing C/C++ Compiler User’s Guide</a>.</li>
<li>Group global variables in a structure. While the structure will still be blocked, the compiler is not allowed to introduce additional holes within the structure and DP-load optimization will still be performed for accesses to elements of the structure.</li>
<li>Use the --disable_dp_load_opt compiler option to disable data blocking and DP-load optimization for your files, or a subset of them containing data that will likely not benefit from DP-load optimization. For example, most array accesses are of the form “array[i]”, which are indirect accesses that do not use the DP and will not benefit from DP-load optimization. Accesses to constant locations such as “array [16]” use the DP, but such accesses are rare in practice. Therefore, placing arrays in a separate file that is built with --disable_dp_load_opt can reduce holes without impacting performance. Accesses to scalars and structures continue to be optimized.</li>
</ol>
<p>Linker placement failures that occur when placing blocked sections may be resolved by examining the placement of memory regions and sections in the application’s linker command file. Recall that a blocked section must either fit within a page or be page aligned. Therefore, placement errors might occur when the start address and size of memory regions do not take into account holes that might be introduced by blocked sections. In such cases, try adjusting the start address of the relevant memory regions to account for blocked sections. </p>
<p style="margin-left:60px;"><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-5.JPG"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/Figure-5.JPG" width="644" height="376" alt=" " style="display:block;margin-left:auto;margin-right:auto;" /></a><strong>Figure 5a: .dataBufferA must be page aligned and will not fit in RegionA Figure 5b: RegionA is page aligned. .dataBufferA fits in RegionA</strong></p>
<p>Please post questions about data blocking in the <a href="/support/development_tools/compiler/">TI E2E C/C++ Compiler Forum</a>. </p>
<br clear="all" /><hr align="left" />
<div>
<p><a>[1]</a> Alignment specifications for variables and sections could also cause these issues.</p>
</div>
</div><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=669249&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Dunni Aribukihttps://e2e.ti.com:443/members/1507176Using OpenCLTM to offload to C66x DSPs on Sitara™ AM572x processorshttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/using-opencltm-to-offload-to-c66x-dsps-on-sitara-am572x-processors2016-10-07T19:06:00Z2016-10-07T19:06:00Z<div><b>Other Parts Discussed in Post: </b><a href="https://www.ti.com/tool/MATHLIB" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">MATHLIB</a>, <a href="https://www.ti.com/product/AM5728" class="internal-link folder product" title="Link to Product Folder" target="_blank">AM5728</a>, <a href="https://www.ti.com/tool/PROCESSOR-SDK-AM57X" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">PROCESSOR-SDK-AM57X</a></div><p>Customers traditionally approach the programming of complex ARM® + C66x digital signal processor (DSP) systems on chip (SoCs) such as TI’s Sitara™ AM57x SoC by focusing on manually partitioning the application across the ARM cores and DSPs and hand-optimizing the appropriate sections of the application for the given core. This approach tends to yield the maximum entitlement but has drawbacks; –the resulting application cannot be easily ported from one TI SoC to another and time to market increases because programmers need to manage dispatch, communication and synchronization mechanisms.</p>
<p>To provide customers an alternative, TI has enabled industry-standard heterogeneous multicore programming models such as OpenCL and OpenMP® offload on ARM + DSP SoCs. This post will focus on OpenCL and TI’s implementation of it. In a later post, I will write about OpenMP Offload.</p>
<p><span style="font-size:2em;">What is OpenCL?</span></p>
<p>OpenCL is a framework for expressing programs where parallel computation is dispatched across heterogeneous devices. It is an open, royalty-free standard managed by Khronos consortium. On a heterogeneous SoC, OpenCL views one of the programmable cores as a host and the other cores as devices. For example, on a Sitara AM572x SoC, the host is the ARM® Cortex®-A15 cluster running SMP/Linux or TI-RTOS and the device is the C6xx DSP cluster. The application running on the host (i.e. the host program) manages execution of code (kernels) on the device and is also responsible for making data available to the device. A device consists of one or more compute units. On Sitara AM572x SoCs, each C66x DSP is a compute unit.</p>
<p>The OpenCL runtime consists of two components: (1) An API for the host program to create and submit kernels for execution and (2) A cross-platform language for expressing kernels – OpenCL C – which is based on C99 C with some additions and restrictions</p>
<p>OpenCL supports both data parallel and task parallel programming paradigms. Data parallel execution parallelizes the execution across compute units on a device. Task parallel execution enables asynchronous dispatch of tasks to each compute unit</p>
<p><span style="font-size:2em;">TI’s implementation of OpenCL</span></p>
<p>Here are a few key features of TI’s OpenCL implementation for Sitara AM572x SoCs:</p>
<ul>
<li>The host is the dual ARM Cortex-A15 cluster running SMP/Linux</li>
<li>One device with either one or two C66x DSP cores (configurable via an environment variable)</li>
<li>The compute unit is a single C66x DSP</li>
<li>OpenCL implementation conformant to v1.1 (full profile)</li>
<li>No support for images, ‘double’ supported as an extension, not included in conformance submission</li>
</ul>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/tools-insider.JPG"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/tools-insider.JPG" width="753" height="369" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p><span style="font-size:2em;">TI’s extensions to OpenCL</span></p>
<p>TI has enabled various extensions to OpenCL to take advantage of features on its SoCs, leverage the existing C66x DSP code base and make them easier to use. The following is a list of some examples of such extensions:</p>
<ul>
<li>Calling standard C code from OpenCL C code, including code with OpenMP pragmas</li>
<li>On-chip global buffers using OCMC RAM
<ul>
<li>__malloc_ddr and __malloc_msmc substitutes for malloc (like OpenCL 2.0 SVMalloc)</li>
<li>Enables zero copy buffer capability</li>
</ul>
</li>
<li>Support for C66x DSP intrinsic functions in OpenCL, like _dcmpy, _dotpsu4, etc</li>
<li>Printf from OpenCL C (similar to OpenCL 1.2 printf capability)</li>
<li>Access to EDMA functionality from OpenCL C using the EdmaMgr API functions</li>
<li>Cache resize and control operations for the DSP’s L1D and L2 caches from OpenCL C</li>
<li>Additional OpenCL C built-in functions, __clock, __cycle_delay etc.</li>
</ul>
<p><span style="font-size:2em;">Why use OpenCL?</span></p>
<p>Using a standard approach to programming heterogeneous SoCs simplifies programming; it allows the programmer to use standard, well-documented APIs to handle the mechanics of dispatching code and data to the DSPs and focus on optimizing the dispatched code. Other benefits include:</p>
<ul>
<li>Seamless migration of applications between TI SoCs – e.g. Take an OpenCL application written for a 66AK2H SoC with eight C66x DSP cores and run it on an AM572x SoC with two C66x DSP cores with only a recompile.</li>
<li>TI extensions to OpenCL enable programmers to leverage optimized TI-provided DSP libraries such as dsplib, mathlib, imagelib</li>
<li>Use the DSPs to offload computation within open source libraries such as OpenCV</li>
</ul>
<p><span style="font-size:2em;">When does OpenCL apply?</span></p>
<p>OpenCL was designed for a scenario in which one of the cores on the SoC is designated the host. This core runs the OpenCL API and manages execution of kernels on the devices. As described earlier, the host on an AM57x SoC is an ARM Cortex-A15 core running Linux or TI-RTOS. All orchestration of control and data is done by the host. If the customer’s use case fits within the host-centric model, OpenCL is an option to offload computation to the DSPs.</p>
<p>Other considerations include:</p>
<ul>
<li>Can the application take advantage of TI libraries optimized using OpenCL to dispatch to the DSP? Examples include OpenCV and Linear Algebra libraries</li>
<li>Is the OpenCL execution and memory model a good fit for the region of application code dispatched to the device?</li>
<li>What is the nature of existing code base –is it already written to use OpenCL for dispatch?</li>
<li>Are there real-time requirements with respect to computation offloaded to the DSP? OpenCL does not offer any real time guarantees</li>
<li>Programmer expertise and preference: using OpenCL APIs for dispatch vs. TI inter-processor communication (IPC)</li>
<li>Can OpenCL be used to get to a quick prototype for offloading code to the DSPs?</li>
<li>Are the necessary OpenCL features supported by TI’s implementation? (E.g. TI OpenCL does not support some optional OpenCL v1.1 features such as images)</li>
</ul>
<p><span style="font-size:2em;">How can I get started?</span></p>
<p>OpenCL on Sitara AM572x SoCs is available via TI’s Processor SDK Linux. Download and install the SDK following the instructions listed at this <a href="http://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.html">link</a>. Refer to the <a href="http://software-dl.ti.com/mctools/esd/docs/opencl/index.html">OpenCL User Guide</a> for instructions on building and running OpenCL examples.</p>
<p><span style="font-size:200%;"> References</span></p>
<ol>
<li>TI’s Sitara AM5728 SoC: <a href="http://www.ti.com/product/AM5728">http://www.ti.com/product/AM5728</a></li>
<li>TI Processor SDK Linux for AM57x SoCs: http://www.ti.com/tool/processor-sdk-am57x</li>
<li>TI OpenCL User Guide: <a href="http://software-dl.ti.com/mctools/esd/docs/opencl/index.html">http://software-dl.ti.com/mctools/esd/docs/opencl/index.html</a></li>
<li>Khronos OpenCL: <a href="https://www.khronos.org/opencl/">https://www.khronos.org/opencl/</a></li>
<li>OpenMP Offload User Guide: <a href="http://software-dl.ti.com/mctools/esd/docs/openmpacc/index.html">http://software-dl.ti.com/mctools/esd/docs/openmpacc/index.html</a></li>
<li>TI Signal processing libraries: <a href="http://www.ti.com/lsds/ti/processors/technology/libraries/signal-processing-libraries.page">http://www.ti.com/lsds/ti/processors/technology/libraries/signal-processing-libraries.page</a></li>
<li>TI OpenCV library: <a href="http://www.ti.com/lsds/ti/processors/technology/libraries/open-cv-libraries.page">http://www.ti.com/lsds/ti/processors/technology/libraries/open-cv-libraries.page</a></li>
<li>TI Linear Algebra library: <a href="http://www.ti.com/lsds/ti/processors/technology/libraries/linear-algebra-libraries.page">http://www.ti.com/lsds/ti/processors/technology/libraries/linear-algebra-libraries.page</a></li>
</ol><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=669118&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Ajay Jayarajhttps://e2e.ti.com:443/members/256126Get a FREE Code Composer Studio license with select TI kits and debug probeshttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/get-a-complementary-code-composer-studio-license-with-selected-launchpads-and-debug-probes2016-09-21T16:07:00Z2016-09-21T16:07:00Z<p>We are running an exclusive promotion on the TI Store for a full <a href="http://www.ti.com/tool/ccstudio?DCMP=dsp_ccs_v4&HQS=ccs">Code Composer Studio™ integrated development environment (IDE)</a> node-locked license (a $445 value) bundled with select TI LaunchPad<sup>TM </sup>development kits and debug probes at no additional charge.</p>
<p>This is a full CCS IDE license and is not code-size limited or tied to a particular development board.</p>
<p>The list of bundles available with this promotion will change week to week, so check back often. To see the currently available bundles just search the TI Store for ‘CCS-PROMO,’ or <a href="https://store.ti.com/Search.aspx?k=CCS-PROMO&pt=-1">click here</a>.</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4426.TI-store-banner.png"><img src="/resized-image/__size/500x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4426.TI-store-banner.png" style="display:block;margin-left:auto;margin-right:auto;" width="657" height="163" alt=" " /></a></p>
<p>To get us started, there are already three LaunchPad development kit and CCS bundles available. Additional LaunchPad kit and debug probe bundles will be made available.</p>
<ul>
<li><a href="https://store.ti.com/MSP430FR5994-LaunchPad-Development-Kit-with-Code-Composer-Studio-Promotion-P51095.aspx">MSP430FR5994 LaunchPad development kit</a></li>
<li><a href="https://store.ti.com/MSP430G2-LaunchPad-Development-Kit-With-Code-Composer-Studio-Promotion-P50861.aspx">MSP430G2 LaunchPad development kit</a></li>
<li><a href="https://store.ti.com/MSP432P401R-LaunchPad-Development-Kit-with-Code-Composer-Studio-Promotion-P51093.aspx">MSP432P401R LaunchPad development kit </a></li>
</ul>
<p>Purchase your LaunchPad and CCS bundle today!</p>
<p></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=669027&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">JohnShttps://e2e.ti.com:443/members/103815 Code Composer Studio tricks that even Ki-Soo Lee himself doesn't knowhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/5-code-composer-studio-tricks-that-even-ki-soo-lee-himself-doesn-39-t-know2016-04-25T17:04:00Z2016-04-25T17:04:00Z<p><em>Guest blog authored by <a href="/members/3650597" class="internal-link view-user-profile">Jan Cumps</a> in celebration of <span style="text-decoration:underline;"><span style="color:#ff0000;text-decoration:underline;"><a href="/group/helpcentral/b/weblog/archive/2016/04/19/ki-soo-lee-amp-code-composer-studio-day-thank-you-from-all-of-the-ti-e2e-community"><span style="color:#ff0000;text-decoration:underline;">Ki-Soo Lee Day</span></a></span></span> Monday, April 25th. <a href="/blogs_/archives/b/toolsinsider/archive/tags/KiSooLeeDay" class="tag hash-tag" data-tags="KiSooLeeDay">#KiSooLeeDay</a><br /></em></p>
<p><span style="font-size:200%;color:#000000;"><strong>1. Use the Git plug-in</strong></span></p>
<p><em><img src="/resized-image/__size/636x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan1_2D00_636.png" alt=" " /><br /></em></p>
<p><span style="color:#000000;">Software geeks have known it forever that version control is your friend. And this friend is available to firmware gurus too: The Eclipse Git Team Provider.</span></p>
<p><span style="color:#000000;">Get yourself a GitHub account and you’ll never ever have to fear again to start that refactoring exercise that you know your project will need.</span></p>
<hr style="height:1px;" />
<p><span style="font-size:200%;color:#000000;"><strong>2. Install a PDF viewer</strong></span></p>
<p><img src="/resized-image/__size/644x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan2_2D00_644.png" alt=" " /></p>
<p><span style="color:#000000;">It’s nice to view your datasheets from within the IDE. From there you can create a folder named documentation under your project root (and exclude it from build). Then add a link to all the documents relevant to the project. Use the New --> File --> Advanced --> Link to File in the File System option to hook a link to the files into the project.</span></p>
<p><span style="color:#000000;">Next, install a PDF viewer. There are several options available. I use PDF4Eclipse. Double-click on the document in the Project explorer and it opens in the editor pane.</span></p>
<hr style="height:1px;" />
<p><span style="font-size:200%;color:#000000;"><strong>3. Use the todo/task view</strong></span></p>
<p><img src="/resized-image/__size/643x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan3_2D00_643.png" alt=" " /></p>
<p><span style="color:#000000;">This one is very simple to perform. To execute it: When there something in your code that needs attention later, just add a todo comment.</span></p>
<p><span style="color:#000000;"><strong>Example:</strong></span></p>
<p><strong><img src="/resized-image/__size/689x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan3_2D00_689.png" alt=" " /><br /></strong></p>
<p><span style="color:#000000;">Then add the task view to your IDE via View --> Other --> Generic --> Task.</span></p>
<hr style="height:1px;" />
<p><span style="font-size:200%;color:#000000;"><strong>4. Use the graph view to show memory content</strong></span></p>
<p><img src="/resized-image/__size/643x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan4_2D00_643.png" alt=" " /></p>
<p><span style="color:#000000;">To see your memory content as a graph (very useful if you have an array of samples), right click on the array in debug mode --> from Variables or Expression Window --> and select Graph.</span></p>
<p><span style="color:#000000;">Additional details are in the CCS Help. Go to Help --> Search and type "graph" in the search box.</span></p>
<hr style="height:1px;" />
<p><span style="font-size:200%;color:#000000;"><strong>5. Use the telnet client</strong></span></p>
<p><img src="/resized-image/__size/642x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/jan5_2D00_642.png" alt=" " /></p>
<p><span style="color:#000000;">There's a terminal emulator inside Code Composer Studio. It's available via View --> Other --> Terminal.</span></p>
<p><span style="color:#000000;">This is extremely handy as you can now read output and send input while debugging. You don’t have to leave the editor.</span></p>
<hr style="height:1px;" />
<p><span style="font-size:200%;color:#000000;"><em><strong>Happy Ki-Soo Lee Day!</strong></em></span></p>
<p><span style="color:#000000;"><br /><a href="/group/helpcentral/b/weblog/archive/2016/04/19/ki-soo-lee-amp-code-composer-studio-day-thank-you-from-all-of-the-ti-e2e-community"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/ki_2D00_7.png" alt=" " /></a><br /></span></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668616&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Jan Cumpshttps://e2e.ti.com:443/members/3650597From the Experts: Debugging and Optimizationhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/from-the-experts-debugging-and-optimization2016-04-15T17:00:00Z2016-04-15T17:00:00Z<p><b>Does debug affect optimization? Does optimization affect debug?</b></p>
<p>A compiler’s main job is to generate instructions and data directives that implement your C/C++ source code. However, compilers have additional responsibilities. For example, compilers act as code-optimization tools, performing program transformations that improve the execution time and reduce the memory footprint of your source programs. Compilers are also responsible for emitting debug information used by debuggers to keep track of things like where variables are located and how to map an instruction address to a C source line.</p>
<p>The <i>--opt_level=[0-3]</i> option to the compiler is the easiest way to enable optimizations in TI compilers. While many compilers require the use of an option, such as –g in GCC, to enable debugging, TI compilers generate full debug information by default. For historical reasons, we accept a --symdebug:dwarf option[1] , but it is not required for debug information.</p>
<p>In the following sections, we will examine what effect debug has on optimization, and what effect optimization has on debug when compiling your source programs with Texas Instruments’ compilers.</p>
<p><b>Effect of debug on optimization</b></p>
<p>In TI’s compilers, generation of debug information has no effect on compiler optimizations. In other words, the performance and memory footprint of a given application compiled using our tools are not affected by the presence of debug information. For this reason, if you use TI’s Code Composer Studio™ (CCS), you will observe that full symbolic debug information is generated by default for both Debug and Release build configurations.</p>
<p>While debug information has no effect on overall system memory footprint, it does add to the size of an object file. If object file size is a concern, and debugging is not needed, use <i>--symdebug:none</i> to disable generation of debug information.</p>
<div>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/change_5F00_debug_5F00_settings_5F00_cropped.png" target="_blank"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/change_5F00_debug_5F00_settings_5F00_cropped.png" style="display:block;margin-left:auto;margin-right:auto;" width="717" height="398" alt=" " /></a></p>
<p><b>Effect of optimization on debug</b></p>
<p>During optimization, the compiler makes transformations to your program to improve its execution time, memory footprint, power consumption, or a combination of these. These transformations significantly change the layout of your code and make it difficult, or impossible, for the debugger to identify the source code that corresponds to a set of instructions.</p>
<p>In general, the higher the level of optimization that is applied, the harder it is to debug the program. This is because higher levels of optimization enable more transformations and apply to broader granularities or scopes of the program. Optimizations at levels 0 and 1 are applied to individual statements or blocks of code within functions, level 2 enables optimizations across blocks of code within a function, level 3 enables optimizations across functions within a file, and level 4 enables optimizations across files. Since transformations that occur at higher levels are usually more widespread, it is harder for the debugger to map the resulting code to the original source program.</p>
<p>Another compiler option, <i>--opt_for_speed=[0-5]</i>, enables optimizations in the context of competing code size and performance tradeoffs. The --<i>opt_for_speed=0</i> option attempts to improve the code size at a high risk of worsening code performance, while <i>opt_for_speed=5</i> is geared toward improving the code performance with a high risk of worsening code size. The effects of the use of <i>--opt_for_speed</i> on your debug experience are not as clear as the effects of increasing <i>--opt_level</i> settings, since each <i>--opt_for_speed</i> level enables or disables a complex set of transformations. In most cases, the compiler will perform more aggressive inlining at higher <i>--opt_for_speed</i> levels which might impact debugging.</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/change_5F00_opt_5F00_level.png" target="_blank"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/change_5F00_opt_5F00_level.png" style="display:block;margin-left:auto;margin-right:auto;" width="717" height="443" alt=" " /></a></p>
<p>When optimization limits your ease of debugging, one option is to try lowering the level of optimization to the lowest level of optimization that meets your constraints on code speed, size, and power (see figure above). If the optimization level you need to meet your constraints is still too hard to debug, consider lowering the optimization level for just the one file you need to debug, and not the whole system. By lowering the optimization level for just one file, it is likely you will continue to meet your system constraints, while making it easier to debug that file.</p>
<p>Another option when debugging optimized files is to drop down to assembly language to see what is really going on. The Disassembly view in CCS allows you to step through the actual instructions that are executing. While the assembly language is a lot more verbose and harder to understand, it is an accurate representation of what is executing.</p>
<p><b>Summary</b></p>
<p>TI compilers generate full debug information by default. The presence of debug information has no impact on the compiler’s ability to perform optimizations. Our debuggers allow you to debug optimized programs; however, compiler optimizations can affect the ease of debugging. To counteract this, try reducing the optimization level.</p>
<p>For more information about the tradeoffs of debug versus optimization when using our compiler tools, visit <a href="http://processors.wiki.ti.com/index.php/Debug_versus_Optimization_Tradeoff" target="_blank">this wiki topic.</a> You may also refer to our <a href="http://processors.wiki.ti.com/index.php/TI_Compiler_Information#Compiler_Manuals" target="_blank">various compiler manuals</a> to learn more about optimization options and debugging optimized code.</p>
<p><b>Read more ‘From the Expert’ blogs</b></p>
<p>- <a href="/blogs_/b/toolsinsider/archive/2016/01/05/from-the-experts-accessing-files-and-libraries-from-a-linker-command-file" target="_blank">Accessing files and libraries from a linker command file (LCF) </a></p>
<p>- <a href="/blogs_/b/toolsinsider/archive/2015/12/11/helpful-tips-executing-code-from-ram" target="_blank">Executing code from RAM using TI compilers</a></p>
<p>Footnotes:</p>
<p>[1] Using the <i>--symdebug:dwarf</i> option in TI’s ARM compiler lowers the default optimization level. More specifically, our ARM compiler defaults to <i>--opt_level=3</i> if no optimization level is specified. If <i>--symdebug:dwarf</i> is used, the default optimization level changes to <i>--opt_level=off</i> (i.e., optimization is disabled). See the compiler manual for your specific compiler for details on interactions between <i>–symdebug:dwarf</i> and default optimization levels.</p>
<p></p>
</div><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668581&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Dunni Aribukihttps://e2e.ti.com:443/members/1507176From the Experts: Accessing files and libraries from a linker command file (LCF)https://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/from-the-experts-accessing-files-and-libraries-from-a-linker-command-file2016-01-05T20:00:00Z2016-01-05T20:00:00Z<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/5228.ccs.jpg"><img src="/resized-image/__size/315x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/5228.ccs.jpg" style="float:right;" alt=" " /></a>Many applications built with TI Code Generation Tools utilize custom linker command files (or LCFs) to control the placement of code and data in target memory. For example, you may want to collect a group of commonly used utility functions into a specific area of target memory. This is simple to do using the available LCF syntax to reference the desired object file or library. However, a problem that many developers run into when they try to do this is a linker generated “file not found” error when accessing an object file or library from inside the LCF. Most often, this error occurs because the syntax used to access the file on the linker command-line does not match the syntax that is used to access the same file in the LCF.</p>
<p>Expanding on the example suggested earlier, imagine that you have an object library, util.lib, which contains definitions of commonly used utility functions that you want to be loaded into a memory area called “UTILMEM”. Assume also that all the utility functions are defined in .text sections in the object file members of util.lib. In your custom LCF, mylnk.cmd, you can control the placement of the utility functions as follows:</p>
<table border="0" style="border-color:#bdbdbd;border-width:0px;width:423px;height:113px;background-color:#bdbdbd;">
<tbody>
<tr>
<td><span style="font-family:'courier new', courier;">SECTIONS</span><br /><span style="font-family:'courier new', courier;"> {</span><br /><span style="font-family:'courier new', courier;"> …</span><br /><span style="font-family:'courier new', courier;"> .utils: { util.lib(.text) } > UTILMEM</span><br /><span style="font-family:'courier new', courier;"> …</span><br /><span style="font-family:'courier new', courier;"> }</span></td>
</tr>
</tbody>
</table>
<p>Now assume that the util.lib object library gets put into a sub-directory called “lib” relative to where you are building the application. In order to gain access to util.lib from the build command-line, you can use a combination of the <b>–i</b> (or –-search_path) and <b>–l</b> (or –-library) options to set up a directory search path which the linker can use to find the util.lib library:</p>
<table border="0" style="border-color:#bdbdbd;border-width:0px;width:867px;height:62px;background-color:#bdbdbd;">
<tbody>
<tr>
<td>
<p><span style="font-family:'courier new', courier;">%> cl6x <compile options/files> -z <span style="color:#ff0000;">–i ./lib –l util.lib mylnk.cmd</span> <link options/files></span></p>
</td>
</tr>
</tbody>
</table>
<p>In essence, the linker has a few different ways of opening files:The <b>–i</b> option adds the lib sub-directory to the directory search path and the <b>–l</b> option instructs the linker to look through the directories in the directory search path to find the util.lib library. However, if you do not update the reference to util.lib in mylnk.cmd, the linker will fail to find the util.lib library and generate a “file not found” error. The reason is that when the linker encounters the reference to util.lib inside the SECTIONS directive, there is no <b>–l</b> option preceding the reference. Therefore, the linker tries to open util.lib in the current working directory.</p>
<ul>
<li>If there is a path included in the file reference, the linker will look for the file in the specified location. For an absolute path, the linker will try to open the file in the specified directory. For a relative path, the linker will follow the specified path starting from the current working directory and try to open the file at that location.</li>
<li>If there is no path included in the file reference, the linker will try to open the file in the current working directory.</li>
<li>If a <b>–l</b> (or –-library) option precedes the file reference, then the linker will try to open the referenced file in the first directory in the directory search path where the file is found. The directory search path is set up via <b>–i</b> (or –-search_path) options on the command-line or within the Code Composer Studio (CCS) options dialog box (if you are building your application in CCS) and environment variables (like C6X_C_DIR, TMS470_C_DIR, C2000_C_DIR, or MSP430_C_DIR depending on what target processor your application is designed to run on). Please see the appropriate Compiler User Guide or the Assembly Language Tools User Guide for more details on using environment variables to help define the directory search path.</li>
</ul>
<p><i><strong>Note:</strong> As long as a file is referenced in a consistent manner on the command line and throughout any applicable LCFs, the linker should be able to find and open that file.</i><i><br /></i></p>
<p>Returning to our example, you can insert a <b>–l</b> option in front of the reference to util.lib in mylnk.cmd to ensure that the linker will find and open the util.lib library when the application is built:</p>
<table border="0" style="border-color:#bdbdbd;border-width:0px;width:423px;height:113px;background-color:#bdbdbd;">
<tbody>
<tr>
<td><span style="font-family:'courier new', courier;">SECTIONS</span><br /><span style="font-family:'courier new', courier;"> {</span><br /><span style="font-family:'courier new', courier;"> …</span><br /><span style="font-family:'courier new', courier;"> .utils: { <span style="color:#ff0000;">-l util.lib(.text)</span> } > UTILMEM</span><br /><span style="font-family:'courier new', courier;"> …</span><br /><span style="font-family:'courier new', courier;"> }</span></td>
</tr>
</tbody>
</table>
<p>Another benefit to using the <b>–l</b> option when referencing a file from within an LCF is that if the location of the referenced file changes, you can modify the directory search path to incorporate the new location of the file (by modifying an existing <b>–i</b> option or adding a new one on the command line, for example) without having to modify the LCF.</p>
<p>For more information about linker command files and linker command file syntax:</p>
<ul>
<li>Visit the relevant Assembly Language Tools User Guide from <a href="http://processors.wiki.ti.com/index.php/TI_Compiler_Information#Compiler_Manuals">here</a> (especially the section entitled “Linker Command Files”).</li>
<li>Visit the <a href="http://processors.wiki.ti.com/index.php/Linker_Command_File_Primer">Linker Command File Primer</a> wiki article.</li>
</ul>
<p> </p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668177&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Todd Sniderhttps://e2e.ti.com:443/members/27743Don’t miss out: New product demos featured at SPS IPC Drives 2015https://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/don-t-miss-out-new-product-demos-featured-at-sps-ipc-drives-20152015-12-18T14:00:00Z2015-12-18T14:00:00Z<div><b>Other Parts Discussed in Post: </b><a href="https://www.ti.com/tool/DESIGNDRIVE" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">DESIGNDRIVE</a>, <a href="https://www.ti.com/tool/CONTROLSUITE" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">CONTROLSUITE</a>, <a href="https://www.ti.com/product/DRV8305" class="internal-link folder product" title="Link to Product Folder" target="_blank">DRV8305</a>, <a href="https://www.ti.com/product/DRV8301" class="internal-link folder product" title="Link to Product Folder" target="_blank">DRV8301</a></div><p>On November 24-26, the C2000™ microcontroller (MCU) team exhibited at the SPS IPC Drives 2015 show in Nuremburg, Germany. The show boasted more than 64,000 visitors and 1,600 exhibitors all focused on delivering solutions for the Smart Factory environment.</p>
<p>On the exhibition floor, the team showcased several new demonstrations including the new <a href="http://www.ti.com/epd-mcu-c2x-f28379-toolsinsider-pf-ddpm-wwe">DesignDRIVE Position Manager</a> technology, the C2000 <a href="http://www.ti.com/epd-mcu-c2x-f28379-toolsinsider-pf-tms320f28379d-wwe">F28379D</a> and <a href="http://www.ti.com/epd-mcu-c2x-f28379-toolsinsider-pf-tms320f28379s-wwe">F28379S</a> MCUs and the latest version of the DesignDRIVE development kit – the IDDK v2.2.1. Further, the DesignDRIVE exhibitors peeked into the future by demonstrating several new DesignDRIVE technologies based on the C2000 Delfino™ MCU LaunchPad™ development kit.</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4442.DD-PM-demo.jpg"><img src="/resized-image/__size/300x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/4442.DD-PM-demo.jpg" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p>Having just announced the DesignDRIVE Position Manager technology on November 19, the team created a triple-sensored servo drive example. Mounted in one rack was a servo motor coupled with an incremental encoder, a SIN/COS transducer, and EnDat 2.2 and BiSS-C rotary absolute encoders. At any given time, three position sensors feed the shaft angle back to the DesignDRIVE-based controller. The user can select between either the EnDat or BiSS sensors on-the-fly. The system is able to adapt to the absolute encoder selected. It’s worth noting that a closed loop FOC-based position control example, which leverages a HEIDENHAIN ROC 425 EnDat encoder, is available now as part of the latest C2000 MCU controlSUITE™ software release. This project is built upon the <a href="http://www.ti.com/epd-mcu-c2x-f28379-toolsinsider-evm-designdrivekit-wwe">DesignDRIVE development kit</a> and will work with both the v2.2 (green) and the v2.2.1 (blue) versions.</p>
<p></p>
<p align="center"><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0333.DesignDRIVE-PM-demo.JPG"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/0333.DesignDRIVE-PM-demo.JPG" alt=" " /></a><b> </b></p>
<p align="center"><b>DesignDRIVE Position Manager technology demonstration</b></p>
<p align="center"> </p>
<p>Looking to future technology and kit releases in 2016, our exhibit also included three new demonstrations using the <a href="http://www.ti.com/epd-mcu-c2x-f28379-toolsinsider-evm-delfinolaunchpad-wwe">Delfino MCU LaunchPad development kit</a> and various TI BoosterPack plug-in modules. With the power and autonomy of a dual core real-time DSP/MCU like the F28379D, whose on-chip ADCs have the capability to work asynchronously to each other (on completely different time-bases); two completely independent control loops can be managed on the same device. Imagine using one DSP core (and CLA) to manage your servo motor control while the other DSP manages the creation of the DC-Link power bus feeding your motor inverter; each real-time control loop sensing and actuating independently to the other!</p>
<p> One of the interesting new features of the Delfino MCU LaunchPad development kit is the addition of a second BoosterPack connector. At the SPS IPC Drives show, a demonstration of the DesignDRIVE LaunchPad kit utilized this capability by adding a DRV8301 BoosterPack and a DRV8305 BoosterPack to a single Delfino MCU LaunchPad kit. Both BoosterPacks are capable of driving low-voltage servo motors. The DesignDRIVE demonstration showed two servo motors executing completely independent motion profiles from a single Delfino MCU LaunchPad!</p>
<p> <a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/3056.LaunchPad-demo.JPG"><img src="/resized-image/__size/600x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/3056.LaunchPad-demo.JPG" style="display:block;margin-left:auto;margin-right:auto;" alt=" " /></a></p>
<p align="center"><b>C2000™ MCU LaunchPad™ development kit demonstrations</b></p>
<p> </p>
<p>The SPS IPC Drives 2015 exhibition was a great success. It was the perfect event for the public unveiling of DesignDRIVE Position Manager technology as well as showcasing upcoming DesignDRIVE technology releases, which are based on the LaunchPad development kit and BoosterPack plug-in module combinations. These kits will put the evaluation of new technologies in the reach of more industrial drives developers. The full-featured development enabled by the DesignDRIVE development kit will also be hosting these new technologies, just as it does for DesignDRIVE Position Manager today.</p>
<p>To learn more about these demonstrations, watch the overview video below, or click <a href="http://www.ti.com/ww/eu/sps-ipc-drives-2015/">here</a>.</p>
<p></p>
<p><a href="https://www.youtube.com/watch?v=qP9t2NnKoi8&amp;feature=em-upload_owner">www.youtube.com/watch</a></p>
<p></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668169&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Brian Fortmanhttps://e2e.ti.com:443/members/15910Don’t miss out on the top training videos of 2015https://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/don-t-miss-out-on-the-top-training-videos-of-20152015-12-16T13:00:00Z2015-12-16T13:00:00Z<p>The year is winding down and we want to help you get a few things crossed off on your to do list. To help, below we captured the top series and/or videos you must watch before 2016. Happy developing!</p>
<p> </p>
<ul>
<li>Built for real-time control, learn how to design with C2000™ MCUs and their many peripherals with our <a href="https://training.ti.com/designing-c2000-f2807x-and-f2837x-microcontroller-family">C2000 F2807x and F2837x MCU family in-depth training.</a></li>
<li>Developing for motor control in 2016? Be sure to watch this <a href="https://training.ti.com/introduction-motors-motor-control-part-1-introduction">Introduction to Motors & Motor Control</a> before you begin.</li>
<li>Getting started with C2000 MCU-based digital power applications? Watch this <a href="https://training.ti.com/c2000-digital-power-control-and-implementation">Digital Power Control and Implementation training video</a> to build better applications in 2016.</li>
<li>Have you been formally introduced to our capacitive touch MSP430™ microcontroller (MCU) with CapTIvate™ technology? Learn more with our <a href="https://training.ti.com/captivate-training-series?DCMP=captivate&HQS=epd-mcu-msp-captivate-blog-tr-trainingblog-wwe">CapTIvate technology training series</a>.</li>
<li>MSP432™ microcontrollers are low-power and high performance. Learn more on how you can enhance your product with our 32-bit ARM® Cortex®-M4F with our <a href="https://training.ti.com/msp432%E2%84%A2-low-power-high-performance-mcus-training-series">MSP432 MCU training series</a>.</li>
<li>In-field firmware updates are becoming an increasingly popular feature supported on products that are deployed to the field; however, this feature is also very commonly exploited by attackers, and if vulnerable, can compromise the security of the system. Learn more with our <a href="https://training.ti.com/msp-crypto-bootloader-training-series">MSP MCU Crypto-Bootloader training series</a>.</li>
</ul>
<p>We'll continue to keep you updated on MSP and C2000 MCU products in the coming year. Best wishes for a prosperous and productive 2016!</p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668164&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Amy Halehttps://e2e.ti.com:443/members/4420273From the Experts: Executing code from RAM using TI compilershttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/helpful-tips-executing-code-from-ram2015-12-11T16:15:00Z2015-12-11T16:15:00Z<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/ccs.jpg"><img src="/resized-image/__size/300x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/ccs.jpg" style="float:right;" alt=" " /></a>Many TI processors and microcontrollers (MCUs) store code in flash memory and then execute out of that same flash memory. When the CPU core is running at full frequency, wait states must be introduced on reads from flash memory. This can have a significant performance impact on the application. RAM typically operates with 0 wait states, even at full frequency. It can be very beneficial for performance-critical functions to execute from RAM instead of flash. TI’s <a href="http://www.ti.com/lsds/ti/tools-software/compilers.page">MCU compilers</a> for ARM-based MCUs, MSP430™ MCUs and C28x MCUs, starting with version 15.9.0.STS, provide a simple mechanism to accomplish this.</p>
<p>In version 15.9.0.STS we added support for the <b>ramfunc</b> attribute.</p>
<table border="0" style="border-color:#bdbdbd;border-width:0px;width:158px;height:36px;background-color:#bdbdbd;">
<tbody>
<tr>
<td>__attribute__((ramfunc)) <br /> void f(void) { ... }</td>
</tr>
</tbody>
</table>
<p>This attribute provides a simple source-level mechanism for executing code from RAM. The attribute instructs the tools to place the function in flash memory and copy it to RAM at boot time. All calls to the function will call the copy in RAM.</p>
<p>Because the attribute is applied to the function, the compiler can optimize the code for execution from RAM. At the time of writing, the only example of this is on C28x. On C28x, there is a fast branch instruction which is optimal only when executing from RAM. With the attribute, the compiler will automatically select the correct branch instruction. In the future, we plan to expand the optimizations done for code executing from RAM.</p>
<p>This is a brand new feature and we are still rolling out the device file updates to make it a seamless experience. If you receive this error message:</p>
<p>error: ".TI.ramfunc" section generated by __attribute__((ramfunc)) or</p>
<p> --ramfunc=on requires a SECTIONS specification to function.</p>
<p>Please add the following line in the SECTIONS directive of your linker command file:</p>
<table border="0" style="border-color:#bdbdbd;border-width:0px;width:213px;height:22px;background-color:#bdbdbd;">
<tbody>
<tr>
<td>.TI.ramfunc : {} load=FLASH, <br /> run=RAM, table(BINIT)</td>
</tr>
</tbody>
</table>
<p>The TI compiler tools provide more complex functionality for executing code from RAM. One example would be to have functions in RAM placed at the same address and copied into RAM before being called. </p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=668133&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Cody Addisonhttps://e2e.ti.com:443/members/1006075The power of a GUI simplifies the design of digital power factor correctionhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/the-power-of-a-gui-simplifies-the-design-of-digital-power-factor-correction2015-10-13T10:00:00Z2015-10-13T10:00:00Z<div><b>Other Parts Discussed in Post: </b><a href="https://www.ti.com/tool/POWERSUITE" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">POWERSUITE</a>, <a href="https://www.ti.com/tool/SFRA" class="internal-link folder tool" title="Link to Tool Folder" target="_blank">SFRA</a></div><p><b>The power of a GUI simplifies the design of digital power factor correction</b></p>
<p>When looking at power conversion systems that can take advantage of digital control techniques, it is obvious and expected to look for power factor correction (PFC) systems. The control loops are typically running at quicker speeds to accommodate the faster switching frequency of the PFC power stage. </p>
<p>Texas Instruments has designed a digitally controlled <a href="http://www.ti.com/tool/TMDSILPFCKIT">2-Phase Interleaved Power Factor Correction (ILPFC) converter</a> that can now be used to develop PFC control software from a GUI based tool. This kit is based on a single <a href="http://www.ti.com/product/TMS320F28035">C2000™ TMS320F28035 microcontroller</a> (MCU) and controls a 700W interleaved PFC power stage. This kit is a reference design that can be modified to meet custom PFC system requirements. That is where the powerSUITE tools come in.</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/5305.PFC-design.jpg"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/5305.PFC-design.jpg" alt=" " /></a></p>
<p>The <a href="http://www.ti.com/tool/powersuite">powerSUITE digital power software tools</a> allow you to modify a few PFC design parameters from the GUI and generate the PFC control code in order to match your PFC system requirements. If your design requires the use of different input or output voltages, different power stage component values, different digital compensators or a single-phase PFC topology, you can change these parameters on the Solution Adapter GUI.</p>
<p>The values from the Solution Adapter GUI are used by the PFC power stage model in the Compensation Designer to plot the theoretical loop gain (voltage and current loops) Bode plot for your custom PFC power stage board. You can then modify the compensator values from this GUI to achieve the desired loop (voltage and current loops) bandwidth, gain margin, and phase margin.</p>
<p>These theoretical values generated by the Compensation Designer can then be validated against the results from the Software Frequency Response Analyzer (SFRA). The data plotted by the SFRA is measured and calculated using the available processing capability in the C2000 MCU. This means that the frequency response is measured entirely in software on the MCU and then digitally transferred to the PC for viewing. However, this data could also be stored and analyzed by the MCU for on-chip system analysis. Once the actual frequency response has been measured and transmitted back to the PC running TI’s Code Composer Studio™ integrated development environment, the measured values of the plant are used by the Compensation Designer to provide a more accurate, measurement-based Bode plot that can be used to more finely-tune the digital compensator to achieve the desired bandwidth, gain margin, and phase margin.</p>
<p>Why not try out this simplified design process yourself? Download the free <a href="http://www.ti.com/tool/TMDSILPFCKIT"> powerSUITE digital power design tools</a> and start adapting the software for your own PFC design!</p>
<p>Login to your myTI account to leave a comment below with ways you can use the powerSUITE tools in your next design.</p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=667852&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Peggy Liskahttps://e2e.ti.com:443/members/1141124Introducing the new SeeedStudio BeagleBone Green open hardware computerhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/introducing-the-new-seeedstudio-beaglebone-green-open-hardware-computer2015-09-24T16:19:48Z2015-09-24T16:19:48Z<p>BeagleBoard.org has collaborated with Seeed Studio to produce a new variant of BeagleBoard.org BeagleBone Black, designed for makers and developers. This new open hardware board is called the SeeedStudio BeagleBone Green. You must be thinking, so what’s different about this one and is it really colored green?</p>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/BBgreen.png"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/BBgreen.png" alt=" " /></a></p>
<p><br /> The SeeedStudio BeagleBone Green, like the BeagleBoard.org BeagleBone Black, runs on a Texas Instruments <a href="http://www.ti.com/AM335x">Sitara AM335x processor</a>. The fundamental differences are:<br /> • Two Grove connectors that make it easy to connect to Grove modules to sense orientation, location, distance, water, touch, sound, temperature, humidity, barometric pressure, heart rate, finger print and much more<br /> • Replaced 5V barrel and miniUSB with a single microUSB connection, most common to power and connect to many common hobbyist and developer boards</p>
<p>• Removal of the microHDMI video output to save cost<br /> <br /> The decision to create this board happened around a discussion by me and Eric Pan of Seeed Studio at the Open Hardware Summit 2014 in Rome<span style="font-size:75%;">[1]</span>, where I spoke about "The Power of the Right Message"<span style="font-size:75%;">[2]</span> and Eric spoke about "Design from Manufacture"<span style="font-size:75%;">[3]</span>. We discovered that the combination of BeagleBoard.org's open nature and Seeed Studio's ability to quickly take open designs to manufacturing could make for an excellent example of the value of both of our organizations. By connecting up easily to Seeed Studio's large number of Grove modules, users are able to experience first success in their physical programming quickly and be confident they can take their experiments to any level they desire without barriers.</p>
<p>SeeedStudio BeagleBone Green is available now for $39 from Seeed Bazaar on-line and Micro Center stores around the United States. For more information, visit <a href="http://beagleboard.org/green">http://beagleboard.org/green</a>. </p>
<p>Let us know in the comments what projects you would use BeagleBone Green for!</p>
<p></p>
<p><span style="font-size:75%;">[1] <a href="http://2014.oshwa.org/2014/11/04/all-open-hardware-summit-2014-videos-are-available/">http://2014.oshwa.org/2014/11/04/all-open-hardware-summit-2014-videos-are-available/</a></span></p>
<p><span style="font-size:75%;">[2] <a href="https://vimeo.com/album/3114662/video/110646596">https://vimeo.com/album/3114662/video/110646596</a></span></p>
<p><span style="font-size:75%;">[3] <a href="https://vimeo.com/album/3114662/video/110336592">https://vimeo.com/album/3114662/video/110336592</a></span></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=667792&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">Jason Kridnerhttps://e2e.ti.com:443/members/3190New low-cost tool for Sitara AM437x processors is now available!https://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/new-low-cost-tool-for-sitara-am437x-processors-is-now-available2015-09-14T15:31:00Z2015-09-14T15:31:00Z<div><b>Other Parts Discussed in Post: </b><a href="https://www.ti.com/product/AM4378" class="internal-link folder product" title="Link to Product Folder" target="_blank">AM4378</a></div><p>The new Sitara AM437x Starter Kit is now available for order entry. We have plenty of inventory so place your order and it will ship immediately.</p>
<p>The AM437x Starter Kit features a 1GHz AM4378 processor; dual Gb Ethernet port; 4.3" capacitive touch screen LCD; on board camera module; 64 MB QSPI-NOR flash; and more.</p>
<p>The AM437x Starter Kit is <strong>only $249</strong> so it's the fastest, most economical way of getting started with the AM437x processors.</p>
<p>Go to <a href="http://www.ti.com/tool/TMDXSK437X">http://www.ti.com/tool/TMDXSK437X</a> to check it out!</p>
<p><a class="advance-link" name="&lid=en_us_folder_ts_product_image_large_image" rel="history"></a><img alt=" " src="http://www.ti.com/diagrams/med_tmdxsk437x_tmdxsk437x_board_image.jpg" width="350" height="225" /></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=667772&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">CBhttps://e2e.ti.com:443/members/1237Debug Applications with Code Composer Studio Cloudhttps://e2e.ti.com/blogs_/archives/b/toolsinsider/posts/debug-applications-with-code-composer-studio-cloud2015-07-17T15:44:00Z2015-07-17T15:44:00Z<p>Cloud-based development tools tend to be limited in the types of debug capabilities they offer. Typically you only have the ability to program your development board and view console output. The latest version of TI's Code Composer Studio cloud-based IDE takes this to another level. </p>
<p>The debugging features of Code Composer Studio Cloud now include:</p>
<ul>
<li>Stepping control</li>
<li>Breakpoints</li>
<li>Variables view</li>
<li>Callstack</li>
</ul>
<p><a href="/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/DebugDisplay.png"><img src="/resized-image/__size/1230x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-05-35/DebugDisplay.png" width="968" height="345" alt=" " /></a></p>
<p>The new debugging capabilities of Code Composer Studio Cloud make the environment even more attractive for evaluation and initial development of an embedded design.</p>
<p>To access Code Composer Studio Cloud and the rest of TI's cloud-based development tools, please visit <a href="http://dev.ti.com">dev.ti.com</a>.</p>
<p></p><div style="clear:both;"></div><img src="https://e2e.ti.com/aggbug?PostID=667576&AppID=535&AppType=Weblog&ContentType=0" width="1" height="1">JohnShttps://e2e.ti.com:443/members/10381