Reducing amplifier power consumption for SAR ADC drivers

As power consumption in SAR ADCs gets smaller with every new device generation, the limitation in power sensitive applications becomes the amplifier.  So how do we reduce power consumption further?  Before looking at possible solutions, let’s consider the reason behind the reduction in power consumption of the ADCs.

The plot below, figure 1, is taken directly from our 12-bit, 4-MSPS ADS7881 SAR ADC and is a good example of the dramatic reduction in power consumption.

Figure 1: ADS7881 power dissipation vs. sample rate

When operating at high clock rate, the only option to save power is to reduce the supply voltage. But, since this is not always possible, and you are using a SAR ADC in monitoring applications, consider using a slow duty cycle when there are few events to increase the sampling speed when the system is fully awake.  This is achieved simply by adjusting the clock rate.

This is all fine and good for ADCs, but does not answer the question on how to achieve significant power reduction in operational amplifiers.  So how do we do that?

The ADS7881 is a 12-bit ADC, with an input range comprised between 0-V and +2.5-V.

The amplifier I selected is the OPA836 as it can be operated on the same supply as the ADS7881.  So with a +5-V, we can minimize the ADC power consumption as well as its driver while maintaining input dynamic range. 

The OPA836 is a 1mA operational amplifier with excellent slew capability and linearity and is available in 2x2mm QFN package, ideal for battery operated operation.  Although it is an RRO (rail-to-rail output) device, its output will not swing to ground unless a small negative supply can be generated.  The limitation will also be present on the positive output, but will not be of interest here.  Note that the OPA836 datasheet makes a distinction between min and max linear output voltage and saturated output voltage. 

The headroom for linear operation is 150/250mV and 15/43mV for saturated for low and high rail.  Also, since the OPA836 input is not RRI (rail-to-rail input) and only includes ground, the -0.2-V to 3.9-V range may be a limitation.  A possible approach to avoid such limitation is to use the OPA836 in a gain greater than 1-V/V.  Since the ADS7881 has a maximum input voltage range limited by the reference voltage of +2.5-V, the only limit we will have is the negative rail on the output, so unity gain operation is perfectly valid.  Because the OPA835 is a high speed amplifier, we will have greater than 56MHz bandwidth and greater than 100-V/ms slew rate ensuring that the bandwidth stays constant with any signal level.

The least significant bit (LSB) for the ADS7881 is ~610mV.  With its 500uV max input offset voltage, the OPA836 is sufficient for a 12bit application.

As you control the clock rate of the ADC, it is possible to generate a signal in the microcontroller to enable/disable the OPA836 with the right timing.  The PD pin of the OPA836 can easily be synchronized with the BUSY pin, the CONVST pin or the NAP pin of the ADS7881 to place the OPA836 in disable mode.  The main issue to resolve now is the turn on time of the amplifier and the slow time constant imposed by the filter interface between the operational amplifier and the ADC.

The OPA836 has the capability of shutting down, but as we can see in figure 2 below, the turn on/off time is fairly fast and could easily accommodate high duty cycle.

Figure 2: OPA836 enable/disable response

The most problematic issue left is the time constant of the filter following the amplifier.

The approach for this is to control the output voltage present at the output of the amplifier while the amplifier is in shutdown mode, such as in figure 3.

Figure 3: maintaining the common-mode voltage output of the amplifier while in disable mode

Figure 4: OPA836 enable/disable response with mid voltage maintained on output

You may have noticed that between figure 2 and 4, the only difference is that the common-mode is different and that the amplifier still has the same turn on/off time constant.  As the ADC is moved from sample to hold mode, the amplifier’s only role is to maintain the appropriate common-mode voltage to help settle the ADC for the next conversion.  This has been replaced by a resistor divider that provide power saving when the operational amplifier is in disabled mode.

For related information, check out our Engineer It videos on "How to select an op amp to drive your SAR ADC" or "How to get datasheet value from your SAR ADC."  

  • Looks like there's a typo here: The least significant bit (LSB) for the ADC121C021 is ~660mV.  With its 500uV max input offset voltage, the OPA836 is sufficient for a 12bit application.  

    For 12 bit operation, I calculate 610 microvolts.  (Geez, how do I bold something in comments??)

  • Thanks for catching this Stephen.  I changed the post to reflect the fix.