DAC Essentials: What’s with all this glitch-ing?


When designing with a digital-to-analog converter (DAC), you expect the output to move from one value to the next monotonically, but real circuits don’t always behave that way. It’s not uncommon to see overshooting or undershooting, quantified as glitch impulse, across certain code ranges. These impulses can appear in one of two forms, shown below in Figure 1.

 

Figure 1: DAC glitch behaviors

Figure 1a shows a glitch that produces two regions of code transition error, which is common in R-2R precision DACs. Figure 1b shows a single-lobe glitch-impulse, which is more common in string DAC topology. Glitch impulse is quantified as a measure of energy which is commonly specified as nano-Volts-sec (nV-s).

But before we can talk about sources of DAC glitch, we must first define the term “major-carry transition.”  A major-carry transition is a single-code transition that causes a most significant bit (MSB) to change because of the lower bits (LSBs) transitioning. Binary code transitions of 0111 to 1000 or 1000 to 0111 are examples of a major-carry transition. Think of it as an inversion of the majority of the switches. This is where glitch-ing is most common.

Two areas of concern are switching synchronization and the switch charge transfer, as multiple switches are simultaneously triggered. For the sake of argument, let’s look at an R2R string DAC that’s designed to rely on switches that are synchronized during code transitions, shown below in Figure 2.

 

Figure 2: DAC major carry transition

 As we all know, there’s no such thing as perfect synchronization, and any variance in the switching will lead to a brief period where all switches are either switched high or low, causing the DAC’s output to error. Recovery occurs and, as a result, a switch charge will create a lobe in the opposite direction, before settling out.

So let’s take a look at the three stages that take place during a major-carry transition and how the DAC output responds, in Figure 3.

 

Figure 3: DAC output during transition

  1. The initial stage of the DAC, prior to the code transition. In this example we’re looking at the 3 MSBs representing binary code 011.
  2. The DAC output enters a major-carry transition that causes, for a short period, all of the R-2R switches to be connected to ground.
  3. The DAC recovers following a small period of switch charge injection, and the output begins to settle out.

Comparing the output glitch from a major-carry transition versus a non-major-carry transition, illustrated in Figure 4, proves that switching synchronization is the major contributing factor.

X-axis scale is 200ns/div and the Y-axis scale is 50mV/div.

 

Figure 4: R-2R DAC output glitch

So far, we’ve looked at glitch in an R-2R DAC architecture to explain that switch synchronization is the major contributor. But when you look at the glitch-ing of a string DAC, it is a little different. By design, it taps into different points on a resistor string to produce the output voltage. Without multiple switching, the pulse amplitude is smaller, and often dominated, by digital feedthrough. A comparison of the same major-carry code transition of an R-2R DAC and string DAC topology is shown in Figure 5.

 

Figure 5: R-2R vs string DAC output glitch

Understanding why glitch-ing occurs can help you decide if your design can live with this short impulse. I’ll talk about some methods to help reduce glitch in the coming weeks.

And if you want to learn more about string and R2R DACs, be sure to check out these previous posts in our DAC Essentials series here on Analog Wire:

Thanks for reading; I promise my next post will be shorter. :-)

  • any known way to solve such glitches without perfect synchronization?

  • Hello Keyur,

    Tony will be addressing some techniques to address glitching in an upcoming post. To answer your question more immediately, though, there are two commonly used techniques to reduce glitch energy; a simple R/C filter and a Sample and Hold topology with an operational amplifier. The R/C filter technique is pretty straight forward but comes at the cost of increasing the time it takes for the analog output to settle. The sample and hold method is a bit more complex and does require a good deal of synchronization but can be leveraged to eliminate almost all of the glitch energy without increasing settling time.

    Check back for Tony's next post where these items will be discussed further.

  • Does the glitch vary drastically with temperature or have random components?  In an R-2R DAC, for instance, can the glitch be decomposed into transitions of the segments?  If I can measure the integrated energy of the glitch, I could account for it for better overall precision of my filtered analog output; a table of energy from every code to every code could get unweildy but a more limited number of values could be reasily compensated.

  • Hi John,

    Thank you for your questions. They are very good questions.

    The glitch should have minimal change over temperature. Depending on the design of the switches, the the logic switching speed characteristics over temperature may have minimal differences but the finite bandwidth response time of the R2R ladder will dominate. Testing has shown that glitch has shown minor variation over temperature.

    The glitch energy, itself, is going to vary depending on which major carry transition you are crossing over. The DAC datasheet will spec the worse case in the electrical characteristics table which is taken across 0x7FFF to 0x8000 in a 16 bit unipolar DAC. You can integrate the glitch energy and it should match up with the datasheet spec in nV.s

    Let me know if that answers your questions.

    Thanks,

    Tony Calabria

  • great explanation!

    three questions:

    1.What kind of switch did you use to measure the glitches?

    2.In R2R example, why all switches connected to ground first and then MSB change?

    3.does 1000 to 0111 create the same glitch as 0111 to 1000?

    Thank you!