Welcome to the second installment of the Get Connected blog series here on Analog Wire! In this post, we explore the benefits of differential signaling and how these benefits can impact your high-speed designs.
Single-ended signals such as TTL, CMOS, and their reduced voltage brethren LVTTL and LVCMOS are techniques commonly used in digital circuit design. However, there are drawbacks to using these types of signaling techniques, which will ultimately inhibit your high-speed design. Single-ended signaling runs “out of steam” when communicating over long distances due to different ground potentials and high slew rates. A single-ended driver switching between positive and negative rails for every signal requires a high ΔV/Δt, which means you need loads of current (I = CΔV/Δt). So it is easy to see the limitations of rail-to-rail signaling (big ΔV) as more power is needed to achieve smaller transition times (smaller Δt). So how do we get our high speed signals around a digital design while avoiding the impairments of single-ended signals? Differentially!
Figure 1: Single-ended signal topology (left) / Differential-signal topology (right)
A differential system is typically a three conductor system (but may be more) that consists of a non-inverting signal, inverting signal, and ground reference. Ideally in a differential system, V+ = -V- and |I+| = |I-| yielding a balanced signal. In a balanced differential topology, the two conductors are tightly coupled together and the net ground current (IGND) is equal to zero. There are benefits to implementing the differential signaling topology in a system and they include but are not limited to higher signaling rates, high common-mode noise immunity, and lower power consumption.
With a differential signal, the rise and fall times can be substantially smaller than that of a single-ended signal, so data rates that exceed 10 Gbps have become an achievable standard in today’s communications systems. With the smaller signal swing comes a lower power requirement on your system's overall power budget. LVPECL and CML differential signals have a higher output voltage swing, so therefore they consume slightly more power than LVDS and M-LVDS signals.
The next benefit we see with differential signaling comes in the form of common-mode noise immunity. Since a differential signal consists of a positive and negative signal that are equal and opposite in magnitude, any common-mode noise that happens to couple onto the transmitted signal will be negated by its compliment. This proves to be a huge system advantage because more than likely there are going to be a few switching regulators connected to the power and ground planes, which are just waiting to couple their energy onto your clean signal. Though this may not seem like a big deal at first, you’ll quickly discover that when your design lives or dies on a tight jitter budget, every picosecond matters!
The table below summarizes the most popular differential signaling topologies, which vary in power consumption, performance, and application space:
An excellent differential signaling application example is interfacing a single-ended VCO output with an FPGA or SerDes that requires a differential LVDS clock input. To avoid ripping up your proven reliable system clocking architecture to satisfy this requirement, you can implement a device like the SN65LVDS1 single LVDS transmitter to perform the translation from single-ended to differential in between the VCO and end device. The SN65LVDS1 runs from a 2.4V or higher voltage supply, so it’s ideal for those applications that are power sensitive and do not have a 3.3V rail.
For more information on application specific solutions, please visit the High Speed Interface Forum in TI’s E2E™ Community and check out existing posts from engineers already using TI buffers, or create a new thread to address your specific application. Please join me for my next post in the Get Connected series where I will be discussing the fundamentals of jitter. If you are not connected you can get connected with one of the most comprehensive buffer portfolio's in the industry.
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