There are high levels of radiation in space, primarily electrons, protons and heavier ions. When an energetic particle travels through matter (like silicon), it suffers numerous interactions that extract some of its kinetic energy. The energy lost as the particle travels through any material leads directly to the creation of excess charge (non-equilibrium electron-hole pairs) and physical damage (vacancies, interstitials and localized melting). If the particle travels through active silicon, and the amount of generated charge is high enough and close to sensitive device regions, proper operation of the IC can be disrupted or destroyed. But not all radiation events are created equal.
One of the most commonly used terms in single event effect (SEE) testing and reporting is ion “stopping power” or linear energy transfer (LET), expressed in Mega-electron volts – centimeter2 per milligram (MeV-cm2/mg). LET is a measure of the amount of energy, dE, lost by a particle in a specific material as it travels an incremental distance, dx, through that material.
LET is not constant but varies as a function of the particle’s energy. LET is strongly dependent on the particle type (proton, electron, light ion, heavy ion, etc.), its energy and the material through which the particle is traveling.
Here are a few rules of thumb for LET:
Figure 1 simulates LET (red) and range (blue) for an iron ion in silicon as a function of its energy. As the ion loses kinetic energy, it moves more slowly, has more time to generate more charge and creates more defects. Thus, going from high-ion energy to lower energy, the ion LET peaks at low energy. Once the kinetic energy drops to zero, the ion is considered stopped and is no longer an issue from a device reliability point of view. This LET peak is known as the Bragg peak.
Figure 1: Simulation of the LET (red) and range (blue) of an iron ion in silicon as a function of the ion’s energy
This nonlinear property of LET as a function of the particle energy implies that unless a shield has a thickness sufficient to completely stop a particle, it will reduce the particle energy, which will actually increase its LET. This effect was seen in TI dynamic random-access memories (DRAMs) using a 5µm polyimide film serving as an overcoat, mechanical stress relief and “alpha-shield.” Experiments revealed that the industry-accepted practice of using shields did not block alpha particles but actually stopped them closer to active device layers with a higher LET, thus making alpha particle soft errors worse than in DRAMs without shielding.
LET is independent of the actual trajectory of the ion (ignoring channeling effects). However, since active layers in most semiconductor devices are constrained to a thin layer at the surface, ions with trajectories closer to these layers (high angles of incidence) will create much more charge in proximity to the active areas. To account for this effect, Equation 1 expresses the concept of effective LET (LETeff):
LETeff = LET/COS Θ (1)
where Θ is the angle of incidence (0° for normal incidence).
Figure 2 shows two identical ion strikes, one at normal incidence (left) and one at a glancing angle of 60° (right). Since most of the energy is lost at the end of the ion’s path, the glancing ion event deposits much more excess charge near the junction; hence, its ability to disrupt the device function is significantly enhanced. Figure 3 shows a stopping and range of ions in matter (SRIM) simulation of LETeff as a function of ion angle. Generally, when LET is mentioned in the context of its effect on electronic devices, you can assume that the angle term is included; thus, LET mentioned in literature is actually LETeff.
Figure 2: Diagram of two identical ion events, hitting a junction at normal incidence (left) and at a glancing incidence (right). Much more charge will be generated/collected by the glancing case
Figure 3: LETeff as a function of angle – effective LET increases with increasing angle as the ion’s trajectory moves closer to the surface. Note that LET and LETeff are the same at normal incidence
Understanding LET and LETeff is crucial to be able to read a single-event effects report and papers on the topic. Since the space environment is defined as a function of effective particle LET, understanding this metric goes a long way to allow you to communicate to space customers and ensure that you understand what is needed for new space product designs. If you enjoyed this post, be sure to sign in and subscribe to Analog Wire to get similar posts delivered right to your inbox.
This blog article appeared on the D RV8332HDDV device page, which is under "Space & High Reliability" components. I would like to use this device for a CuubeSat design, in-lieu of a number of large, power hungry, and expensive qualified red-hard parts. Does the semiconductor technology / design of the '8332 have the ability to survive 20kRad TID and low earth orbit SEE events for short missions?
The DRV8332HDDV is a high-temperature part (-HT suffix) and, as such, is not designed for space use. That does not necessarily mean that it cannot be used in a space application BUT the reliability failure risks are high. The HT part has NOT been characterized for total ionizing dose (TID) or single-event effects (SEE) as many space (-SP) and some enhanced performance (-EP) products have. For this particular product we unfortunately do not currently have an -EP or -SP equivalent.
This product is based on a power biCMOS process, and the gate oxides are relatively thick so it is likely there would be parametric shifts in a TID environment. With the power supply of 12V and up to 50V, heavy-ion-induced latch-up could occur (single-event latch-up or SEL).
A short mission duration is good since it limits the accumulated dose (TID and proton dose) BUT an SEL could occur at any time during the mission and given the operating voltages and currents would likely be destructive.
Hope this helps.
Thank you for the guidance.
In general, regarding SEL, how does a power biCMOS process perform relative to other TI processes? And, is it correct that the greater the power supply voltage (50V vs 12V), the higher the probability of SEL?
Technologies such as pure bipolar or true SOI where the wells are isolated either by junctions or oxide, SEL is generally not possible and thus these types of technology could be considered SEL-immune. Any CMOS/biCMOS technology has the potential for SEL (and electrical LU) - the pre-requiste being n and p wells and n+ and p+ contacts in close proximity such that with charge injection there is the possibility of creating and sustaining NPN/PNP pairs that for the high-current latch.
Higher voltages increase the risk of SEL in very low voltage since you need at least two diode drops to tunr on the parasitic bipolars. Anytime the operating voltage exceeds the snap back voltage of the SCR created by parasitic bipolar formation, a sustained high current steady-state LU is possible.
In many high voltage devices where the voltage is dropped across a relatively low doped "drift" region, avalanche multiplication of the initial charge deposited by the ion can be amplified and increase the likelihood of an SEL.
Hope this helps, Rob
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