Signal Conditioning functions go mainstream in PCI Express Gen 4


It’s been quite a while – just about seven years now – since the current PCI Express (PCIe) Gen 3 specification became official. With a swell of activity in the standard committees, a new PCIe Gen 4 specification reached version 1.0 in late 2017. As everyone already knows, PCIe Gen 4 doubles the available data rate to 16Gbps and keeps backward compatibility firmly in place. By using the same 128/130 encoding scheme and equalization training, architects hope to minimize any conversion issues as the industry jumps to the updated standard.

Doubling the data rate does impose some distance limitations on the native channel length, especially with standard FR4-printed circuit board material. Improving the connector and enhancing PCIe receiver capabilities has translated into a larger attenuation budget for the PCIe channel. Even with the larger budget, the maximum channel length tends to be shorter for a PCIe Gen 4-compliant link. To counteract the increased attenuation, a much higher percentage of PCIe Gen 4 systems will use improved board materials and “link extension” devices. The term “link extension” can describe two types of signal conditioning devices. See Table 1.

Table 1: Comparing the two types of signal-conditioning devices

A linear equalizer is an analog-only device designed to boost the incoming signal with continuous time linear equalization (CTLE). This type of gain and link extension is best used for simple channels without multiple board and cable connections. These “simple” channels are dominated by attenuation, which is too much for system components to handle alone. Key performance metrics for a linear equalizer are a large dynamic voltage range, low additive random jitter and easily controlled AC gain.

To demonstrate the performance of linear equalization, a family of PCIe presets (Figure 1) was captured directly from a 16Gbps generator (TP1). A channel containing a linear equalizer then used the same signals as inputs. Measurements after the channel and linear equalizer at TP2 show it is possible to completely compensate for high speed channel losses with linear equalization. Accurate reproduction of the analog waveform content ensures that in-channel equalization will not compromise any digital algorithms used for link equalization training.

Figure 1: PCIe Tx Preset family, before and after a channel that includes a linear equalizer

A PCIe retimer is a combination of analog and digital circuits with specific features and requirements to directly interoperate with other PCIe Gen 4 devices. The addition of digital control and protocol awareness enables the retimer to completely reset the system’s jitter budget and handle the full channel attenuation specified in PCIe. This doubles the effective reach of a PCIe system link, enabling a wide variety of system architecture and topology choices (Figure 2).

Figure 2: Multi-clock domain PCIe link

The PCIe standard continues to be the primary input/output (IO) interconnect within the server and PC environment. As engineers work to extend PCIe beyond the server to take advantage of its simplicity, scalability and bandwidth, they must also deal with PCIe clock distribution throughout the expanded system. To help alleviate distribution problems, many designs are moving to PCIe implementations that encompass multiple local clock domains. Retimers supporting Separate Reference Clock with Independent Spread (SRIS) form a good clock domain boundary as PCIe signals travel across cables or between server chassis in a rack.

As a recognized system component, the PCIe retimer will engage in equalization training on the upstream and downstream channels. This built-in capability automatically optimizes the signal-conditioning solution for short, medium or long PCIe-compliant channels.

The choice of a linear repeater or protocol-aware retimer will depend on many factors. Systems that just need a little help to lower the effective channel attenuation between system components can consider the repeater a lower-power alternative to a full retimer implementation. Systems with complex topologies and high levels of attenuation are candidates for a retimer solution; learn more here.

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