Low voltage differential signaling (LVDS, also known as OpenLDI) thin-film transistor (TFT) liquid crystal (LCD) displays typically have a specified resolution and minimum required clock frequency to meet desired resolution. Normally, you will find this information listed in the display data sheet and won’t need to perform any calculations.
However, if you do not yet have access to your display data sheet and only know what resolution you want your system to support, you can estimate what clock frequency you need and determine which serializer/deserializer (SerDes) is appropriate for your application.
Pixel clock frequency
Equation 1 calculates pixel clock frequency as:
Let’s define each parameter of this equation.
Figure 1: Video format parameters
The values for these blanking parameters are listed in display data sheets. The total blanking period varies from 3% to 39%. If your system uses reduced blanking, then you can estimate %Blanking at 10%. If you are not sure what blanking period your system uses, estimate around 20% and above to be conservative.
Throughput is another metric that you can use to determine whether or not a device will support your desired display resolution. The throughput is the effective payload of video data, and is derived from the required pixel clock frequency and color depth of your system, as shown in Equation 2:
The remaining parameter to cover:
The color depth will determine how many LVDS data lanes your display requires. SerDes serialize data at a rate of 7x the pixel clock frequency on each LVDS data lane. If the color depth is 24-bit RGB, then you will need four LVDS data lanes (there are an additional four bits used for control, which brings the total bit count to 28 bits) and can use a SerDes like the SN65LVDS93A. If the color depth is 18-bit RGB, then you will need three LVDS data lanes (there are an additional 3 bits used for control, which brings the total bit count to 21 bits) and can use a SerDes like the SN74LVDS84A or the SN65LVDS93A.
If the color depth is 48-bit RGB, then you will need eight LVDS data lanes (there are an additional 8 bits used for control, which brings the total bit count to 56 bits) and will need to use a device like the DS90C387 or DS90C189-Q1, which can output as many as eight LVDS data lanes.
When calculating the throughput for DIDO applications, you need to calculate the throughput for the odd pixels and even pixels separately and then add them together. For example, for a 48-bit DIDO application, the total required throughput would be 2 x Pixel Clock x 24.
Now that you have the necessary equations for pixel clock frequency and throughput, let’s go through a couple of examples.
Example 1 - SISO application
The first example is for a SISO application. Table 1 lists the parameters needed to calculate the pixel clock frequency and throughput.
Frame rate (Hz)
Blanking period (%)
Table 1: Design parameters for SISO application
Using Equation 1:
So the minimum pixel clock frequency to support a 1280 x 800 resolution display is 83.56MHz.
Using Equation 2:
So the total minimum required throughput is around 2005Mbps.
Since the color depth is 24-bit RGB, you will need four LVDS data lanes. The SN65LVDS93A is a good fit for this application, since it has a pixel clock frequency range of 10MHz to 135MHz. Additionally, the maximum throughput for each LVDS data lane on this device is 135 x 7 = 945Mbps. Because this device has four LVDS data lanes, the total maximum throughput is 945 x 4 = 3780Mbps, which is higher than the minimum required throughput.
Example 2 - DIDO application
This example is for a DIDO application. Table 2 lists the parameters needed to calculate the pixel clock frequency and throughput.
Table 2: Design parameters for DIDO application
So the minimum pixel clock frequency to support a 2048 x 1536 resolution display is 208MHz. However, since this is a 48-bit DIDO application, there are actually two clocks: the frequency is split between them. Each clock must have a frequency of at least 104MHz.
Using Equation 2, the minimum required throughput for each channel (one channel = four data lanes) is: Throughput = 108 x 24 = 2496Mbps.
So the total minimum required throughput is 2 x 2496 = 4992Mbps.
Since the color depth is 48-bit RGB, you will need eight LVDS data lanes. The DS90C387 and DS90C187 are a good fit for this application, since they have a pixel clock frequency range of 32.5MHz to 112MHz (the DS90C387) and 25MHz to 105MHz (the DS90C187) for each channel in DIDO applications. Thus, if you don’t have access to the display data sheet yet, you can still estimate the required pixel clock frequency and throughput to support your desired resolution. If the SerDes does not meet these parameters, data on the display may display incorrectly, or not display at all.
Leave a comment below if you would like to learn more about anything discussed here, or if there is an LVDS topic you would like to see in the future.
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