Analog Wire

  • Did you know you can design a PCB coil for inductive sensing in five minutes with WEBENCH®? If you are considering using an inductance-to-digital converter , like the LDC1000 , but are concerned about the time it takes to design a sensor coil,...
  • Welcome back to our Timing is Everything clock series! Today I will be covering how to select the clock or timing IC that best fits your application . It’s a fair question to ask: “Is there more to choosing a clock than to just pick one...
  • Pick any CMOS or JFET amplifier and you’ll get the lowest possible input bias (Ib) current, right? Not so fast. If you mean low Ib compared to that of bipolar, then yes. But if you mean sub 10pA, there are other factors to consider. Did you say...
  • Welcome back to Timing is Everything! Last time we covered Understanding PLL loop filter response . Today, I will be helping you learn how to better understand the variety of jitter specifications. As timing requirements in high-speed applications become...
  • In my previous post, Understanding the protocol , I took a high-level functional look at the three states within the JESD204B protocol that are critical to establish a valid data link between the TX and RX portion of the link: code group synchronization...
  • Welcome back to the Get Connected blog series here on Analog Wire ! In the previous Get Connected blog post, SerDes XAUI to SFI design , we took an in-depth look at using the TLK10232 in a XAUI to SFI protocol converter design. In this post, we are going...
  • Have you noticed how differential signaling is becoming more and more dominant in high performance signal paths? Differential signaling offers several advantages! I’ve been thinking about the fact that every differential signal path has a parasitic...
  • Did you know that at least one voltage reference is used in almost every application? This is because a reference point is typically required somewhere inside the signal chain of a system. Voltage references are most commonly used as a reference for data...
  • As many of you know, jitter (which is clock edge uncertainty) is a bad thing that leads to increased noise and degradation of a data converter’s ENOB. For example, if we have a system that requires an ENOB of 14 (minimum) bits at 100 MHz,...
  • I’ve learned a lot about the JESD204B interface standard while designing systems with our latest analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which use this protocol to communicate with FPGAs. I’ve also read...