Analog Wire

  • Configuration of inductance-to-digital converter (LDC) sensors can seem quite challenging, but by using the graph introduced in this blog post, the process can be greatly simplified. For LDCs, a sensor is a simple inductor, spring, or PCB coil in parallel...
  • Baluns are often used to convert a single-ended signal to differential, without adding noise and while maintaining good distortion. A common example of that is in the driver circuit for a high-speed, differential-input analog-to-digital converter (ADC...
  • To pick the right isolator for a system, a design engineer must understand what component-level isolation parameters define an isolator’s high-voltage performance, how these parameters are tested and certified, and why these parameters are relevant...
  • In the world of isolation technology, designing a reinforced digital isolation integrated circuit (IC) that meets the performance specifications and standards of the harsh industrial environment is challenging. Testing and delivering such an isolator...
  • If you are a power supply designer, then isolation is often a concern when dealing with high-voltage switching converters. It is very common to use some form of isolation between the high-voltage primary voltage and secondary low voltages. The feed-back...
  • If you have ever felt the “click” of a button on your computer mouse or the “bump” of the home key on a smartphone, you know the feeling of tactile feedback, also known as haptic feedback. But why do some user interfaces not “click”...
  • In my previous blog post , I outlined the fact that differential signaling can still be negatively impacted by common mode noise. In this post, I will outline some methods that you can use to reduce the impact of common mode noise on differential signal...
  • In my last post , I explained the importance of JESD204B subclasses and reviewed the details of subclass 0 and 1. Today, I’ll explore subclass 2. Subclass 2 Subclass 2 analog-to-digital converters (ADCs) and digital-to-analog converters (DACs...
  • Most of the JESD204B standard addresses the data interface between logic devices and converters, so what are the clocking requirements? For JESD204B subclass 1, the clocking requirement is quite simple: use the SYSREF rising edge to mark the device clock...
  • In this blog, I’ll look at a key feature of the JESD204B standard that defines a method to achieve deterministic latency for each link and subsequently multi-device synchronization. Some applications, such as synchronous sampling, multi-channel...