In June 2017, I posted about unprecedented current-loop performance from an off-the-shelf microcontroller (MCU) achieved by the C2000™ family with the fast current loop (FCL) software solution. Closing the current loop in less than 1ms had previously been the domain of custom application-specific integrated circuit (ASIC) and field-programmable gate arrays (FPGAs) with parallel data-path architectures.
The DesignDRIVE C2000 FCL release at that time was targeted for the industrial drive development kit (IDDK) and, while you could measure the loop time with a scope, analyzing the control bandwidth of the current loop meant using an expensive dynamometer and control response analyzer tools in your own laboratory environment.
In early 2018, TI released its second version of the FCL solution, with these updates:
The most important update to share is the fact that our own in-depth measurements exceeded our previous expectations of “over 3kHz” of control bandwidth versus traditional approaches. Figure 1 summarizes the results of FCL tests versus traditional current-loop designs. In each case, we designed control loops for a target bandwidth and measured the phase margin. By plotting these results against each other, you can see the dramatic difference in bandwidth at a given phase margin between the two control approaches.
Every one of these tests uses only a 10kHz pulse-width modulation (PWM) carrier frequency and in-line current sensing enabled by INA240 sensors on the low-voltage three-phase gallium nitride (GaN) inverter BoosterPack. Using in-line sensing enables the current to be sampled twice per PWM period during the polarity transition points. The results shown in both curves of Figure 1 leverage the double sampling technique. (For reference, an incremental or ABZ encoder provides the shaft angle feedback.)
Most in the industry measure their current-loop bandwidth at 45 degrees of phase margin in order to avoid instability situations. If you compare the results in Figure 1 at 45 degrees (the dashed red line), you will see that the FCL controller delivers about 5kHz of control bandwidth, while the traditional approach is less than 2kHz.
Figure 1: Gain margin vs. phase margin results comparing FCL to traditional current-loop control
For more details on how we obtained this plot, see the technical brief, “Performance Analysis of Fast Current Loop (FCL) in Servo Drives Using SFRA on C2000™ Platform.” Or better yet, see the Additional Resources section at the end of this post and validate these measurements for yourself.
SFRA tools, now with motor-control support
So how will you measure the frequency and phase margin of FCL or the specific controllers that you design in the future? One option is to leverage the free C2000 SFRA tool. Part of the powerSUITE tool chain, the SFRA tool enables the measurement of the open loop gain and plant frequency response of a closed-loop digital controller using only software. Taking advantage of software libraries linked into the C2000 project and executed in silicon as well as the digital debugging connection, you take the measurements and plot them in the SFRA PC application. This makes the in-system measurement of digital control loop bandwidth, gain margin and phase margin quick and easy.
Now available for motor current control analysis as well, these tools are included for free in the FCL download. Figure 2 shows an example of the frequency response plots of an FCL project as presented by the SFRA tool.
Figure 2: SFRA PC graphical user interface
But I need a motor and a controlled load to measure the response
That’s true, and a dynamometer machine and the hardware tools you need to control it can be really expensive. But not in this case! You can replicate our performance analysis with a bundled package that includes a C2000 Delfino™ controller, two GaN three-phase inverters and dual motor dynamometer in a single orderable product on the TI store. See Figure 3.
Figure 3: A low-cost GaN-based bundle for motor-control performance testing
Available for less than $600, this is the same configuration that produced the test results shown in Figure 2. The inverter BoosterPack development boards included in this bundle also include the in-phase current sensing, and therefore enable double sampling of the current per PWM period.
If you are interested in a quick way to see FCL results on your own bench and establish your own performance motor-control development and testing environment, this bundle can get you moving fast. It also serves as a great tool for testing your motor-control ideas beyond FCL – for speed and position loop control, for example.
We have also tested FCL with TI’s DRV8305N three-phase motor drive BoosterPack evaluation module with integrated sense amplifiers. In this case, the current is sampled on the inverter shunts; therefore, a single sample is taken per PWM period. These tools have also been packaged with the two-motor dynamometer and are shown in Figure 4.
Figure 4: A low-cost, shunt-based sensing bundle for motor-control performance testing
Another development with the FCL release is that the software project incorporates the control of two motors concurrently from a single C28x core. We decided to use a second FCL instance in order to incorporate the load-side control. The coordination of analog-to-digital converter (ADC) sampling, field-oriented control (FOC) processing and PWM updates are resolved in this release. We used the second controller to act as the load, but in your dual-axis servo drive architecture, you can use these axes independently for whatever your industrial application may require. When you investigate this for yourself, you will see that both loops are capable of delivering the same bandwidth results as in Figure 1.
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