Part 4: Dos and don’ts of layout design
Howdy and welcome back!
In my previous posts, we pieced together a system, found our components, conquered the mighty schematic, and reviewed, reviewed, and reviewed some more. Many people will call their portion of the design complete, hand off the schematic to a layout engineer and have a coffee while waiting for their PCB. But, don’t let up just yet! Layout is where we physically instantiate the schematic and it is home to a variety of common mistakes. In this post, I will walk you through many of these common layout mistakes and the fixes for them. Know that many of these tips are engineering rules of thumb, for more details on PCB layout design you can see numerous resources available on the web.
Here are some app notes from Texas Instruments on proper PCB layout practices and design…
The three common mistakes we will look at today are…
*Image Notes: Red = Top Copper Layer, Blue = Bottom Copper Layer, Device = DRV8711
1. Improper connection to the PowerPAD (thermal pad)
Today, many devices have a PowerPAD (exposed copper pad on the bottom side of the IC) in order to improve thermal dissipation from the internal silicon. This is especially important in motor drivers, amplifiers, power converters, etc. that often have integrated power MOSFETs. These power MOSFETs generate heat (directly related to RDS(ON) and current through the FET) that must be transferred away from the silicon in order to maintain a high level of performance and avoid damage. Oftentimes, this pad is incorrectly left unsoldered or connected to isolated copper on the PCB. We’ll use the DRV8711, stepper motor pre-driver, as our example below of what to do and what not to do.
No PowerPAD landing area placed onto the PCB. Solder resist will isolate PowerPAD from copper on the PCB (no heat sinking capability).
PowerPAD connected to isolated copper plane (minimal heat sinking capability). Two traces cutoff the top copper plane and there are no via connections to the bottom copper plane.
PowerPAD connected to open copper planes on both the top and bottom layers with recommended via land pattern (see datasheet).
2. Improper trace sizes for high current lines
Sizing your copper traces appropriately to handle current load is a key component of PCB layout design. Many factors play into this calculation including your desired temperature rise, heat sinking capabilities and the time the trace will handle a load. A general rule of thumb to utilize is 10 mils (trace width)/Amp (with 2 oz. copper). This is a bare minimum rule. For critical routes and designs, you will want to spend more time determining the ideal trace width for your PCB.
5A power supply traces sized for 10 mils (too narrow).
5A power supply traces sized appropriately (just right).
3. Lengthy and High Impedance Current Loops
The last topic we will touch on today are lengthy and high impedance currents loops. These can show up in a design in a variety of places. The first common mistake we see for undesirable current loops is with the decoupling capacitor for internal voltage regulators. The decoupling capacitor should be placed near the device pin of the regulator output with a short return path to the device GND pin.
On the DRV8711 we see two decoupling capacitors on the V5 and VINT (C5 and C6) voltage regulators.
Have a lengthy current loop for decoupling capacitors. The GND net of the capacitors makes a lengthy path around the PCB before going through the PowerPAD and entering the GND pin of the DRV8711.
Utilize a compact, low impedance current loop for decoupling capacitors. The GND net of the capacitors proceeds directly to the GND pin of the DRV8711.
For stepper motor drivers there is often a sense resistor on the low side of each H-bridge. In a motor driver with integrated power MOSFETs (or even drivers with external power MOSTFETs) it is often forgotten that this sense resistor is the main return path for the high current from the motor back to the power supply.
Below we see the current return path (through R1 and R2, sense resistors) for two external H-bridges (Q1-Q4) driven by the DRV8711.
Have a lengthy current loop for high current paths. Below, the high current path travels through the DRV8711, around a variety of headers to the MCU (possibly interfering with ADCs, SPI lines, and GPIO), then finally returns to the power supply.
Utilize a compact, low impedance current loop for the high current paths. Here the sense resistors immediately via to the bottom layer where a low impedance trace delivers the current directly back to the power supply.
Question: In the last image, there is a fairly common mistake in violation of one of these three rules I just laid out. Can you find it? This one is not quite as obvious as the examples I have given here and is something more similar to what we see every day.
Hint: It is related to the sense resistors and this board has been designed to achieve a peak current of 8A.
Answer: The two sense resistor utilize thermal relief, a default setting in Altium. Thermal relief defaults to a width of 10 mils and even with 4 spokes, this is still not adequate to carry the peak current spec’d for in this design.
Thanks for reading and feel free to leave comments! Next time, we will cover a few more key mistakes made in layout design including improper grounding techniques, poor component placement, and poor signal routing.
You can also check out earlier installments of the series at…
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Great article! Very informative..thank you
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