Achieve unprecedented current-loop performance from an off-the-shelf MCU

TI’s expertise in real-time control architectures and experience with industrial drive control systems over the last 20 years has led to many cycle scavenging enhancements to its C2000™ family of real-time microcontrollers (MCUs) and corresponding software solutions.

The latest advancement, Fast Current Loop(FCL), is featured in the DesignDRIVE developers kit and takes advantage of C2000 MCU’s real-time cycle-scavenging architecture, high-performance processing resources and fast data throughput to significantly increase the bandwidth of the current control loop, achieving subcycle updates of the pulse-width modulator (PWM) in less than 1 microsecond and without the assistance of external processing components like a field-programmable gate array (FPGA) or analog-to-digital controller (ADC).

In fact, the field-oriented-control (FOC) processing period, the central processing unit (CPU) time used after sampling and converting the current, is only 460ns on a 200MHz clock. How is this possible with an off-the-shelf MCU? It’s because C2000 MCUs are not typical MCUs. Their design from the beginning was to minimize the time (in CPU cycles) that it takes to process samples and update the actuation, which subsequent C2000 MCU generations have only improved upon. The many cycle-scavenging data-path features built into the latest C2000 MCUs include an integrated high-performance successive-approximation-register (SAR) ADC, ADC post-processing hardware, single-cycle reads from the ADC, single-cycle writes to the PWM, a trigonometric math accelerator, a code law accelerator and ePWM immediate update mode. You can even use FCL to control two axes at the same time. It’s no problem.  Just move to dual-core configurations like the TMS320F28379D and use FCL on each C28x core.

Why should you care about Fast Current Loop? Because the improvements it makes to your current loop enable significant improvements to your speed and position loop control bandwidth. And improvements in these specifications on your servo drive are what your customers are really looking at. More efficient control of their factory automation equipment means more productivity, resulting in more throughput and ultimately greater profitability.

From a hardware design perspective, with FCL you can achieve greater bandwidth without increasing your carrier frequency or adding additional processing components. A higher carrier frequency means higher switching losses and additional heat dissipation, necessitating more extensive and expensive thermal-management strategies. More components mean more bill-of-material (BOM) cost, more board space, more current, etc.

Beyond the super-fast FOC processing and the resulting bandwidth improvements, FCL also includes a new, efficient control algorithm option that compensates for the inherent transport delay of the motor drive system. The DesignDRIVE Complex Controller (CC) results in perfect pole-zero cancellation at all times, ensuring stability at higher speeds than those achieved by traditional digital control algorithms.

A C2000 drive control system-on-chip like the TMS320F28379 with FCL delivers similar performance compared to FPGA-based systems while simplifying servo drive development and reducing system costs, power complexities and board space. And compared to traditional MCU-based systems, the FCL can potentially triple the drive system’s torque response and double its maximum speed without increasing the carrier frequency.

Additional resources

  • Finding datasheet review TMS320F28379D  Delfino architecture page 4 does not remit info of embedded FOC ROM. That seems to be the norm for  most C2000 datasheets omitting information of #InstaSpin FOC embedded ROM in the architecture illustration and product description.

    Had to go to a cross reference PDF table for TMS320Family of processors to find datasheet details of the embedded FOC ROM.

    Can you explain if 500ns FCL is possible with (<=5400RPM) 90 degrees non-salient synchronous stators, assume text refers a typical axial flux BLDC? Does double the rotor maximum speed claim also apply to existing controllers using (EMF/FOC) for axial flux BLDC and with less than 1us FCL?

    Please elaborate what is meant by 3Khz bandwidth in 10Khz carrier without ADC loop ?  How can we do FOC phase current monitor without ADC in the loop. Clicking on the pictures does not enlarge them to a point of visual and clear explanation!

  • Have to assume (Internal) ADC is still required for FCL. Figure 4 & 7 FCL block shows external current shunt/monitor inputs (Ia,Ib,Ic)  but no indication where on MCU pins FCL block connects or if we can relocate FCL monitors to any of the Delfino 12/16 analog channel pins. No reference to or if InstaSpin or any FOC is embedded with FCL being the C2000 Design Drive training videos don't discuss FOC closed speed loop support.

    What of custom PCB designs need to leverage the power of TI-RTOS with FOC and FCL in the Delfino Dual core?

    www.ti.com/.../sprac55.pdf

  • Sensored open loop FOC seems to use QEP index pulse to report rotor speed, Sprac55 is not very clear on how FOC requires QEP to determine rotor position. Have to wonder why no option exists for embedding InstaSpin FAST estimator rom in the 1k OTP space. Being a dual core it would seem TI-RTOS can handle 2 separate core tasks for full sensorless FOC and QEP hardware is not required.

  • @BP101: FCL is not based on InstaSPIN.  FCL is available as a flash-based library and probably will never be placed into a C2000 on chip ROM.  It does require position feedback that is received from a QEP in our example.

    The improvements in the maximum speed come from the greater stability of the current loop in high speed conditions.  This is enabled by the enhanced stability  of the new Complex Controller (CC) as compared to traditional PI controllers at high speeds.

    An ADC is absolutely required for current sensing and we use the on-chip, high performance ADC on the '37x family.  FPGA-based current loops require an additional, external ADC (please see the whitepaper) to be used/controlled by the FPGA.  

    We plan to have FCL-specific introduction videos posted in the near future.

    FCL doesn't rely on TI-RTOS today but there is no reason why the FCL techniques couldn't be applied to a TI-RTOS-based system.  You would want to be sure to minimize any RTOS timing overhead associated with the critical FOC calculation path.  

    The premise of FCL is to minimize the time/cycles needed from the point of current sampling to the PWM update time.  Direct in-line current sensing with our integrated ADC and position feedback via QEP offer the minimal time impact to this critical loop as compared to the additional critical calculations required to run sensorless or the latency due to receiving absolute encoder data.  We hope to give a performance/latency comparison of QEP vs. absolute encoder timing in the future.

  • Hi Brian,

    I was a little confused about FCL since the block diagram looks a lot like InstaSpin FAST embedded ROM. After reading more about FCL it appears to use extend EMF for determining rotor position not QEP index. Rotor position is derived from FCL logic filers Ld/Lq much like the FAST block, so it seems QEP index is required only for the PI speed controller loop. A Canadian graduate 2016 did his thesis on Ld/Lq extended EMF rotor position principal. Do have the PDF white paper if your interested.

    The older software we now use leverages EMF edge counts to determine rotor position & speed. Curious how we could use FCL library without QEP index sensor, instead use EMF Ld/Lq to also determine rotor speed? Unless I have missed something in how FCL leverages QEP index pulse seemingly only for PI speed reporting not rotor position.

  • Hi Brian,

    could you share a block diagram of the Complex Control (CC) vs standard

    and how you split the actions between the DSP, CLA, TMU etc...

    Thanks

    Nicola_