Improve the performance of your power tool design with power blocks

Appliances like power tools, garden tools and vacuum cleaners use low-voltage (two- to 10-cell) lithium-ion battery-powered motor drives. These tools use brushed DC (BDC) or three-phase brushless DC (BLDC) motors. BLDC motors are more efficient and have less maintenance, less noise and longer life spans.

The most important performance requirements of the power stage driving the motors are small form factor, high efficiency, good thermal performance, reliable protection and peak-current capability. A small form factor enables flexible mounting of the power stage inside the tool, better board layout performance and low-cost designs. High efficiency provides maximum battery life and reduces cooling efforts. Reliable operation and protection facilitate long lifetimes, which help with product reputations.

To drive a BDC motor in both the directions, you need to provide two half bridges (four metal-oxide semiconductor field-effect transistors (MOSFETs)) forming a full bridge. To drive a three phase BLDC motor, you need three half bridges (six MOSFETs) forming a three phase inverter.

With TI’s CSD88584Q5DC and CSD88599Q5DC power blocks, available in a small-outline no-lead (SON), 5mm-by-6mm package using a stacked die architecture, you can drive a BDC motor in both directions with just two power blocks and three-phase BLDC motor with just three power blocks , as shown in Figure 1. Each power block has two MOSFETs connected as a high side and low side MOSFET forming a half bridge.


Figure 1: Power block MOSFETs in different motor-drive topologies

Let’s look at the benefits that these power blocks could bring to a cordless tool motor-drive subsystem design.

Double the power density

The dual stacked die technology in the CSD885x power block enables twice as much silicon per printed circuit board (PCB) area, effectively decreasing the PCB footprint by 50% compared to discrete MOSFETs.

Compared to a discrete MOSFET of same performance level, which is available in 5mm –by-6mm, the power block integrating two FETs in the same package achieves PCB area savings of 90mm2 (3 x 5mm-by-6mm) for a three phase inverter topology. There will be MOSFET interconnecting tracks running in the PCB with discrete MOSFETs and a higher operating current ask for wider PCB tracks also, and hence the saving in PCB size is actually much more than 90mm2. Most cordless power tool applications use at least four-layer PCBs, with copper thickness more than 2oz. Therefore, saving in PCB size with power block leads to considerable savings in PCB cost.

Clean MOSFET switching with low parasitics

Figure 2 shows parasitic inductance and capacitances contributed by component leads and non-optimized layout in a power stage PCB design. These PCB parasitics cause voltage ringing and thus voltage stress on the MOSFETs.

 

Figure 2: Parasitic inductance and capacitance in a power stage half bridge.

One of the causes of ringing is diode reverse recovery. A high rate-of-change of current caused by fast switching can result in a high diode reverse-recovery current. The reverse-recovery current flows through the parasitic layout inductance. The resonant network formed by the FET capacitance and the parasitic inductance cause phase-node ringing, reducing the voltage margin and increasing stress on the device. Figure 3 shows phase-node voltage ringing with discrete MOSFETs as a result of circuit parasitics.

With power blocks, having the switch-node clip that connects the two MOSFETs keeps parasitic inductances between the high and low MOSFETs to an absolute minimum. The use of a low- and high-side FET in the same package minimizes PCB parasitics and reduces phase-node voltage ringing.

Using these power blocks helps to ensure smooth MOSFET switching without voltage overshoots even at currents as high as 50A, as shown in Figure 4.

     

Figure 3: Phase-node voltage ringing and voltage overshoot with discrete MOSFETs

Figure 4: Clean phase-node switching waveform with power blocks

Low PCB losses with reduced PCB parasitic resistance

The power blocks help to reduce the length of high current carrying tracks in the PCB and hence reduces the power loss in the tracks.

Let us understand the PCB track requirement in the case of discrete FETs. The PCB track connection between the top- and bottom-side discrete MOSFETs causes I2R losses in the PCB. Figure 5 shows the copper track when connecting the top and bottom discrete MOSFETs side by side; this is one of the common layouts for easy motor winding connection to PCB.  The copper area connecting the phase node has a length twice as the width (the track width depends on the current and the track width is normally limited by the board’s form factor). Alternatively, you could arrange the top- and bottom-side discrete MOSFETs up and down, keeping the phase node in between. But because of the need of provision to connect motor winding to the phase node, you may not be able to reduce the track length and also such an arrangement may not be suitable for all the applications.

If the design has a PCB copper thickness of 2oz (70µm), a single-layer PCB track connecting the phase node as given in figure 5, will have approximately 0.24mΩ resistance. Assuming that the track exists in two PCB planes, the equivalent PCB resistance is 0.12mΩ. For a three phase power stage, you have three such PCB tracks. You can perform a similar analysis for the DC supply incoming and return tracks also.

The power block, having the top side and bottom side MOSFET in single package and the phase node connected by a metallic clip inside the package, optimizes the parasitic resistances and gives you the flexibility for layout and saves a minimal 0.5 to 1mΩ total PCB resistance.

Figure 5: Typical phase-node track length with discrete MOSFETs

Superior thermal performance with dual cooling

The CSD885x power blocks come with DualCool™ packaging, which enables heatsinking at the top of the package in order to pull heat away from the board, offering superior thermal performance and increase the amount of power that can be dissipated in a 5mm-by-6mm package. As per datasheet specification, the power block has a junction-to-bottom case thermal resistance of 1.1°C/W and a junction-to-top case thermal resistance of 2.1°C/W. You can optimize the cooling either to the PCB from the bottom case or to the heat sink from the top case of the power block. Figure 6 shows the results with a top-side common heat sink (27mm-by-27mm-by-23mm) tested with three CSD88599Q5DC dual-cooled 60V power blocks in a 1kW,36V three phase inverter PCB (36mm-by-50mm), without any airflow. An electrically insulated thermal interface having low thermal impedance (Rθ < 0.5°C/W) is used between the heat sink and the power block top case during testing.

Figure 6: Thermal image of the board showing effective top-side cooling

In Figure 6, you can see the effectiveness of top-side cooling where the difference between the maximum temperature observed on the PCB (below the power block bottom case) and the heat sink temperature is less than 11°C. The heat is well conducted and distributed to the top-side heat sink through the top cooling metal pad of the power block.

Heat sharing between the top and bottom FETs

In a single- or three-phase inverter, the losses in the top- and bottom-side MOSFETs may differ. These losses normally depend on the type of pulse-width modulation topology and operating duty cycle. Different losses cause different heating of the top and bottom MOSFETs. When using discrete MOSFETs in a system design, you could try these different methods to equalize the temperature between the top and bottom FETs:

  • Use a different cooling area for the MOSFETs and provide more PCB copper area or heat sink for the MOSFET that has more losses.
  • Use different devices for the top- and bottom-side MOSFETs depending on their nominal current. For example, you can use a device with less ON state conduction resistance (RDS_ON) for the MOSFET that carries more current.

These methods will not give optimal cooling when the MOSFET heat up depends on the operating duty cycle, resulting in underutilization of the PCB area or MOSFET rating. Using power block MOSFETs, where the top and bottom MOSFETs are in the same package, results in automatic heat sharing between the top- and bottom-side MOSFETs and provides both better thermal performance and optimized system performance.

Low system cost

It is possible to optimize system cost by using power block MOSFETs in your design. The cost reduction will occur as a result of all of the benefits I’ve discussed in this post:

  • Half the solution size, reducing PCB cost drastically.
  • Low parasitics enable a much more reliable solution, one with longer life and low maintenance.
  • Reducing the PCB track length reduces the PCB resistance, resulting in lower losses and higher efficiency with a smaller heat sink.
  • Superior thermal performance resulting in less cooling efforts.

A MOSFET power block helps to achieve a more reliable, smaller-sized, efficient and cost-competitive system solution.

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