The buck regulator efficiency/size tradeoff dilemma


As an applications engineer, I know that buck regulator implementations are inevitably tied to a tradeoff of efficiency versus size. While this axiom is true for many switch-mode DC/DC topologies, you can put a long series of exclamation marks after the sentence (!!!) when the application demands low output voltage and high output current, e.g. 1V and 30A. Then, a small form-factor power solution, balancing efficiency and size, is vital.

High efficiency is a key performance benchmark, leading to reduced power loss and component temperature rise, and more useable power at a given airflow and ambient temperature. From this standpoint, a low switching frequency is very enticing, but cost and size increase as large filter components are needed to meet target specifications such as output ripple and transient response.

PCB area dedicated to power management is an immense constraint for the system designer. With that in mind, let’s review the benefits of high switching frequency. First, inductance and capacitance requirements decrease at higher frequency, leading to tighter PCB layout and smaller footprint and profile. A lower inductance allows a faster large-signal change in current, and coupled with higher control loop bandwidth, enables faster load transient response. A rule of thumb for maximum loop bandwidth is 20% of switching frequency. Last, some interesting options open up at higher frequencies in terms of component selection.

For example, take a look at this regulator design that exploits careful component selection to push efficiency/size/cost boundaries.  Watch a video demonstration here.

Schematic of 600-kHz step-down regulator rated at 30A

(1)  Inductor - Even though iron powder or composite core inductors give commendable performance at low frequency, higher core losses negate their value proposition above 500kHz or so. At that point, ultra-low DCR ferrite magnetics tend to offer lower copper and core losses. Note that core losses are easy to gauge, at least on a relative basis, by looking at a converter’s no-load input current. Off-the-shelf options for ferrite inductors with single-turn “staple” winding are widely available, and sub 1-mΩ DCR is easily achieved if only one winding turn is required!

(2)  PWM Controller - Now, if a design is captive to the hard saturation characteristic of a ferrite-cored inductor, it’s imperative to never exceed the inductor’s saturation current. This points to a PWM controller that leverages parasitic circuit resistance(s) for accurate yet lossless current sensing (read my previous blog, “Nailing Accurate and Lossless Current Sensing in High-Current Converters" for more on this topic). Other salient features include efficient gate drivers, remote BJT temperature sensing, and fast error amplifier.

(3)  MOSFETs - Power semiconductors are the cornerstone to gaining advances in efficiency and size. Consider, for example, the Power Block NexFET™ family, oft-praised for innovatively co-packaging high- and low-side MOSFETs by vertical stacking. When frequency-proportional losses warrant a close eye, low QG, QRR, QOSS charges are vital. Low RDS(ON), high current copper clips, kelvin gate connections, and grounded tab are essential, too.

(4)  Capacitors - At higher frequencies ceramic capacitors are favored over electrolytics. Now, output bulk energy storage becomes redundant as the control loop promptly reacts to transient demands. Ceramics offer not only lower ESR but also lower ESL, which mitigates output ripple from inductive divide effect and low filter inductance.

What other factors affect regulator efficiency and size? Popular themes of late include GaN MOSFETs, and power-system-in-package (PSIP) and -on-chip (PSOC).  Let me know what you think?

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  • Mind explaining 'kelvin gate connection'?  I thought kelvin connection was for current sense resistors.  

  • Somewhat analgous to kelvined sensing, a kelvined gate connection is a way of decoupling the gate drive (gate-source) loop from the main current (drain-source) loop of the power MOSFET. This helps to reduce parasitics in the gate drive circuit and maintain fast swithcing speed. In particular, common source inductance (CSI) should be minimized - for more details on this, see lit # SLPA009A or www.ti.com/.../slpa009a.pdf.