Understanding undervoltage lockout

I'm told that the optimum environment for the human body is somewhere between 21°C and 30°C degrees, so inside TI’s air-conditioned office – set year-round to a toasty 23°C – conditions are perfect to deliver optimum performance (at least, that’s what my boss tells me).

In wintertime in central Europe, however, temperatures can fall to –20°C or lower. Even with many layers of clothing, the human body does not operate well under these conditions: it can survive, but it does not achieve optimum performance.

The human body is not the only thing affected by its operating conditions. Integrated circuits also operate best within certain temperature and supply-voltage ranges. In this post, I’ll discuss the latter, and the related undervoltage lockout (UVLO) function.  You can find more details in the application report, “Understanding Undervoltage Lockout in Display Power Devices.”

How low can you go?

As most electronic engineers already know, many integrated circuits contain an UVLO function that disables the device when its supply voltage is too low for correct operation. Without a UVLO function, at low supply voltages the device may do something, but you cannot be sure what. A UVLO function makes sure that the device either operates according to its specification or does nothing at all.

Among other things, a low supply voltage can cause:

  • Bias circuits to operate incorrectly.
  • Bandgaps to generate the wrong reference voltage.
  • Logic functions to fail.
  • Power transistors to turn on or off only partially.

Many devices have a UVLO threshold below a couple of volts. To be honest, it’s impressive that devices do anything at such low supply voltages. If you don’t believe me, try designing an analog circuit that operates from 2V and see how you get on.

The challenges are even greater in power devices. When the supply voltage is low, perhaps you can turn a power MOSFET on and off, but you can’t do it very quickly. And typically, the MOSFET’s on-resistance will increase, because the supply voltage is too low to generate a high-enough gate-source voltage.

Some devices specify a recommended supply-voltage range as well as a UVLO threshold. The device achieves full performance only if its supply voltage is in this range. But what happens between the UVLO threshold and the recommended minimum supply voltage? In TI’s display power group (the product line I work for), devices still function in this range, but we do not specify their performance. That means that buck converters still buck and boost converters still boost, but the output power available may be less than the maximum the device is capable of.

In mission-critical applications, UVLO thresholds are typically above the minimum recommended supply voltage – the device turns on only when it can achieve full performance. This approach leads to extremely robust system designs, but in general is not cost-effective for consumer products. It would be like driving a car that stopped working as soon as the fuel level got low (but not empty). It’s more useful to have the car still drivable – albeit with reduced performance – than to suddenly stop working altogether.

Figure 1 illustrates the operational state of a typical power device. You can see that:

  • In the red region where VI < VIT (min), the device does not operate and consumes minimal supply current.
  • In the green region where VI > VREC (min), the device operates with full performance.
  • In the gray region where VIT (min) < VI < VIT (max), the device is either off (red) or functional (yellow), but either state depends on the precise threshold of the UVLO function.
  • In the yellow region where VIT < VI < VREC (min), the device is fully functional but its performance is not specified in the data sheet.


Figure 1: Typical UVLO behavior

Note that the rising and falling UVLO thresholds are different. That is because a well-designed UVLO function has hysteresis. Why? Well, not only do comparator circuits in general benefit from hysteresis, power devices by their very nature tend to pull significant current from the upstream power supply. And since there’s always some resistance between the power supply and the device it’s powering, the voltage that the UVLO comparator sees is always a bit less than the voltage of the upstream power supply (see Figure 2). When the voltage reaches the UVLO threshold, the device turns off and the current flowing into it drops instantaneously to almost zero, causing the voltage that the UVLO comparator sees to immediately increase (because when the input current drops, the voltage drop across the input resistance suddenly disappears).


Figure 2: Equivalent circuit of a typical power device with UVLO function

If the hysteresis voltage is smaller than I×R, under certain conditions the power management IC (PMIC) can turn on and off a number of times before it finally turns off for good. At best, this looks ugly; at worst, it can cause system-level problems. Figures 3 and 4 are scope plots illustrating this phenomenon.


Figure 3: Low-input resistance results in regular power-down behavior


Figure 4: High-input resistance results in irregular power-down behavior

The next time you're designing an application circuit, take a moment to make sure that you understand how the UVLO function works. For example:

  • Make sure that you know the circuit’s rising and falling thresholds and its hysteresis; if not stated in the data sheet, feel free to ask for more details in the TI E2E™ Community non-isolated DC/DC forum.
  • See if there’s a region between the UVLO threshold and the recommended operating voltage range in which the device can operate but perhaps not deliver all of its specified performance. Make sure that your application can handle this region.
  • Remember that the input current multiplied by the input resistance should be less than the UVLO hysteresis for clean power-up and power-down behavior. 

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