LDO basics: Current limit

The key goal of DC power management is to provide a regulated, steady voltage for the slew of electronic content present in any system. This is particularly true for low-dropout regulators (LDOs), as they can achieve a regulated voltage while supplying current as needed.

There are external conditions and scenarios where an LDO might experience an unexpected high current draw. This high current will harm most electronic systems as well as the host power-management circuit if the current is transmitted to the other electronics being powered. Selecting an LDO with internal protection from short circuits and current limiting can help prevent this harmful effect and provide additional protection when designing the overall power management.

What is current limiting/how does it work?

Current limit in an LDO is defined by establishing an upper boundary for the current supplied. Unlike a constant current source, LDOs supply current on demand but can also control the total power regulated. Current limiting is achieved through internal circuitry controlling the output stage transistors inside the LDO. See Figure 1. This is a classic current-limit circuit for an LDO and is commonly referred to as a “brick-wall” current limit due to its abrupt current stop once the limit is reached. In this internal circuit, the LDO measures the output voltage for feedback but also measures a scaled mirror of the output current against the internal reference (IREF).

 

Figure 1: A current-limiting internal LDO structure

Brick-wall current limiting

In a brick-wall current limit, the upper boundary is defined and the LDO supplies current incrementally until the limit current limit is reached. Once the current limit is exceeded, the output voltage is not regulated and is determined by the resistance for the load circuitry (RLOAD) and the output current limit (ILIMIT) (Equation 1

                                             (1)

The pass transistor will continue this operation and dissipate power, as long as the thermal resistance (θJA) allows for healthy power dissipation where the junction temperature is within acceptable limits (TJ < 125°C). Once VOUT goes too low and the thermal limit is reached, thermal shutdown will turn off the device in order to protect it from permanent damage. Once the device has cooled, it will turn back on and regulation can proceed. This is particularly important in cases where a short circuit may present itself, as the LDO will proceed to regulate VOUT to 0V.

For example, TI’s TPS7A16 can limit high current outputs in wide voltage conditions. Figure 2 shows an example behavior of the current-limiting function in 30V input conditions. As you can see, once the current limit is surpassed, the LDO continues to supply at the limit, but it will no longer regulate VOUT to 3.3V. Once the thermal limit is surpassed at 105mA, thermal shutdown kicks in.

This current-limiting function is helpful for charging nickel-cadmium and nickel-metal hydride single-cell batteries, as both require a constant current supply. An LDO like the TPS7A16 can help maintain a constant current at the limit (ILIMIT) as the battery voltage changes while the battery is charging.

 

Figure 2: TPS7A16 brick-wall current limiting (30VIN, 3.3VVIN, VSON at 25°C)

Foldback current limit

Foldback current limit is very similar to the standard upper-boundary limit. But the main goal of foldback current is to limit the total power dissipation, keeping the output transistor within its safe power-dissipation limit by reducing the output current limit linearly while VOUT decreases and VIN remains steady.

Devices like the TLV717P feature foldback current limiting and benefit from it, due to being predominantly offered in very small packages with higher thermal impedance. If you look at the behavior of the TLV717P’s output current limit, as shown in Figure 3, you can see that the maximum power dissipation allowed at 25°C is 150mW, as VIN is specified as VOUT + 0.5V. After the current limit is exceeded and VOUT begins to reduce (assuming a constant RLOAD), both IOUT and the power dissipation reduce. This adds a bit of complexity for non-ohmic devices that draw a constant current and could trigger a lockout condition in which the powered device continues to reduce VOUT and the LDO continues to reduce IOUT.

 

Figure 3: TLV717P output current limit vs. VOUT

Whenever harmful conditions may be present such as short circuits or overloading, it is important to prevent the transmission of this effect to other sensitive electronics. Protected LDOs can provide a wide range of functionality that can make any design much more robust. Read more blog posts on the basics of LDO design.

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