When starting a new design, engineers are often overwhelmed by the number of package options for power metal-oxide semiconductor field-effect transistors (MOSFETs) and power blocks. For example, TI offers single N-channel MOSFETs in 12 unique packages. Given this myriad of options, how do you know which package to select for your application?
There are many considerations when choosing a component package, including through-hole vs. surface mount, size, cost, lead spacing and thermal capability. In this technical article, I’d like to focus on package thermal capability and provide some rules of thumb for power dissipation in TI MOSFET and power block packages. I hope that you’ll find these rules helpful, because power dissipation determines the smallest package possible in a given application.
Start by looking at the data sheet
All power MOSFET and power block data sheets include thermal impedance specifications in the thermal information table. Figure 1 shows an example of thermal impedance specifications for the CSD17581Q5A.
Figure 1: Device absolute maximum ratings for the CSD17581Q5A
As detailed in an earlier technical article, the thermal impedance in the data sheet is determined using standard test procedures and printed circuit board (PCB) layout. Figure 2 depicts the standard test boards used to measure the thermal impedance of a 5-mm-by-6-mm small outline no-lead (SON) package. TI has developed similar standardized test boards for other TI MOSFET packages.
Usually, real-world applications use a PCB with two or more layers, thermal vias and a pad area somewhere in between those shown in Figure 2. These efforts result in low thermal impedance, allowing the heat to spread into the internal PCB layers for a space-optimized solution using the smallest board area.
Figure 2: 5-mm-by-6-mm SON junction-to-ambient thermal resistance (RθJA) measurements as they appear in the CSD17581Q5A data sheet
The maximum power dissipation is specified in the absolute maximum ratings table (Table 1) of a power MOSFET/power block data sheet. Maximum power dissipation is a calculated value, as shown in this technical article, and in reality, it is not very useful because the standard PCB used for this type of testing does not correlate to actual, real-world applications. Start with the absolute maximum ratings but keep in mind that the thermal capability of a particular package may be better or worse in your application, with your PCB design and ambient conditions.
TA = 25°C (unless otherwise stated)
MIN TYP MAX
RθJC Junction-to-case thermal resistance(1)
RθJA Junction-to-ambient thermal resistance(1)(2)
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Table 1: CSD17581Q5A thermal impedance specifications
Consider design experience and empirical data
Fortunately, there are existing designs using MOSFET packages that can give you an idea of the thermal capabilities of each package in real-world conditions. Combined with empirical data collected during testing, you should have some guidance for the amount of power that can be dissipated in a particular power MOSFET package. Tables 1 through 5 summarize the estimated maximum power dissipation by product category and package type.
Keep in mind that the power dissipation numbers in the tables below are only estimates. Because the effective junction-to-ambient thermal impedance is very dependent upon the PCB design, your actual performance may vary; in other words, your particular design may be able to dissipate more or less power than what is presented here. Use these guidelines to help narrow down what packages to consider for your design.
How to read the tables
Let’s consider the 5-mm-by-6-mm plastic SON package. TI uses a few versions of this SON package for its power MOSFETs and power blocks. Most vendors have a similar package for their power devices, and a lot of data exists about how much power it can dissipate. TI has tested power blocks in this package on a PCB design with dimensions of 4 inches wide by 3.5 inches long by 0.062 inches high and six copper layers of 1-oz copper thickness. Based on the test results, a good rule of thumb is that the 5-mm-by-6mm SON package can dissipate about 3 watts in a typical application with a good layout.
Product category = single N-channel MOSFET
Package type (drawing)
Typical RθJA (°C/W)
Estimated PDISS (W)
PicoStar™ package (YJM)
0.73 by 0.64
PicoStar package (YJC, YJJ)
1.0 by 0.6
PicoStar package (YJK)
1.53 by 0.77
Wafer-level package (W, W10)
1.0 by 1.0
Wafer-level package (W1015)
1.0 by 1.5
2-mm-by-2-mm SON (Q2)
2.0 by 2.0
Wirebond 3-mm-by-3mm SON (Q3A)
3.3 by 3.3
Clip 3-mm-by-3mm SON (Q3)
Wirebond 5-mm-by-6-mm SON (Q5A)
5.0 by 6.0
Clip 5-mm-by-6-mm SON (Q5B)
Clip 5-mm-by-6-mm SON (Q5)
Table 2: Single N-channel MOSFET estimated power dissipation by package
Product category = dual N-channel MOSFET
PicoStar package (YME)
1.35 by 1.35
PicoStar package (YJE)
2.2 by 1.15
PicoStar package (YJG)
3.37 by 1.47
Wafer-level package (W1723)
1.7 by 2.3
3-mm-by-3-mm SON (Q3E)
Table 3: Dual N-channel MOSFET estimated power dissipation by package
Product category = single P-channel MOSFET
PicoStar package (YJM, YJN)
PicoStar package (YMG)
1.2 by 1.2
Wafer-level package (W10)
Wafer-level package (W, W1015)
Wafer-level package (W, W15)
1.5 by 1.5
Wirebond 3-mm-by-3-mm SON (Q3A)
Clip 3-mm-by-3-mm SON (Q3)
Table 4: Single P-channel MOSFET estimated power dissipation by package
Product category = dual P-channel MOSFET
Wafer-level package (W15)
Table 5: Dual P-channel MOSFET estimated power dissipation by package
Product category = N-channel power block
Typical RθJA (°C/W)
3.0 by 2.5
2.5 by 5.0
5.0 by 3.5
Clip 3-mm-by-3mm SON (Q3D)
Clip 5-mm-by-6-mm SON (Q5D)
DualCool™ 5-mm-by-6-mm SON (Q5DC) packaging
Table 6: N-channel power block estimated power dissipation by package
You can use the information presented in this technical article to guide your package selection for power MOSFETs and power blocks. Always check that the MOSFET power loss in your application does not exceed the package capability. These are not absolute limits and the performance in your application will depend on the operating and environmental conditions, as well as the PCB layout and stackup.
Of course, power dissipation is not the only consideration when selecting a power device for a design. You’ll also have to consider other parameters such as voltage and current ratings, on-resistance, package size, and lead spacing.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.