A successive approximation register (SAR) analog-to-digital converter (ADC) generally requires a driver for its analog input to achieve the desired precision results. But at lower throughputs and lower resolution, you may not need a driver. Let’s look at sampling process and analog input structure of a SAR ADC to understand the driver’s requirement.
The analog input of a SAR ADC is a combination of a sampling switch, a resistor and the sampling capacitor. Figure 1 shows the analog input structure for a SAR ADC.
The sampling switch is closed for a period tACQ (acquisition time) to acquire the input signal and it opens during the conversion process. During the sampling phase, the sampling capacitor is charged up to input voltage by transfer of charge between the analog input source and the sampling capacitor. For an ADC with a resolution of N bits, the voltage at sampling capacitor should settle to (VIN ± ½ LSB) range within the acquisition time.
It’s usually best to place an RC filter before the input of the SAR ADC. This is done to provide the charge to the sampling capacitor during the sampling phase and to reduce the voltage glitch seen by the analog source during the sampling phase. Figure 2 shows a simplified circuit for a SAR ADC analog input driven by an analog source.
The analog source sees a voltage glitch at the sampling instant.
The value of CFLT is generally chosen to be between 20 to 60 times the sampling capacitor.
The output impedance of the analog source plays a critical role in input voltage settling during the sampling phase. The time required by the input voltage to settle (tsettle) increases with the output impedance of the analog source.
To achieve a precision of N Bits, tsettle ≤ tacq:
The waveform below in figure 3 shows the settling time achieved with a different ROUT for a SAR ADC running at a throughput of 100KSPS.
Figure 3 shows that an analog source with an output impedance of 1500 ohms (Case I) cannot settle the input signal within the acquisition time of the ADC, but an analog source with an output impedance of 500 ohms (Case II) is able to meet the acquisition time requirement of the ADC. So, Case I requires a driver to settle the input signal within the acquisition time of the SAR ADC while Case II does not..
The acquisition time generally depends on the throughput of SAR ADC, reducing the throughput will lead to higher acquisition time. For Case I also, the driver might not be required at throughputs lesser than 100 kSPS.
Conclusion: At lower throughputs, a lower resolution SAR ADC can be driven without the amplifier. As the resolution of SAR ADC increases, the settling time increases and as the throughput increases, the acquisition time reduces, so SAR ADCs with higher resolution and higher throughput require a driver to reduce the settling time and achieve the desired precision.
To learn more about this use case, check out TIPD168, a complete reference design for ultra-small form factor and low power data acquisition systems. Read more SAR ADC-related blogs on the Precision Hub, such as Input considerations for SAR ADCs, written by my colleague Amit Kumbasi.
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