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Today, the smallest feature sizes on integrated circuits are approximately 20 nanometers. It’s now fairly clear that CMOS will be further scaled,at least by about another factor of ½. However, we are already well into the region of diminishing returns from this historical scaling trend. For example, microprocessor clock speeds essentially saturated almost 10 years ago. Note that this is largely due to the challenge of heat-removal, which, of course, also reflects the fact that high-speed scaled CMOS now uses relatively more power.
Texas Instruments has been a member of the Semiconductor Research Corporation (SRC), supporting university research for over 25 years. Just this year, the SRC Focus Center Research Program, now called “STARnet,” and the SRC Nanoelectronics Research Initiative (NRI), both working on “beyond CMOS,” have been successfully recompeted for the next five years. In addition, some of the STARnet centers will also address new circuit and system techniques for better exploiting CMOS.
I’m looking forward to the discovery of new devices by NRI and STARnet that might be further developed by the semiconductor industry into practical technologies for supplementing and/or replacing CMOS in many applications. Of course, CMOS is a tough act to follow. It’s even possible that there isn’t anything that could be developed over the next few decades into a practical technology that would be significantly superior to CMOS in speed, power efficiency, and cost per function. This is largely because the field-effect transistors (FETs) that serve as the “switches” in CMOS logic are so elegantly simple and effective for controlling the flow of electric current. However, as the great breadth of research in NRI and STARnet indicates, we are definitely not idea-limited!
For example, one of the research threads aims to improve on the turn-off characteristics of the switch. Below the gate threshold voltage, FET current drops by an order of magnitude for at least 60 millivolts of drop in voltage on the gate. This turn-off rate is limited by the mechanism of thermionic emission for the flow of electrons from the source to the channel of the device. Research is underway on devices in which quantum tunneling through the source-channel barrier replaces thermionic emission over the barrier. The main challenge for such “tunneling” devices is to conduct sufficient current when the device is “on” (i.e., gate voltage above the threshold). In part, this is being addressed through using new channel materials – for example, graphene as a replacement for silicon. Graphene also plays a role in research on other potential “beyond CMOS” devices, and you can read more about it in the blog by Luigi Colombo.
Another promising area of research on superior electronic switches involves materials that are called “multiferroics.” This means that they exhibit more than one of the properties of ferromagnetism, ferroelectricity, and ferroelasticity. Many of these materials are perovskite transition-metal oxides. Those combining ferromagnetism and ferroelectricity offer the promise of controlling the flow of spin/magnetization with electric charge rather than with current-generated magnetic fields, which is a much less efficient process. Thus, for example, we can envision devices in which the flow of information is via waves of electron-spin-polarization rather than simply electric current. Research is also underway on devices in which the orientation of nanomagnets represents a logic state. Such devices represent a type of nonvolatile logic that retains its state even when no power is supplied. In this case, the main challenge is in making circuits that operate at high speed. Of course, speed versus power efficiency is almost always a major trade-off, even in non-electronic technologies!
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