00001 /* *********************************************************** 00002 * THIS PROGRAM IS PROVIDED "AS IS". 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IN NO EVENT WILL TI'S 00021 * AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF 00022 * YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS 00023 * (U.S.$500). 00024 * 00025 * Unless otherwise stated, the Program written and copyrighted 00026 * by Texas Instruments is distributed as "freeware". You may, 00027 * only under TI's copyright in the Program, use and modify the 00028 * Program without any charge or restriction. You may 00029 * distribute to third parties, provided that you transfer a 00030 * copy of this license to the third party and the third party 00031 * agrees to these terms by its first use of the Program. You 00032 * must reproduce the copyright notice and any other legend of 00033 * ownership on each copy or partial copy, of the Program. 00034 * 00035 * You acknowledge and agree that the Program contains 00036 * copyrighted material, trade secrets and other TI proprietary 00037 * information and is protected by copyright laws, 00038 * international copyright treaties, and trade secret laws, as 00039 * well as other intellectual property laws. To protect TI's 00040 * rights in the Program, you agree not to decompile, reverse 00041 * engineer, disassemble or otherwise translate any object code 00042 * versions of the Program to a human-readable form. You agree 00043 * that in no event will you alter, remove or destroy any 00044 * copyright notice included in the Program. TI reserves all 00045 * rights not specifically granted under this license. Except 00046 * as specifically provided herein, nothing in this agreement 00047 * shall be construed as conferring by implication, estoppel, 00048 * or otherwise, upon you, any license or other right under any 00049 * TI patents, copyrights or trade secrets. 00050 * 00051 * You may not use the Program in non-TI devices. 00052 // 00053 //This software has been submitted to export control regulations 00054 //The ECCN is EAR99 00055 * ********************************************************* */ 00056 //***************************************************************************** 00068 //***************************************************************************** 00069 // Provides Functions to Initialize the UCS/FLL and clock sources 00070 // File: hal_ucs.c 00071 // 00072 // Texas Instruments 00073 // 00074 // Version 1.2 00075 // 11/24/09 00076 // 00077 // V1.0 Initial Version 00078 // V1.1 Added timeout function 00079 // V1.1 Added parameter for XTDrive 00080 //******************************************************************************* 00081 00082 #include "msp430.h" 00083 #include "hal_UCS.h" 00084 00085 00086 00087 //==================================================================== 00092 void LFXT_Start(uint16_t xtdrive) 00093 { 00094 UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1 startup 00095 00096 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00097 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags 00098 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00099 } 00100 UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode 00101 } 00102 00103 //==================================================================== 00108 uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout) 00109 { 00110 UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1 startup 00111 00112 while ((SFRIFG1 & OFIFG) && timeout--){ // check OFIFG fault flag 00113 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags 00114 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00115 } 00116 UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode 00117 if (timeout) 00118 return (UCS_STATUS_OK); 00119 else 00120 return (UCS_STATUS_ERROR); 00121 } 00122 00123 00124 //==================================================================== 00129 void XT1_Start(uint16_t xtdrive) 00130 { 00131 UCSCTL6 &= ~(XT1OFF | XT1DRIVE_3); // enable XT1 00132 UCSCTL6 |= (XTS | xtdrive); // enable XT1 and set XT1Drive 00133 00134 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00135 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00136 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00137 } 00138 } 00139 00140 //==================================================================== 00145 uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout) 00146 { 00147 UCSCTL6 &= ~(XT1OFF | XT1DRIVE_3); // enable XT1 00148 UCSCTL6 |= (XTS | xtdrive); // enable XT1 and set XT1Drive 00149 00150 while ((SFRIFG1 & OFIFG) && timeout--) { // check OFIFG fault flag 00151 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00152 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00153 } 00154 if (timeout) 00155 return (UCS_STATUS_OK); 00156 else 00157 return (UCS_STATUS_ERROR); 00158 } 00159 00160 //==================================================================== 00165 void XT1_Bypass(void) 00166 { 00167 UCSCTL6 |= XT1BYPASS; 00168 00169 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00170 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00171 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00172 } 00173 } 00174 00175 //==================================================================== 00180 void XT2_Start(uint16_t xtdrive) 00181 { 00182 UCSCTL6 &= ~(XT2OFF | XT2DRIVE_3); // enable XT2 00183 UCSCTL6 |= (xtdrive); // Set XT2Drive 00184 00185 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00186 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00187 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00188 } 00189 00190 } 00191 00192 //==================================================================== 00197 uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout) 00198 { 00199 UCSCTL6 &= ~XT2OFF; // Set XT2 On 00200 UCSCTL6 &= ~XT2DRIVE_3; // enable XT2 00201 UCSCTL6 |= (xtdrive); // Set XT2Drive 00202 00203 while ((SFRIFG1 & OFIFG) && timeout--){ // check OFIFG fault flag 00204 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00205 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00206 } 00207 if (timeout) 00208 return (UCS_STATUS_OK); 00209 else 00210 return (UCS_STATUS_ERROR); 00211 } 00212 00213 //==================================================================== 00218 void XT2_Bypass(void) 00219 { 00220 #ifdef XT2BYPASS // on devices without XT2 this function will be empty 00221 UCSCTL6 |= XT2BYPASS; 00222 00223 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00224 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00225 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00226 } 00227 #endif 00228 } 00229 00230 //==================================================================== 00237 void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio) 00238 { 00239 volatile uint16_t x = ratio * 32; 00240 // save actual state of FLL loop control 00241 uint16_t globalInterruptState = __get_SR_register() & SCG0; 00242 00243 __bic_SR_register(SCG0); // Enable FLL loop control 00244 00245 Init_FLL(fsystem, ratio); 00246 00247 while(x--) 00248 { 00249 __delay_cycles(30); 00250 } 00251 00252 __bis_SR_register(globalInterruptState); // restore previous state 00253 00254 } 00255 00256 //==================================================================== 00263 static void Init_FLL(uint16_t fsystem, uint16_t ratio) 00264 { 00265 uint16_t d, dco_div_bits; 00266 uint16_t mode = 0; 00267 00268 d = ratio; 00269 dco_div_bits = FLLD__2; // Have at least a divider of 2 00270 if (fsystem > 16000){ 00271 d >>= 1 ; 00272 mode = 1; 00273 } 00274 else 00275 fsystem <<= 1; // fsystem = fsystem * 2 00276 00277 while (d > 512) 00278 { 00279 dco_div_bits = dco_div_bits + FLLD0; // set next higher div level 00280 d >>= 1; 00281 } 00282 00283 UCSCTL0 = 0x000; // Set DCO to lowest Tap 00284 00285 UCSCTL2 &= ~(0x3FF); // Reset FN bits 00286 UCSCTL2 = dco_div_bits | (d - 1); 00287 00288 if (fsystem <= 630) // fsystem < 0.63MHz 00289 UCSCTL1= DCORSEL_0 ; 00290 else if (fsystem < 1250) // 0.63MHz < fsystem < 1.25MHz 00291 UCSCTL1= DCORSEL_1 ; 00292 else if (fsystem < 2500) // 1.25MHz < fsystem < 2.5MHz 00293 UCSCTL1= DCORSEL_2 ; 00294 else if (fsystem < 5000) // 2.5MHz < fsystem < 5MHz 00295 UCSCTL1= DCORSEL_3 ; 00296 else if (fsystem < 10000) // 5MHz < fsystem < 10MHz 00297 UCSCTL1= DCORSEL_4 ; 00298 else if (fsystem < 20000) // 10MHz < fsystem < 20MHz 00299 UCSCTL1= DCORSEL_5 ; 00300 else if (fsystem < 40000) // 20MHz < fsystem < 40MHz 00301 UCSCTL1= DCORSEL_6 ; 00302 else 00303 UCSCTL1= DCORSEL_7 ; 00304 00305 while (SFRIFG1 & OFIFG) { // check OFIFG fault flag 00306 UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags 00307 SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag 00308 } 00309 00310 if (mode == 1) // fsystem > 16000 00311 SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK); // select DCOCLK 00312 else 00313 SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV); // selcet DCODIVCLK 00314 00315 00316 } // End of fll_init()
1.7.1