/*  ===========================================================================
 *  Copyright (c) Texas Instruments Incorporated 2002, 2003, 2004, 2005, 2006, 2008
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/** ============================================================================
 *   @file  cslr_emif16.h
 *
 *   @path  $(CSLPATH)\inc
 *
 *   @desc  This file contains the Register Desciptions for EMIF16
 *
 */
#ifndef _CSLR_EMIF16_H_
#define _CSLR_EMIF16_H_

#include <cslr.h>

#include <tistdtypes.h>


/* Minimum unit = 1 byte */
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 RCSR;
    volatile Uint32 AWCCR;
    volatile Uint8 RSVD0[8];
    volatile Uint32 A1CR;
    volatile Uint32 A2CR;
    volatile Uint32 A3CR;
    volatile Uint32 A4CR;
    volatile Uint8 RSVD1[32];
    volatile Uint32 IRR;
    volatile Uint32 IMR;
    volatile Uint32 IMSR;
    volatile Uint32 IMCR;
    volatile Uint32 IOCR;
    volatile Uint32 IOSR;
    volatile Uint8 RSVD2[8];
    volatile Uint32 NANDFCTL;
    volatile Uint32 NANDFSR;
    volatile Uint32 PMCR;
    volatile Uint8 RSVD3[4];
    volatile Uint32 NFECCCS2;
    volatile Uint32 NFECCCS3;
    volatile Uint32 NFECCCS4;
    volatile Uint32 NFECCCS5;
    volatile Uint8 RSVD4[4];
    volatile Uint32 IODFTEXECNT;
    volatile Uint32 IODFTGBLCTRL;
    volatile Uint8 RSVD5[4];
    volatile Uint32 IODFTTLAMISR;
    volatile Uint32 IODFTTLDMISR;
    volatile Uint32 IODFTTLDCMISR;
    volatile Uint8 RSVD6[20];
    volatile Uint32 MODRELNUM;
    volatile Uint8 RSVD7[8];
    volatile Uint32 NANDF4BECCLR;
    volatile Uint32 NANDF4BECC1R;
    volatile Uint32 NANDF4BECC2R;
    volatile Uint32 NANDF4BECC3R;
    volatile Uint32 NANDF4BECC4R;
    volatile Uint32 NANDFEA1R;
    volatile Uint32 NANDFEA2R;
    volatile Uint32 NANDFEV1R;
    volatile Uint32 NANDFEV2R;
}  CSL_Emif16Regs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* RCSR */

#define CSL_EMIF16_RCSR_BE_MASK (0x80000000u)
#define CSL_EMIF16_RCSR_BE_SHIFT (0x0000001Fu)
#define CSL_EMIF16_RCSR_BE_RESETVAL (0x00000000u)

#define CSL_EMIF16_RCSR_FR_MASK (0x40000000u)
#define CSL_EMIF16_RCSR_FR_SHIFT (0x0000001Eu)
#define CSL_EMIF16_RCSR_FR_RESETVAL (0x00000000u)

#define CSL_EMIF16_RCSR_MODID_MASK (0x3FFF0000u)
#define CSL_EMIF16_RCSR_MODID_SHIFT (0x00000010u)
#define CSL_EMIF16_RCSR_MODID_RESETVAL (0x00000000u)

#define CSL_EMIF16_RCSR_MAJREV_MASK (0x0000FF00u)
#define CSL_EMIF16_RCSR_MAJREV_SHIFT (0x00000008u)
#define CSL_EMIF16_RCSR_MAJREV_RESETVAL (0x00000002u)

#define CSL_EMIF16_RCSR_MINREV_MASK (0x000000FFu)
#define CSL_EMIF16_RCSR_MINREV_SHIFT (0x00000000u)
#define CSL_EMIF16_RCSR_MINREV_RESETVAL (0x00000005u)

#define CSL_EMIF16_RCSR_RESETVAL (0x00000205u)

/* AWCCR */

#define CSL_EMIF16_AWCCR_WP3_MASK (0x80000000u)
#define CSL_EMIF16_AWCCR_WP3_SHIFT (0x0000001Fu)
#define CSL_EMIF16_AWCCR_WP3_RESETVAL (0x00000001u)
/*----WP3 Tokens----*/
#define CSL_EMIF16_AWCCR_WP3_WAITLOW (0x00000000u)
#define CSL_EMIF16_AWCCR_WP3_WAITHIGH (0x00000001u)

#define CSL_EMIF16_AWCCR_WP2_MASK (0x40000000u)
#define CSL_EMIF16_AWCCR_WP2_SHIFT (0x0000001Eu)
#define CSL_EMIF16_AWCCR_WP2_RESETVAL (0x00000001u)
/*----WP2 Tokens----*/
#define CSL_EMIF16_AWCCR_WP2_WAITLOW (0x00000000u)
#define CSL_EMIF16_AWCCR_WP2_WAITHIGH (0x00000001u)

#define CSL_EMIF16_AWCCR_WP1_MASK (0x20000000u)
#define CSL_EMIF16_AWCCR_WP1_SHIFT (0x0000001Du)
#define CSL_EMIF16_AWCCR_WP1_RESETVAL (0x00000001u)
/*----WP1 Tokens----*/
#define CSL_EMIF16_AWCCR_WP1_WAITLOW (0x00000000u)
#define CSL_EMIF16_AWCCR_WP1_WAITHIGH (0x00000001u)

#define CSL_EMIF16_AWCCR_WP0_MASK (0x10000000u)
#define CSL_EMIF16_AWCCR_WP0_SHIFT (0x0000001Cu)
#define CSL_EMIF16_AWCCR_WP0_RESETVAL (0x00000001u)
/*----WP0 Tokens----*/
#define CSL_EMIF16_AWCCR_WP0_WAITLOW (0x00000000u)
#define CSL_EMIF16_AWCCR_WP0_WAITHIGH (0x00000001u)


#define CSL_EMIF16_AWCCR_CS5WAIT_MASK (0x00C00000u)
#define CSL_EMIF16_AWCCR_CS5WAIT_SHIFT (0x00000016u)
#define CSL_EMIF16_AWCCR_CS5WAIT_RESETVAL (0x00000000u)
/*----CS5WAIT Tokens----*/
#define CSL_EMIF16_AWCCR_CS5WAIT_WAIT0 (0x00000000u)

#define CSL_EMIF16_AWCCR_CS4WAIT_MASK (0x00300000u)
#define CSL_EMIF16_AWCCR_CS4WAIT_SHIFT (0x00000014u)
#define CSL_EMIF16_AWCCR_CS4WAIT_RESETVAL (0x00000000u)
/*----CS4WAIT Tokens----*/
#define CSL_EMIF16_AWCCR_CS4WAIT_WAIT0 (0x00000000u)

#define CSL_EMIF16_AWCCR_CS3WAIT_MASK (0x000C0000u)
#define CSL_EMIF16_AWCCR_CS3WAIT_SHIFT (0x00000012u)
#define CSL_EMIF16_AWCCR_CS3WAIT_RESETVAL (0x00000000u)
/*----CS3WAIT Tokens----*/
#define CSL_EMIF16_AWCCR_CS3WAIT_WAIT0 (0x00000000u)

#define CSL_EMIF16_AWCCR_CS2WAIT_MASK (0x00030000u)
#define CSL_EMIF16_AWCCR_CS2WAIT_SHIFT (0x00000010u)
#define CSL_EMIF16_AWCCR_CS2WAIT_RESETVAL (0x00000000u)
/*----CS2WAIT Tokens----*/
#define CSL_EMIF16_AWCCR_CS2WAIT_WAIT0 (0x00000000u)


#define CSL_EMIF16_AWCCR_MAXEXTWAIT_MASK (0x000000FFu)
#define CSL_EMIF16_AWCCR_MAXEXTWAIT_SHIFT (0x00000000u)
#define CSL_EMIF16_AWCCR_MAXEXTWAIT_RESETVAL (0x00000080u)

#define CSL_EMIF16_AWCCR_RESETVAL (0xF0000080u)


/* A1CR */

#define CSL_EMIF16_A1CR_SS_MASK (0x80000000u)
#define CSL_EMIF16_A1CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF16_A1CR_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIF16_A1CR_SS_DISABLE (0x00000000u)
#define CSL_EMIF16_A1CR_SS_ENABLE (0x00000001u)

#define CSL_EMIF16_A1CR_EW_MASK (0x40000000u)
#define CSL_EMIF16_A1CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF16_A1CR_EW_RESETVAL (0x00000000u)
/*----EW Tokens----*/
#define CSL_EMIF16_A1CR_EW_DISABLE (0x00000000u)
#define CSL_EMIF16_A1CR_EW_ENABLE (0x00000001u)

#define CSL_EMIF16_A1CR_WSETUP_MASK (0x3C000000u)
#define CSL_EMIF16_A1CR_WSETUP_SHIFT (0x0000001Au)
#define CSL_EMIF16_A1CR_WSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A1CR_WSTROBE_MASK (0x03F00000u)
#define CSL_EMIF16_A1CR_WSTROBE_SHIFT (0x00000014u)
#define CSL_EMIF16_A1CR_WSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A1CR_WHOLD_MASK (0x000E0000u)
#define CSL_EMIF16_A1CR_WHOLD_SHIFT (0x00000011u)
#define CSL_EMIF16_A1CR_WHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A1CR_RSETUP_MASK (0x0001E000u)
#define CSL_EMIF16_A1CR_RSETUP_SHIFT (0x0000000Du)
#define CSL_EMIF16_A1CR_RSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A1CR_RSTROBE_MASK (0x00001F80u)
#define CSL_EMIF16_A1CR_RSTROBE_SHIFT (0x00000007u)
#define CSL_EMIF16_A1CR_RSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A1CR_RHOLD_MASK (0x00000070u)
#define CSL_EMIF16_A1CR_RHOLD_SHIFT (0x00000004u)
#define CSL_EMIF16_A1CR_RHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A1CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF16_A1CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF16_A1CR_TA_RESETVAL (0x00000003u)

#define CSL_EMIF16_A1CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF16_A1CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF16_A1CR_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIF16_A1CR_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF16_A1CR_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF16_A1CR_ASIZE_32BITS (0x00000002u)

#define CSL_EMIF16_A1CR_RESETVAL (0x3FFFFFFCu)

/* A2CR */

#define CSL_EMIF16_A2CR_SS_MASK (0x80000000u)
#define CSL_EMIF16_A2CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF16_A2CR_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIF16_A2CR_SS_DISABLE (0x00000000u)
#define CSL_EMIF16_A2CR_SS_ENABLE (0x00000001u)

#define CSL_EMIF16_A2CR_EW_MASK (0x40000000u)
#define CSL_EMIF16_A2CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF16_A2CR_EW_RESETVAL (0x00000000u)
/*----EW Tokens----*/
#define CSL_EMIF16_A2CR_EW_DISABLE (0x00000000u)
#define CSL_EMIF16_A2CR_EW_ENABLE (0x00000001u)

#define CSL_EMIF16_A2CR_WSETUP_MASK (0x3C000000u)
#define CSL_EMIF16_A2CR_WSETUP_SHIFT (0x0000001Au)
#define CSL_EMIF16_A2CR_WSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A2CR_WSTROBE_MASK (0x03F00000u)
#define CSL_EMIF16_A2CR_WSTROBE_SHIFT (0x00000014u)
#define CSL_EMIF16_A2CR_WSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A2CR_WHOLD_MASK (0x000E0000u)
#define CSL_EMIF16_A2CR_WHOLD_SHIFT (0x00000011u)
#define CSL_EMIF16_A2CR_WHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A2CR_RSETUP_MASK (0x0001E000u)
#define CSL_EMIF16_A2CR_RSETUP_SHIFT (0x0000000Du)
#define CSL_EMIF16_A2CR_RSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A2CR_RSTROBE_MASK (0x00001F80u)
#define CSL_EMIF16_A2CR_RSTROBE_SHIFT (0x00000007u)
#define CSL_EMIF16_A2CR_RSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A2CR_RHOLD_MASK (0x00000070u)
#define CSL_EMIF16_A2CR_RHOLD_SHIFT (0x00000004u)
#define CSL_EMIF16_A2CR_RHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A2CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF16_A2CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF16_A2CR_TA_RESETVAL (0x00000003u)

#define CSL_EMIF16_A2CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF16_A2CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF16_A2CR_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIF16_A2CR_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF16_A2CR_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF16_A2CR_ASIZE_32BITS (0x00000002u)

#define CSL_EMIF16_A2CR_RESETVAL (0x3FFFFFFCu)

/* A3CR */

#define CSL_EMIF16_A3CR_SS_MASK (0x80000000u)
#define CSL_EMIF16_A3CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF16_A3CR_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIF16_A3CR_SS_DISABLE (0x00000000u)
#define CSL_EMIF16_A3CR_SS_ENABLE (0x00000001u)

#define CSL_EMIF16_A3CR_EW_MASK (0x40000000u)
#define CSL_EMIF16_A3CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF16_A3CR_EW_RESETVAL (0x00000000u)
/*----EW Tokens----*/
#define CSL_EMIF16_A3CR_EW_DISABLE (0x00000000u)
#define CSL_EMIF16_A3CR_EW_ENABLE (0x00000001u)

#define CSL_EMIF16_A3CR_WSETUP_MASK (0x3C000000u)
#define CSL_EMIF16_A3CR_WSETUP_SHIFT (0x0000001Au)
#define CSL_EMIF16_A3CR_WSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A3CR_WSTROBE_MASK (0x03F00000u)
#define CSL_EMIF16_A3CR_WSTROBE_SHIFT (0x00000014u)
#define CSL_EMIF16_A3CR_WSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A3CR_WHOLD_MASK (0x000E0000u)
#define CSL_EMIF16_A3CR_WHOLD_SHIFT (0x00000011u)
#define CSL_EMIF16_A3CR_WHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A3CR_RSETUP_MASK (0x0001E000u)
#define CSL_EMIF16_A3CR_RSETUP_SHIFT (0x0000000Du)
#define CSL_EMIF16_A3CR_RSETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A3CR_RSTROBE_MASK (0x00001F80u)
#define CSL_EMIF16_A3CR_RSTROBE_SHIFT (0x00000007u)
#define CSL_EMIF16_A3CR_RSTROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A3CR_RHOLD_MASK (0x00000070u)
#define CSL_EMIF16_A3CR_RHOLD_SHIFT (0x00000004u)
#define CSL_EMIF16_A3CR_RHOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A3CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF16_A3CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF16_A3CR_TA_RESETVAL (0x00000003u)

#define CSL_EMIF16_A3CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF16_A3CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF16_A3CR_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIF16_A3CR_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF16_A3CR_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF16_A3CR_ASIZE_32BITS (0x00000002u)

#define CSL_EMIF16_A3CR_RESETVAL (0x3FFFFFFCu)

/* A4CR */

#define CSL_EMIF16_A4CR_SS_MASK (0x80000000u)
#define CSL_EMIF16_A4CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF16_A4CR_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIF16_A4CR_SS_DISABLE (0x00000000u)
#define CSL_EMIF16_A4CR_SS_ENABLE (0x00000001u)

#define CSL_EMIF16_A4CR_EW_MASK (0x40000000u)
#define CSL_EMIF16_A4CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF16_A4CR_EW_RESETVAL (0x00000000u)
/*----EW Tokens----*/
#define CSL_EMIF16_A4CR_EW_DISABLE (0x00000000u)
#define CSL_EMIF16_A4CR_EW_ENABLE (0x00000001u)

#define CSL_EMIF16_A4CR_W_SETUP_MASK (0x3C000000u)
#define CSL_EMIF16_A4CR_W_SETUP_SHIFT (0x0000001Au)
#define CSL_EMIF16_A4CR_W_SETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A4CR_W_STROBE_MASK (0x03F00000u)
#define CSL_EMIF16_A4CR_W_STROBE_SHIFT (0x00000014u)
#define CSL_EMIF16_A4CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A4CR_W_HOLD_MASK (0x000E0000u)
#define CSL_EMIF16_A4CR_W_HOLD_SHIFT (0x00000011u)
#define CSL_EMIF16_A4CR_W_HOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A4CR_R_SETUP_MASK (0x0001E000u)
#define CSL_EMIF16_A4CR_R_SETUP_SHIFT (0x0000000Du)
#define CSL_EMIF16_A4CR_R_SETUP_RESETVAL (0x0000000Fu)

#define CSL_EMIF16_A4CR_R_STROBE_MASK (0x00001F80u)
#define CSL_EMIF16_A4CR_R_STROBE_SHIFT (0x00000007u)
#define CSL_EMIF16_A4CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_A4CR_R_HOLD_MASK (0x00000070u)
#define CSL_EMIF16_A4CR_R_HOLD_SHIFT (0x00000004u)
#define CSL_EMIF16_A4CR_R_HOLD_RESETVAL (0x00000007u)

#define CSL_EMIF16_A4CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF16_A4CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF16_A4CR_TA_RESETVAL (0x00000003u)

#define CSL_EMIF16_A4CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF16_A4CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF16_A4CR_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIF16_A4CR_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF16_A4CR_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF16_A4CR_ASIZE_32BITS (0x00000002u)

#define CSL_EMIF16_A4CR_RESETVAL (0x3FFFFFFCu)


/* IRR */

#define CSL_EMIF16_IRR_WR_MASK (0x0000003Cu)
#define CSL_EMIF16_IRR_WR_SHIFT (0x00000002u)
#define CSL_EMIF16_IRR_WR_RESETVAL (0x00000000u)
/*----WR Tokens----*/
#define CSL_EMIF16_IRR_WR_NOACTION (0x00000000u)
#define CSL_EMIF16_IRR_WR_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IRR_LT_MASK (0x00000002u)
#define CSL_EMIF16_IRR_LT_SHIFT (0x00000001u)
#define CSL_EMIF16_IRR_LT_RESETVAL (0x00000000u)
/*----LT Tokens----*/
#define CSL_EMIF16_IRR_LT_NOACTION (0x00000000u)
#define CSL_EMIF16_IRR_LT_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IRR_AT_MASK (0x00000001u)
#define CSL_EMIF16_IRR_AT_SHIFT (0x00000000u)
#define CSL_EMIF16_IRR_AT_RESETVAL (0x00000000u)
/*----AT Tokens----*/
#define CSL_EMIF16_IRR_AT_NOACTION (0x00000000u)
#define CSL_EMIF16_IRR_AT_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IRR_RESETVAL (0x00000000u)

/* IMR */


#define CSL_EMIF16_IMR_WRM_MASK (0x0000003Cu)
#define CSL_EMIF16_IMR_WRM_SHIFT (0x00000002u)
#define CSL_EMIF16_IMR_WRM_RESETVAL (0x00000000u)
/*----WRM Tokens----*/
#define CSL_EMIF16_IMR_WRM_NOACTION (0x00000000u)
#define CSL_EMIF16_IMR_WRM_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IMR_LTM_MASK (0x00000002u)
#define CSL_EMIF16_IMR_LTM_SHIFT (0x00000001u)
#define CSL_EMIF16_IMR_LTM_RESETVAL (0x00000000u)
/*----LTM Tokens----*/
#define CSL_EMIF16_IMR_LTM_NOACTION (0x00000000u)
#define CSL_EMIF16_IMR_LTM_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IMR_ATM_MASK (0x00000001u)
#define CSL_EMIF16_IMR_ATM_SHIFT (0x00000000u)
#define CSL_EMIF16_IMR_ATM_RESETVAL (0x00000000u)
/*----ATM Tokens----*/
#define CSL_EMIF16_IMR_ATM_NOACTION (0x00000000u)
#define CSL_EMIF16_IMR_ATM_CLEARBIT (0x00000001u)

#define CSL_EMIF16_IMR_RESETVAL (0x00000000u)

/* IMSR */


#define CSL_EMIF16_IMSR_WRMSET_MASK (0x0000003Cu)
#define CSL_EMIF16_IMSR_WRMSET_SHIFT (0x00000002u)
#define CSL_EMIF16_IMSR_WRMSET_RESETVAL (0x00000000u)
/*----WRMSET Tokens----*/
#define CSL_EMIF16_IMSR_WRMSET_NOACTION (0x00000000u)
#define CSL_EMIF16_IMSR_WRMSET_ENABLE (0x00000001u)

#define CSL_EMIF16_IMSR_LTMSET_MASK (0x00000002u)
#define CSL_EMIF16_IMSR_LTMSET_SHIFT (0x00000001u)
#define CSL_EMIF16_IMSR_LTMSET_RESETVAL (0x00000000u)
/*----LTMSET Tokens----*/
#define CSL_EMIF16_IMSR_LTMSET_NOACTION (0x00000000u)
#define CSL_EMIF16_IMSR_LTMSET_ENABLE (0x00000001u)

#define CSL_EMIF16_IMSR_ATMSET_MASK (0x00000001u)
#define CSL_EMIF16_IMSR_ATMSET_SHIFT (0x00000000u)
#define CSL_EMIF16_IMSR_ATMSET_RESETVAL (0x00000000u)
/*----ATMSET Tokens----*/
#define CSL_EMIF16_IMSR_ATMSET_NOACTION (0x00000000u)
#define CSL_EMIF16_IMSR_ATMSET_ENABLE (0x00000001u)

#define CSL_EMIF16_IMSR_RESETVAL (0x00000000u)

/* IMCR */


#define CSL_EMIF16_IMCR_WRMCLR_MASK (0x0000003Cu)
#define CSL_EMIF16_IMCR_WRMCLR_SHIFT (0x00000002u)
#define CSL_EMIF16_IMCR_WRMCLR_RESETVAL (0x00000000u)
/*----WRMCLR Tokens----*/
#define CSL_EMIF16_IMCR_WRMCLR_NOACTION (0x00000000u)
#define CSL_EMIF16_IMCR_WRMCLR_DISABLE (0x00000001u)

#define CSL_EMIF16_IMCR_LTMCLR_MASK (0x00000002u)
#define CSL_EMIF16_IMCR_LTMCLR_SHIFT (0x00000001u)
#define CSL_EMIF16_IMCR_LTMCLR_RESETVAL (0x00000000u)
/*----LTMCLR Tokens----*/
#define CSL_EMIF16_IMCR_LTMCLR_NOACTION (0x00000000u)
#define CSL_EMIF16_IMCR_LTMCLR_DISABLE (0x00000001u)

#define CSL_EMIF16_IMCR_ATMCLR_MASK (0x00000001u)
#define CSL_EMIF16_IMCR_ATMCLR_SHIFT (0x00000000u)
#define CSL_EMIF16_IMCR_ATMCLR_RESETVAL (0x00000000u)
/*----ATMCLR Tokens----*/
#define CSL_EMIF16_IMCR_ATMCLR_NOACTION (0x00000000u)
#define CSL_EMIF16_IMCR_ATMCLR_DISABLE (0x00000001u)

#define CSL_EMIF16_IMCR_RESETVAL (0x00000000u)

/* IOCR */


#define CSL_EMIF16_IOCR_IOCTRL_MASK (0x0000FFFFu)
#define CSL_EMIF16_IOCR_IOCTRL_SHIFT (0x00000000u)
#define CSL_EMIF16_IOCR_IOCTRL_RESETVAL (0x00000000u)

#define CSL_EMIF16_IOCR_RESETVAL (0x00000000u)

/* IOSR */


#define CSL_EMIF16_IOSR_IOSTAT_MASK (0x0000000Fu)
#define CSL_EMIF16_IOSR_IOSTAT_SHIFT (0x00000000u)
#define CSL_EMIF16_IOSR_IOSTAT_RESETVAL (0x00000000u)

#define CSL_EMIF16_IOSR_RESETVAL (0x00000000u)

/* NANDFCTL */


#define CSL_EMIF16_NANDFCTL_ADDR_CALC_ST_MASK (0x00002000u)
#define CSL_EMIF16_NANDFCTL_ADDR_CALC_ST_SHIFT (0x0000000Du)
#define CSL_EMIF16_NANDFCTL_ADDR_CALC_ST_RESETVAL (0x00000000u)
/*----ADDR_CALC_ST Tokens----*/
#define CSL_EMIF16_NANDFCTL_ADDR_CALC_ST_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_ADDR_CALC_ST_STARTCALC (0x00000001u)

#define CSL_EMIF16_NANDFCTL_4BIT_ECC_ST_MASK (0x00001000u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_ST_SHIFT (0x0000000Cu)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_ST_RESETVAL (0x00000000u)
/*----4BIT_ECC_ST Tokens----*/
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_ST_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_ST_STARTCALC (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS5ECC_MASK (0x00000800u)
#define CSL_EMIF16_NANDFCTL_CS5ECC_SHIFT (0x0000000Bu)
#define CSL_EMIF16_NANDFCTL_CS5ECC_RESETVAL (0x00000000u)
/*----CS5ECC Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS5ECC_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS5ECC_STARTCALC (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS4ECC_MASK (0x00000400u)
#define CSL_EMIF16_NANDFCTL_CS4ECC_SHIFT (0x0000000Au)
#define CSL_EMIF16_NANDFCTL_CS4ECC_RESETVAL (0x00000000u)
/*----CS4ECC Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS4ECC_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS4ECC_STARTCALC (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS3ECC_MASK (0x00000200u)
#define CSL_EMIF16_NANDFCTL_CS3ECC_SHIFT (0x00000009u)
#define CSL_EMIF16_NANDFCTL_CS3ECC_RESETVAL (0x00000000u)
/*----CS3ECC Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS3ECC_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS3ECC_STARTCALC (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS2ECC_MASK (0x00000100u)
#define CSL_EMIF16_NANDFCTL_CS2ECC_SHIFT (0x00000008u)
#define CSL_EMIF16_NANDFCTL_CS2ECC_RESETVAL (0x00000000u)
/*----CS2ECC Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS2ECC_NOACTION (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS2ECC_STARTCALC (0x00000001u)


#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_MASK (0x00000030u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_SHIFT (0x00000004u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_RESETVAL (0x00000000u)
/*----4BIT_ECC_SEL Tokens----*/
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_SELCS2 (0x00000000u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_SELCS3 (0x00000001u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_SELCS4 (0x00000002u)
#define CSL_EMIF16_NANDFCTL_4BIT_ECC_SEL_SELCS5 (0x00000003u)

#define CSL_EMIF16_NANDFCTL_CS5NAND_MASK (0x00000008u)
#define CSL_EMIF16_NANDFCTL_CS5NAND_SHIFT (0x00000003u)
#define CSL_EMIF16_NANDFCTL_CS5NAND_RESETVAL (0x00000000u)
/*----CS5NAND Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS5NAND_DISABLE (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS5NAND_ENABLE (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS4NAND_MASK (0x00000004u)
#define CSL_EMIF16_NANDFCTL_CS4NAND_SHIFT (0x00000002u)
#define CSL_EMIF16_NANDFCTL_CS4NAND_RESETVAL (0x00000000u)
/*----CS4NAND Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS4NAND_DISABLE (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS4NAND_ENABLE (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS3NAND_MASK (0x00000002u)
#define CSL_EMIF16_NANDFCTL_CS3NAND_SHIFT (0x00000001u)
#define CSL_EMIF16_NANDFCTL_CS3NAND_RESETVAL (0x00000000u)
/*----CS3NAND Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS3NAND_DISABLE (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS3NAND_ENABLE (0x00000001u)

#define CSL_EMIF16_NANDFCTL_CS2NAND_MASK (0x00000001u)
#define CSL_EMIF16_NANDFCTL_CS2NAND_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS2NAND_RESETVAL (u)
/*----CS2NAND Tokens----*/
#define CSL_EMIF16_NANDFCTL_CS2NAND_DISABLE (0x00000000u)
#define CSL_EMIF16_NANDFCTL_CS2NAND_ENABLE (0x00000001u)

#define CSL_EMIF16_NANDFCTL_RESETVAL (0x00000000u)

/* NANDFSR */


#define CSL_EMIF16_NANDFSR_ERR_NUM_MASK (0x00030000u)
#define CSL_EMIF16_NANDFSR_ERR_NUM_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDFSR_ERR_NUM_RESETVAL (0x00000000u)
/*----ERR_NUM Tokens----*/
#define CSL_EMIF16_NANDFSR_ERR_NUM_ERROR1 (0x00000000u)
#define CSL_EMIF16_NANDFSR_ERR_NUM_ERROR2 (0x00000001u)
#define CSL_EMIF16_NANDFSR_ERR_NUM_ERROR3 (0x00000002u)
#define CSL_EMIF16_NANDFSR_ERR_NUM_ERROR4 (0x00000003u)


#define CSL_EMIF16_NANDFSR_CORR_STATE_MASK (0x00000F00u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_SHIFT (0x00000008u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_RESETVAL (0x00000000u)
/*----CORR_STATE Tokens----*/
#define CSL_EMIF16_NANDFSR_CORR_STATE_NOERROR (0x00000000u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_NOCORRECT (0x00000001u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CORRECTCOMPLETE2 (0x00000002u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CORRECTCOMPLETE3 (0x00000003u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CALCNUMERR (0x00000005u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_PREPERROR6 (0x00000006u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_PREPERROR7 (0x00000007u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_SEARCHERR (0x00000008u)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CALCERR12 (0x0000000Cu)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CALCERR13 (0x0000000Du)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CALCERR14 (0x0000000Eu)
#define CSL_EMIF16_NANDFSR_CORR_STATE_CALCERR15 (0x0000000Fu)


#define CSL_EMIF16_NANDFSR_WAITSTAT_MASK (0x0000000Fu)
#define CSL_EMIF16_NANDFSR_WAITSTAT_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFSR_WAITSTAT_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDFSR_RESETVAL (0x00000000u)

/* PMCR */

#define CSL_EMIF16_PMCR_CS5PGDEL_MASK (0xFC000000u)
#define CSL_EMIF16_PMCR_CS5PGDEL_SHIFT (0x0000001Au)
#define CSL_EMIF16_PMCR_CS5PGDEL_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_PMCR_CS5PGSIZE_MASK (0x02000000u)
#define CSL_EMIF16_PMCR_CS5PGSIZE_SHIFT (0x00000019u)
#define CSL_EMIF16_PMCR_CS5PGSIZE_RESETVAL (0x00000000u)
/*----CS5PGSIZE Tokens----*/
#define CSL_EMIF16_PMCR_CS5PGSIZE_4WORD (0x00000000u)
#define CSL_EMIF16_PMCR_CS5PGSIZE_8WORD (0x00000001u)

#define CSL_EMIF16_PMCR_CS5PGMDEN_MASK (0x01000000u)
#define CSL_EMIF16_PMCR_CS5PGMDEN_SHIFT (0x00000018u)
#define CSL_EMIF16_PMCR_CS5PGMDEN_RESETVAL (0x00000000u)
/*----CS5PGMDEN Tokens----*/
#define CSL_EMIF16_PMCR_CS5PGMDEN_DISABLE (0x00000000u)
#define CSL_EMIF16_PMCR_CS5PGMDEN_ENABLE (0x00000001u)

#define CSL_EMIF16_PMCR_CS4PGDEL_MASK (0x00FC0000u)
#define CSL_EMIF16_PMCR_CS4PGDEL_SHIFT (0x00000012u)
#define CSL_EMIF16_PMCR_CS4PGDEL_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_PMCR_CS4PGSIZE_MASK (0x00020000u)
#define CSL_EMIF16_PMCR_CS4PGSIZE_SHIFT (0x00000011u)
#define CSL_EMIF16_PMCR_CS4PGSIZE_RESETVAL (0x00000000u)
/*----CS4PGSIZE Tokens----*/
#define CSL_EMIF16_PMCR_CS4PGSIZE_4WORD (0x00000000u)
#define CSL_EMIF16_PMCR_CS4PGSIZE_8WORD (0x00000001u)

#define CSL_EMIF16_PMCR_CS4PGMDEN_MASK (0x00010000u)
#define CSL_EMIF16_PMCR_CS4PGMDEN_SHIFT (0x00000010u)
#define CSL_EMIF16_PMCR_CS4PGMDEN_RESETVAL (0x00000000u)
/*----CS4PGMDEN Tokens----*/
#define CSL_EMIF16_PMCR_CS4PGMDEN_DISABLE (0x00000000u)
#define CSL_EMIF16_PMCR_CS4PGMDEN_ENABLE (0x00000001u)

#define CSL_EMIF16_PMCR_CS3PGDEL_MASK (0x0000FC00u)
#define CSL_EMIF16_PMCR_CS3PGDEL_SHIFT (0x0000000Au)
#define CSL_EMIF16_PMCR_CS3PGDEL_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_PMCR_CS3PGSIZE_MASK (0x00000200u)
#define CSL_EMIF16_PMCR_CS3PGSIZE_SHIFT (0x00000009u)
#define CSL_EMIF16_PMCR_CS3PGSIZE_RESETVAL (0x00000000u)
/*----CS3PGSIZE Tokens----*/
#define CSL_EMIF16_PMCR_CS3PGSIZE_4WORD (0x00000000u)
#define CSL_EMIF16_PMCR_CS3PGSIZE_8WORD (0x00000001u)

#define CSL_EMIF16_PMCR_CS3PGMDEN_MASK (0x00000100u)
#define CSL_EMIF16_PMCR_CS3PGMDEN_SHIFT (0x00000008u)
#define CSL_EMIF16_PMCR_CS3PGMDEN_RESETVAL (0x00000000u)
/*----CS3PGMDEN Tokens----*/
#define CSL_EMIF16_PMCR_CS3PGMDEN_DISABLE (0x00000000u)
#define CSL_EMIF16_PMCR_CS3PGMDEN_ENABLE (0x00000001u)

#define CSL_EMIF16_PMCR_CS2PGDEL_MASK (0x000000FCu)
#define CSL_EMIF16_PMCR_CS2PGDEL_SHIFT (0x00000002u)
#define CSL_EMIF16_PMCR_CS2PGDEL_RESETVAL (0x0000003Fu)

#define CSL_EMIF16_PMCR_CS2PGSIZE_MASK (0x00000002u)
#define CSL_EMIF16_PMCR_CS2PGSIZE_SHIFT (0x00000001u)
#define CSL_EMIF16_PMCR_CS2PGSIZE_RESETVAL (0x00000000u)
/*----CS2PGSIZE Tokens----*/
#define CSL_EMIF16_PMCR_CS2PGSIZE_4WORD (0x00000000u)
#define CSL_EMIF16_PMCR_CS2PGSIZE_8WORD (0x00000001u)

#define CSL_EMIF16_PMCR_CS2PGMDEN_MASK (0x00000001u)
#define CSL_EMIF16_PMCR_CS2PGMDEN_SHIFT (0x00000000u)
#define CSL_EMIF16_PMCR_CS2PGMDEN_RESETVAL (0x00000000u)
/*----CS2PGMDEN Tokens----*/
#define CSL_EMIF16_PMCR_CS2PGMDEN_DISABLE (0x00000000u)

#define CSL_EMIF16_PMCR_RESETVAL (0xFCFCFCFCu)

/* NFECCCS2 */


#define CSL_EMIF16_NFECCCS2_P2048O_MASK (0x08000000u)
#define CSL_EMIF16_NFECCCS2_P2048O_SHIFT (0x0000001Bu)
#define CSL_EMIF16_NFECCCS2_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P1024O_MASK (0x04000000u)
#define CSL_EMIF16_NFECCCS2_P1024O_SHIFT (0x0000001Au)
#define CSL_EMIF16_NFECCCS2_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P512O_MASK (0x02000000u)
#define CSL_EMIF16_NFECCCS2_P512O_SHIFT (0x00000019u)
#define CSL_EMIF16_NFECCCS2_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P256O_MASK (0x01000000u)
#define CSL_EMIF16_NFECCCS2_P256O_SHIFT (0x00000018u)
#define CSL_EMIF16_NFECCCS2_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P128O_MASK (0x00800000u)
#define CSL_EMIF16_NFECCCS2_P128O_SHIFT (0x00000017u)
#define CSL_EMIF16_NFECCCS2_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P64O_MASK (0x00400000u)
#define CSL_EMIF16_NFECCCS2_P64O_SHIFT (0x00000016u)
#define CSL_EMIF16_NFECCCS2_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P32O_MASK (0x00200000u)
#define CSL_EMIF16_NFECCCS2_P32O_SHIFT (0x00000015u)
#define CSL_EMIF16_NFECCCS2_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P16O_MASK (0x00100000u)
#define CSL_EMIF16_NFECCCS2_P16O_SHIFT (0x00000014u)
#define CSL_EMIF16_NFECCCS2_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P8O_MASK (0x00080000u)
#define CSL_EMIF16_NFECCCS2_P8O_SHIFT (0x00000013u)
#define CSL_EMIF16_NFECCCS2_P8O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P4O_MASK (0x00040000u)
#define CSL_EMIF16_NFECCCS2_P4O_SHIFT (0x00000012u)
#define CSL_EMIF16_NFECCCS2_P4O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P2O_MASK (0x00020000u)
#define CSL_EMIF16_NFECCCS2_P2O_SHIFT (0x00000011u)
#define CSL_EMIF16_NFECCCS2_P2O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P1O_MASK (0x00010000u)
#define CSL_EMIF16_NFECCCS2_P1O_SHIFT (0x00000010u)
#define CSL_EMIF16_NFECCCS2_P1O_RESETVAL (0x00000000u)


#define CSL_EMIF16_NFECCCS2_P2048E_MASK (0x00000800u)
#define CSL_EMIF16_NFECCCS2_P2048E_SHIFT (0x0000000Bu)
#define CSL_EMIF16_NFECCCS2_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P1024E_MASK (0x00000400u)
#define CSL_EMIF16_NFECCCS2_P1024E_SHIFT (0x0000000Au)
#define CSL_EMIF16_NFECCCS2_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P512E_MASK (0x00000200u)
#define CSL_EMIF16_NFECCCS2_P512E_SHIFT (0x00000009u)
#define CSL_EMIF16_NFECCCS2_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P256E_MASK (0x00000100u)
#define CSL_EMIF16_NFECCCS2_P256E_SHIFT (0x00000008u)
#define CSL_EMIF16_NFECCCS2_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P128E_MASK (0x00000080u)
#define CSL_EMIF16_NFECCCS2_P128E_SHIFT (0x00000007u)
#define CSL_EMIF16_NFECCCS2_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P64E_MASK (0x00000040u)
#define CSL_EMIF16_NFECCCS2_P64E_SHIFT (0x00000006u)
#define CSL_EMIF16_NFECCCS2_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P32E_MASK (0x00000020u)
#define CSL_EMIF16_NFECCCS2_P32E_SHIFT (0x00000005u)
#define CSL_EMIF16_NFECCCS2_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P16E_MASK (0x00000010u)
#define CSL_EMIF16_NFECCCS2_P16E_SHIFT (0x00000004u)
#define CSL_EMIF16_NFECCCS2_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P8E_MASK (0x00000008u)
#define CSL_EMIF16_NFECCCS2_P8E_SHIFT (0x00000003u)
#define CSL_EMIF16_NFECCCS2_P8E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P4E_MASK (0x00000004u)
#define CSL_EMIF16_NFECCCS2_P4E_SHIFT (0x00000002u)
#define CSL_EMIF16_NFECCCS2_P4E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P2E_MASK (0x00000002u)
#define CSL_EMIF16_NFECCCS2_P2E_SHIFT (0x00000001u)
#define CSL_EMIF16_NFECCCS2_P2E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_P1E_MASK (0x00000001u)
#define CSL_EMIF16_NFECCCS2_P1E_SHIFT (0x00000000u)
#define CSL_EMIF16_NFECCCS2_P1E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS2_RESETVAL (0x00000000u)

/* NFECCCS3 */


#define CSL_EMIF16_NFECCCS3_P2048O_MASK (0x08000000u)
#define CSL_EMIF16_NFECCCS3_P2048O_SHIFT (0x0000001Bu)
#define CSL_EMIF16_NFECCCS3_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P1024O_MASK (0x04000000u)
#define CSL_EMIF16_NFECCCS3_P1024O_SHIFT (0x0000001Au)
#define CSL_EMIF16_NFECCCS3_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P512O_MASK (0x02000000u)
#define CSL_EMIF16_NFECCCS3_P512O_SHIFT (0x00000019u)
#define CSL_EMIF16_NFECCCS3_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P256O_MASK (0x01000000u)
#define CSL_EMIF16_NFECCCS3_P256O_SHIFT (0x00000018u)
#define CSL_EMIF16_NFECCCS3_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P128O_MASK (0x00800000u)
#define CSL_EMIF16_NFECCCS3_P128O_SHIFT (0x00000017u)
#define CSL_EMIF16_NFECCCS3_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P64O_MASK (0x00400000u)
#define CSL_EMIF16_NFECCCS3_P64O_SHIFT (0x00000016u)
#define CSL_EMIF16_NFECCCS3_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P32O_MASK (0x00200000u)
#define CSL_EMIF16_NFECCCS3_P32O_SHIFT (0x00000015u)
#define CSL_EMIF16_NFECCCS3_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P16O_MASK (0x00100000u)
#define CSL_EMIF16_NFECCCS3_P16O_SHIFT (0x00000014u)
#define CSL_EMIF16_NFECCCS3_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P8O_MASK (0x00080000u)
#define CSL_EMIF16_NFECCCS3_P8O_SHIFT (0x00000013u)
#define CSL_EMIF16_NFECCCS3_P8O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P4O_MASK (0x00040000u)
#define CSL_EMIF16_NFECCCS3_P4O_SHIFT (0x00000012u)
#define CSL_EMIF16_NFECCCS3_P4O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P2O_MASK (0x00020000u)
#define CSL_EMIF16_NFECCCS3_P2O_SHIFT (0x00000011u)
#define CSL_EMIF16_NFECCCS3_P2O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P1O_MASK (0x00010000u)
#define CSL_EMIF16_NFECCCS3_P1O_SHIFT (0x00000010u)
#define CSL_EMIF16_NFECCCS3_P1O_RESETVAL (0x00000000u)


#define CSL_EMIF16_NFECCCS3_P2048E_MASK (0x00000800u)
#define CSL_EMIF16_NFECCCS3_P2048E_SHIFT (0x0000000Bu)
#define CSL_EMIF16_NFECCCS3_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P1024E_MASK (0x00000400u)
#define CSL_EMIF16_NFECCCS3_P1024E_SHIFT (0x0000000Au)
#define CSL_EMIF16_NFECCCS3_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P512E_MASK (0x00000200u)
#define CSL_EMIF16_NFECCCS3_P512E_SHIFT (0x00000009u)
#define CSL_EMIF16_NFECCCS3_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P256E_MASK (0x00000100u)
#define CSL_EMIF16_NFECCCS3_P256E_SHIFT (0x00000008u)
#define CSL_EMIF16_NFECCCS3_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P128E_MASK (0x00000080u)
#define CSL_EMIF16_NFECCCS3_P128E_SHIFT (0x00000007u)
#define CSL_EMIF16_NFECCCS3_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P64E_MASK (0x00000040u)
#define CSL_EMIF16_NFECCCS3_P64E_SHIFT (0x00000006u)
#define CSL_EMIF16_NFECCCS3_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P32E_MASK (0x00000020u)
#define CSL_EMIF16_NFECCCS3_P32E_SHIFT (0x00000005u)
#define CSL_EMIF16_NFECCCS3_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P16E_MASK (0x00000010u)
#define CSL_EMIF16_NFECCCS3_P16E_SHIFT (0x00000004u)
#define CSL_EMIF16_NFECCCS3_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P8E_MASK (0x00000008u)
#define CSL_EMIF16_NFECCCS3_P8E_SHIFT (0x00000003u)
#define CSL_EMIF16_NFECCCS3_P8E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P4E_MASK (0x00000004u)
#define CSL_EMIF16_NFECCCS3_P4E_SHIFT (0x00000002u)
#define CSL_EMIF16_NFECCCS3_P4E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P2E_MASK (0x00000002u)
#define CSL_EMIF16_NFECCCS3_P2E_SHIFT (0x00000001u)
#define CSL_EMIF16_NFECCCS3_P2E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_P1E_MASK (0x00000001u)
#define CSL_EMIF16_NFECCCS3_P1E_SHIFT (0x00000000u)
#define CSL_EMIF16_NFECCCS3_P1E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS3_RESETVAL (0x00000000u)

/* NFECCCS4 */


#define CSL_EMIF16_NFECCCS4_P2048O_MASK (0x08000000u)
#define CSL_EMIF16_NFECCCS4_P2048O_SHIFT (0x0000001Bu)
#define CSL_EMIF16_NFECCCS4_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P1024O_MASK (0x04000000u)
#define CSL_EMIF16_NFECCCS4_P1024O_SHIFT (0x0000001Au)
#define CSL_EMIF16_NFECCCS4_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P512O_MASK (0x02000000u)
#define CSL_EMIF16_NFECCCS4_P512O_SHIFT (0x00000019u)
#define CSL_EMIF16_NFECCCS4_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P256O_MASK (0x01000000u)
#define CSL_EMIF16_NFECCCS4_P256O_SHIFT (0x00000018u)
#define CSL_EMIF16_NFECCCS4_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P128O_MASK (0x00800000u)
#define CSL_EMIF16_NFECCCS4_P128O_SHIFT (0x00000017u)
#define CSL_EMIF16_NFECCCS4_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P64O_MASK (0x00400000u)
#define CSL_EMIF16_NFECCCS4_P64O_SHIFT (0x00000016u)
#define CSL_EMIF16_NFECCCS4_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P32O_MASK (0x00200000u)
#define CSL_EMIF16_NFECCCS4_P32O_SHIFT (0x00000015u)
#define CSL_EMIF16_NFECCCS4_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P16O_MASK (0x00100000u)
#define CSL_EMIF16_NFECCCS4_P16O_SHIFT (0x00000014u)
#define CSL_EMIF16_NFECCCS4_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P8O_MASK (0x00080000u)
#define CSL_EMIF16_NFECCCS4_P8O_SHIFT (0x00000013u)
#define CSL_EMIF16_NFECCCS4_P8O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P4O_MASK (0x00040000u)
#define CSL_EMIF16_NFECCCS4_P4O_SHIFT (0x00000012u)
#define CSL_EMIF16_NFECCCS4_P4O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P2O_MASK (0x00020000u)
#define CSL_EMIF16_NFECCCS4_P2O_SHIFT (0x00000011u)
#define CSL_EMIF16_NFECCCS4_P2O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P1O_MASK (0x00010000u)
#define CSL_EMIF16_NFECCCS4_P1O_SHIFT (0x00000010u)
#define CSL_EMIF16_NFECCCS4_P1O_RESETVAL (0x00000000u)


#define CSL_EMIF16_NFECCCS4_P2048E_MASK (0x00000800u)
#define CSL_EMIF16_NFECCCS4_P2048E_SHIFT (0x0000000Bu)
#define CSL_EMIF16_NFECCCS4_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P1024E_MASK (0x00000400u)
#define CSL_EMIF16_NFECCCS4_P1024E_SHIFT (0x0000000Au)
#define CSL_EMIF16_NFECCCS4_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P512E_MASK (0x00000200u)
#define CSL_EMIF16_NFECCCS4_P512E_SHIFT (0x00000009u)
#define CSL_EMIF16_NFECCCS4_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P256E_MASK (0x00000100u)
#define CSL_EMIF16_NFECCCS4_P256E_SHIFT (0x00000008u)
#define CSL_EMIF16_NFECCCS4_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P128E_MASK (0x00000080u)
#define CSL_EMIF16_NFECCCS4_P128E_SHIFT (0x00000007u)
#define CSL_EMIF16_NFECCCS4_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P64E_MASK (0x00000040u)
#define CSL_EMIF16_NFECCCS4_P64E_SHIFT (0x00000006u)
#define CSL_EMIF16_NFECCCS4_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P32E_MASK (0x00000020u)
#define CSL_EMIF16_NFECCCS4_P32E_SHIFT (0x00000005u)
#define CSL_EMIF16_NFECCCS4_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P16E_MASK (0x00000010u)
#define CSL_EMIF16_NFECCCS4_P16E_SHIFT (0x00000004u)
#define CSL_EMIF16_NFECCCS4_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P8E_MASK (0x00000008u)
#define CSL_EMIF16_NFECCCS4_P8E_SHIFT (0x00000003u)
#define CSL_EMIF16_NFECCCS4_P8E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P4E_MASK (0x00000004u)
#define CSL_EMIF16_NFECCCS4_P4E_SHIFT (0x00000002u)
#define CSL_EMIF16_NFECCCS4_P4E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P2E_MASK (0x00000002u)
#define CSL_EMIF16_NFECCCS4_P2E_SHIFT (0x00000001u)
#define CSL_EMIF16_NFECCCS4_P2E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_P1E_MASK (0x00000001u)
#define CSL_EMIF16_NFECCCS4_P1E_SHIFT (0x00000000u)
#define CSL_EMIF16_NFECCCS4_P1E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS4_RESETVAL (0x00000000u)

/* NFECCCS5 */


#define CSL_EMIF16_NFECCCS5_P2048O_MASK (0x08000000u)
#define CSL_EMIF16_NFECCCS5_P2048O_SHIFT (0x0000001Bu)
#define CSL_EMIF16_NFECCCS5_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P1024O_MASK (0x04000000u)
#define CSL_EMIF16_NFECCCS5_P1024O_SHIFT (0x0000001Au)
#define CSL_EMIF16_NFECCCS5_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P512O_MASK (0x02000000u)
#define CSL_EMIF16_NFECCCS5_P512O_SHIFT (0x00000019u)
#define CSL_EMIF16_NFECCCS5_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P256O_MASK (0x01000000u)
#define CSL_EMIF16_NFECCCS5_P256O_SHIFT (0x00000018u)
#define CSL_EMIF16_NFECCCS5_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P128O_MASK (0x00800000u)
#define CSL_EMIF16_NFECCCS5_P128O_SHIFT (0x00000017u)
#define CSL_EMIF16_NFECCCS5_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P64O_MASK (0x00400000u)
#define CSL_EMIF16_NFECCCS5_P64O_SHIFT (0x00000016u)
#define CSL_EMIF16_NFECCCS5_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P32O_MASK (0x00200000u)
#define CSL_EMIF16_NFECCCS5_P32O_SHIFT (0x00000015u)
#define CSL_EMIF16_NFECCCS5_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P16O_MASK (0x00100000u)
#define CSL_EMIF16_NFECCCS5_P16O_SHIFT (0x00000014u)
#define CSL_EMIF16_NFECCCS5_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P8O_MASK (0x00080000u)
#define CSL_EMIF16_NFECCCS5_P8O_SHIFT (0x00000013u)
#define CSL_EMIF16_NFECCCS5_P8O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P4O_MASK (0x00040000u)
#define CSL_EMIF16_NFECCCS5_P4O_SHIFT (0x00000012u)
#define CSL_EMIF16_NFECCCS5_P4O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P2O_MASK (0x00020000u)
#define CSL_EMIF16_NFECCCS5_P2O_SHIFT (0x00000011u)
#define CSL_EMIF16_NFECCCS5_P2O_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P1O_MASK (0x00010000u)
#define CSL_EMIF16_NFECCCS5_P1O_SHIFT (0x00000010u)
#define CSL_EMIF16_NFECCCS5_P1O_RESETVAL (0x00000000u)


#define CSL_EMIF16_NFECCCS5_P2048E_MASK (0x00000800u)
#define CSL_EMIF16_NFECCCS5_P2048E_SHIFT (0x0000000Bu)
#define CSL_EMIF16_NFECCCS5_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P1024E_MASK (0x00000400u)
#define CSL_EMIF16_NFECCCS5_P1024E_SHIFT (0x0000000Au)
#define CSL_EMIF16_NFECCCS5_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P512E_MASK (0x00000200u)
#define CSL_EMIF16_NFECCCS5_P512E_SHIFT (0x00000009u)
#define CSL_EMIF16_NFECCCS5_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P256E_MASK (0x00000100u)
#define CSL_EMIF16_NFECCCS5_P256E_SHIFT (0x00000008u)
#define CSL_EMIF16_NFECCCS5_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P128E_MASK (0x00000080u)
#define CSL_EMIF16_NFECCCS5_P128E_SHIFT (0x00000007u)
#define CSL_EMIF16_NFECCCS5_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P64E_MASK (0x00000040u)
#define CSL_EMIF16_NFECCCS5_P64E_SHIFT (0x00000006u)
#define CSL_EMIF16_NFECCCS5_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P32E_MASK (0x00000020u)
#define CSL_EMIF16_NFECCCS5_P32E_SHIFT (0x00000005u)
#define CSL_EMIF16_NFECCCS5_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P16E_MASK (0x00000010u)
#define CSL_EMIF16_NFECCCS5_P16E_SHIFT (0x00000004u)
#define CSL_EMIF16_NFECCCS5_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P8E_MASK (0x00000008u)
#define CSL_EMIF16_NFECCCS5_P8E_SHIFT (0x00000003u)
#define CSL_EMIF16_NFECCCS5_P8E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P4E_MASK (0x00000004u)
#define CSL_EMIF16_NFECCCS5_P4E_SHIFT (0x00000002u)
#define CSL_EMIF16_NFECCCS5_P4E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P2E_MASK (0x00000002u)
#define CSL_EMIF16_NFECCCS5_P2E_SHIFT (0x00000001u)
#define CSL_EMIF16_NFECCCS5_P2E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_P1E_MASK (0x00000001u)
#define CSL_EMIF16_NFECCCS5_P1E_SHIFT (0x00000000u)
#define CSL_EMIF16_NFECCCS5_P1E_RESETVAL (0x00000000u)

#define CSL_EMIF16_NFECCCS5_RESETVAL (0x00000000u)

/* IODFTEXECNT */


#define CSL_EMIF16_IODFTEXECNT_TLEC_MASK (0x0000FFFFu)
#define CSL_EMIF16_IODFTEXECNT_TLEC_SHIFT (0x00000000u)
#define CSL_EMIF16_IODFTEXECNT_TLEC_RESETVAL (0x00000000u)

#define CSL_EMIF16_IODFTEXECNT_RESETVAL (0x00000000u)

/* IODFTGBLCTRL */


#define CSL_EMIF16_IODFTGBLCTRL_MT_MASK (0x00004000u)
#define CSL_EMIF16_IODFTGBLCTRL_MT_SHIFT (0x0000000Eu)
#define CSL_EMIF16_IODFTGBLCTRL_MT_RESETVAL (0x00000000u)

#define CSL_EMIF16_IODFTGBLCTRL_ACT_CAP_EN_MASK (0x00002000u)

#define CSL_EMIF16_IODFTGBLCTRL_OPG_LD_MASK (0x00001000u)
#define CSL_EMIF16_IODFTGBLCTRL_OPG_LD_SHIFT (0x0000000Cu)
#define CSL_EMIF16_IODFTGBLCTRL_OPG_LD_RESETVAL (0x00000000u)


#define CSL_EMIF16_IODFTGBLCTRL_MMS_MASK (0x00000100u)
#define CSL_EMIF16_IODFTGBLCTRL_MMS_SHIFT (0x00000008u)
#define CSL_EMIF16_IODFTGBLCTRL_MMS_RESETVAL (0x00000000u)
/*----MMS Tokens----*/
#define CSL_EMIF16_IODFTGBLCTRL_MMS_OUTPUTREG (0x00000000u)
#define CSL_EMIF16_IODFTGBLCTRL_MMS_INPUTCAP (0x00000001u)

#define CSL_EMIF16_IODFTGBLCTRL_ESEL_MASK (0x00000080u)
#define CSL_EMIF16_IODFTGBLCTRL_ESEL_SHIFT (0x00000007u)
#define CSL_EMIF16_IODFTGBLCTRL_ESEL_RESETVAL (0x00000001u)
/*----ESEL Tokens----*/
#define CSL_EMIF16_IODFTGBLCTRL_ESEL_TESTMODE (0x00000000u)
#define CSL_EMIF16_IODFTGBLCTRL_ESEL_NORMALMODE (0x00000001u)

#define CSL_EMIF16_IODFTGBLCTRL_TOEN_MASK (0x00000040u)
#define CSL_EMIF16_IODFTGBLCTRL_TOEN_SHIFT (0x00000006u)
#define CSL_EMIF16_IODFTGBLCTRL_TOEN_RESETVAL (0x00000000u)
/*----TOEN Tokens----*/
#define CSL_EMIF16_IODFTGBLCTRL_TOEN_ENABLE (0x00000000u)
#define CSL_EMIF16_IODFTGBLCTRL_TOEN_DISABLE (0x00000001u)

#define CSL_EMIF16_IODFTGBLCTRL_MC_MASK (0x00000030u)
#define CSL_EMIF16_IODFTGBLCTRL_MC_SHIFT (0x00000004u)
#define CSL_EMIF16_IODFTGBLCTRL_MC_RESETVAL (0x00000001u)
/*----MC Tokens----*/
#define CSL_EMIF16_IODFTGBLCTRL_MC_DNLWD (0x00000000u)
#define CSL_EMIF16_IODFTGBLCTRL_MC_HOLD (0x00000001u)
#define CSL_EMIF16_IODFTGBLCTRL_MC_LWDINIT (0x00000002u)
#define CSL_EMIF16_IODFTGBLCTRL_MC_MISRENCAP (0x00000003u)

#define CSL_EMIF16_IODFTGBLCTRL_PC_MASK (0x0000000Eu)
#define CSL_EMIF16_IODFTGBLCTRL_PC_SHIFT (0x00000001u)
#define CSL_EMIF16_IODFTGBLCTRL_PC_RESETVAL (0x00000000u)

#define CSL_EMIF16_IODFTGBLCTRL_TM_MASK (0x00000001u)
#define CSL_EMIF16_IODFTGBLCTRL_TM_SHIFT (0x00000000u)
#define CSL_EMIF16_IODFTGBLCTRL_TM_RESETVAL (0x00000001u)

#define CSL_EMIF16_IODFTGBLCTRL_RESETVAL (0x00000091u)

/* IODFTTLAMISR */

#define CSL_EMIF16_IODFTTLAMISR_ADDR_TLMR_MASK (0xFFFFFFFu)
#define CSL_EMIF16_IODFTTLAMISR_ADDR_TLMR_RESETVAL (0x0000000u)

#define CSL_EMIF16_IODFTMISRLSB_RESETVAL (0x00000000u)

/* IODFTTLDMISR */

#define CSL_EMIF16_IODFTTLDMISR_TLMR_31_0_MASK (0xFFFFFFFFu)
#define CSL_EMIF16_IODFTTLDMISR_TLMR_31_0_SHIFT (0x00000000u)
#define CSL_EMIF16_IODFTTLDMISR_TLMR_31_0_RESETVAL (0x00000000u)

#define CSL_EMIF16_IODFTTLDMISR_RESETVAL (0x00000000u)

/* IODFTTLDCMISR */


#define CSL_EMIF16_IODFTTLDCMISR_CTL_TLMR_MASK (0x3FFF0000u)
#define CSL_EMIF16_IODFTTLDCMISR_CTL_TLMR_RESETVAL (0x0000u)

#define CSL_EMIF16_IODFTTLDCMISR_DQM_TLMR_MASK (0x00003F00u)
#define CSL_EMIF16_IODFTTLDCMISR_DQM_TLMR_RESETVAL (0x00u)

#define CSL_EMIF16_IODFTTLDCMISR_TLMR_34_32_MASK (0x00000003u)
#define CSL_EMIF16_IODFTTLDCMISR_TLMR_34_32_RESETVAL (0x0u)

#define CSL_EMIF16_IODFTTLDCMISR_RESETVAL (0x00000000u)

/* MODRELNUM */


#define CSL_EMIF16_MODRELNUM_RELEASE_NUM_MASK (0x000000FFu)
#define CSL_EMIF16_MODRELNUM_RELEASE_NUM_SHIFT (0x00000000u)
#define CSL_EMIF16_MODRELNUM_RELEASE_NUM_RESETVAL (0x00000000u)

#define CSL_EMIF16_MODRELNUM_RESETVAL (0x00000000u)

/* NANDF4BECCLR */


#define CSL_EMIF16_NANDF4BECCLR_4BIT_ECC_LOAD_MASK (0x000003FFu)
#define CSL_EMIF16_NANDF4BECCLR_4BIT_ECC_LOAD_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDF4BECCLR_4BIT_ECC_LOAD_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDF4BECCLR_RESETVAL (0x00000000u)

/* NANDF4BECC1R */


#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL2_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL2_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL2_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL1_MASK (0x000003FFu)
#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL1_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDF4BECC1R_4BIT_ECC_VAL1_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDF4BECC1R_RESETVAL (0x00000000u)

/* NANDF4BECC2R */


#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL4_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL4_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL4_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL3_MASK (0x000003FFu)
#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL3_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDF4BECC2R_4BIT_ECC_VAL3_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDF4BECC2R_RESETVAL (0x00000000u)

/* NANDF4BECC3R */


#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL6_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL6_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL6_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL5_MASK (0x000003FFu)
#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL5_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDF4BECC3R_4BIT_ECC_VAL5_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDF4BECC3R_RESETVAL (0x00000000u)

/* NANDF4BECC4R */


#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL8_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL8_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL8_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL7_MASK (0x000003FFu)
#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL7_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDF4BECC4R_4BIT_ECC_VAL7_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDF4BECC4R_RESETVAL (0x00000000u)

/* NANDFEA1R */


#define CSL_EMIF16_NANDFEA1R_ERR_ADDR2_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDFEA1R_ERR_ADDR2_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDFEA1R_ERR_ADDR2_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDFEA1R_ERR_ADDR1_MASK (0x000003FFu)
#define CSL_EMIF16_NANDFEA1R_ERR_ADDR1_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFEA1R_ERR_ADDR1_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDFEA1R_RESETVAL (0x00000000u)

/* NANDFEA2R */


#define CSL_EMIF16_NANDFEA2R_ERR_ADDR4_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDFEA2R_ERR_ADDR4_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDFEA2R_ERR_ADDR4_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDFEA2R_ERR_ADDR3_MASK (0x000003FFu)
#define CSL_EMIF16_NANDFEA2R_ERR_ADDR3_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFEA2R_ERR_ADDR3_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDFEA2R_RESETVAL (0x00000000u)

/* NANDFEV1R */


#define CSL_EMIF16_NANDFEV1R_ERR_VALUE2_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDFEV1R_ERR_VALUE2_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDFEV1R_ERR_VALUE2_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDFEV1R_ERR_VALUE1_MASK (0x000003FFu)
#define CSL_EMIF16_NANDFEV1R_ERR_VALUE1_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFEV1R_ERR_VALUE1_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDFEV1R_RESETVAL (0x00000000u)

/* NANDFEV2R */


#define CSL_EMIF16_NANDFEV2R_ERR_ADDR4_MASK (0x03FF0000u)
#define CSL_EMIF16_NANDFEV2R_ERR_ADDR4_SHIFT (0x00000010u)
#define CSL_EMIF16_NANDFEV2R_ERR_ADDR4_RESETVAL (0x00000000u)


#define CSL_EMIF16_NANDFEV2R_ERR_ADDR3_MASK (0x000003FFu)
#define CSL_EMIF16_NANDFEV2R_ERR_ADDR3_SHIFT (0x00000000u)
#define CSL_EMIF16_NANDFEV2R_ERR_ADDR3_RESETVAL (0x00000000u)

#define CSL_EMIF16_NANDFEV2R_RESETVAL (0x00000000u)

#endif
