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Data Structures |
| struct | CSL_Aif2SdLinkSetup |
| | This is a sub-structure in CSL_AifCommonLinkSetup. This structure is used for configuring the parameters for Serdes params specific to a link. More...
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| struct | CSL_Aif2CommonLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of common link index specifies which all link modules are using. More...
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| struct | CSL_Aif2CpriTmSetup |
| | This is a sub-structure in CSL_Aif2TmLinkSetup. This structure is used for configuring the parameters of the CPRI params relating to TM. More...
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| struct | CSL_Aif2TmLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of the TM. More...
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| struct | CSL_Aif2RmLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of RM link. More...
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| struct | CSL_Aif2RtLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of Retransmitter. More...
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| struct | CSL_Aif2DualBitMap |
| | This is a sub-structure in CSL_Aif2Pd(Pe)LinkSetup. This structure is used for configuring the parameters of Pd and Pe dual bit map. More...
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| struct | CSL_Aif2PdTypeLut |
| | This is a sub-structure in CSL_Aif2PdLinkSetup. This structure is used for configuring the parameters of 32 Pd type LUT. More...
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| struct | CSL_Aif2PdLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of protocol decoder. More...
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| struct | CSL_Aif2PeLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the link parameters of protocol encoder. More...
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| struct | CSL_Aif2AtLinkSetup |
| | This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of aif2 timer module. More...
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| struct | CSL_Aif2SdCommonSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of a SD module, the link index specifies which SD module is used links 0-3 use SD module 0, links 4-5 use SD module 1. More...
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| struct | CSL_Aif2PdRoute |
| | This is a sub-structure in CSL_Aif2PdCommonSetup. This structure is used for configuring the routing parameters of protocol decoder. More...
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| struct | CSL_Aif2PdChConfig |
| | This is a sub-structure in CSL_Aif2PdCommonSetup. This structure is used for configuring Pd 128 Dma channel configuration. More...
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| struct | CSL_Aif2PdChConfig1 |
| | This is a sub-structure in CSL_Aif2PdCommonSetup. This structure is used for configuring Pd 128 Dma channel configuration 1 register. More...
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| struct | CSL_Aif2FrameCounter |
| | This is a sub-structure in CSL_Aif2Pd(Pe)CommonSetup. This structure is used for configuring the parameters of PD, PE frame counter. More...
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| struct | CSL_Aif2PdCommonSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of protocol decoder which are common to all links. More...
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| struct | CSL_Aif2ModuloTc |
| | This is a sub-structure in CSL_Aif2Pd(Pe)CommonSetup. This structure is used for configuring the parameters of Modulo Terminal count. More...
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| struct | CSL_Aif2PeDmaCh0 |
| | This is a sub-structure in CSL_Aif2PeCommonSetup. This structure is used for PE DMA channel configuration 0 register. More...
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| struct | CSL_Aif2PeInFifoControl |
| | This is a sub-structure in CSL_Aif2PeCommonSetup. This structure is used for PE input fifo control register. More...
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| struct | CSL_Aif2PeCommonSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of protocol encoder which are common to all links. More...
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| struct | CSL_Aif2DbChannel |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of ingress Data Buffer. More...
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| struct | CSL_Aif2IngrDbSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of ingress Data Buffer. More...
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| struct | CSL_Aif2EgrDbSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of Egress data buffer. More...
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| struct | CSL_Aif2AdCommonSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the common parameters of aif2 Dma module. More...
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| struct | CSL_Aif2AdDioEngine |
| | This is a sub-structure in CSL_Aif2AdDioSetup. This structure is used for configuring the parameters of aif2 dma engine. More...
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| struct | CSL_Aif2AdDioSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of aif2 dma module especially for DIO mode. More...
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| struct | CSL_Aif2AtCountObj |
| struct | CSL_Aif2AtInitObj |
| struct | CSL_Aif2AtTcObj |
| struct | CSL_Aif2AtGsmTCount |
| | This object contains the aif2 GSM Tcount information. More...
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| struct | CSL_Aif2AtCommonSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the common parameters of aif2 timer module. More...
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| struct | CSL_Aif2AtEvent |
| | This is a sub-structure in CSL_Aif2AtEventSetup. This structure is used for configuring the parameters of aif2 at event for external Rad events and Internal events for dio. More...
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| struct | CSL_Aif2AtEventSetup |
| | This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of aif2 dma module especially for external Rad events and Internal events for dio. More...
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| struct | CSL_Aif2GlobalSetup |
| | This is a sub-structure in CSL_Aif2HwSetup. This structure is used for configuring the parameters global to AIF2. More...
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| struct | CSL_Aif2CommonSetup |
| | This is a sub-structure in CSL_Aif2HwSetup. This structure is used for configuring the parameters of a link. More...
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| struct | CSL_Aif2LinkSetup |
| | This is a sub-structure in CSL_Aif2HwSetup. This structure is used for configuring the parameters of an outbound link. More...
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| struct | CSL_Aif2Obj |
| | This object contains the reference to the instance of AIF2 opened using the CSL_aif2Open(). More...
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| struct | CSL_Aif2BaseAddress |
| | This will have the base-address information for the peripheral instance. More...
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| struct | CSL_Aif2Param |
| | Module specific parameters. More...
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| struct | CSL_Aif2Setup |
| | This is the Setup structure for configuring AIF2 using CSL_aif2HwSetup() function. More...
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| struct | CSL_Aif2PeDbmr |
| | This structure is used for DBMR dynamic configuring parameters of protocol encoder. More...
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| struct | CSL_Aif2PeObsaiHeader |
| | This structure is used for dynamic configuring the obsai header parameters of protocol encoder. More...
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| struct | CSL_Aif2PeModuloRule |
| | This structure is used for dynamic configuring the Modulo rule parameters of protocol encoder. More...
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| struct | CSL_Aif2PeChannelConfig |
| | This structure is used for dynamic configuring the channel parameters of protocol encoder. More...
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| struct | CSL_Aif2PeChRuleLut |
| | This structure is used for dynamic configuring the channel parameters of protocol encoder. More...
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| struct | CSL_Aif2PdCpriIdLut |
| | This structure is used for dynamic configuring the cpri Id LUT parameters of protocol decoder. More...
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| struct | CSL_Aif2CpriCwLut |
| | This structure is used for dynamic configuring the cpri 256 control word LUT parameters of protocol decoder. More...
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| struct | CSL_Aif2PdChannelConfig |
| | This structure is used for dynamic configuring the channel parameters of protocol decoder. More...
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| struct | CSL_Aif2DbSideData |
| | This object contains the aif2 DB side data information. More...
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| struct | CSL_Aif2VcEmu |
| | This object contains the aif2 Vc Emu control data information. More...
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| struct | CSL_Aif2EeAif2Int |
| | This object contains the aif2 EE Aif2 Error Interrupt data information. More...
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| struct | CSL_Aif2EeDbInt |
| | This object contains the aif2 EE DB Interrupt data information. More...
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| struct | CSL_Aif2EeAdInt |
| | This object contains the aif2 EE AD Interrupt data information. More...
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| struct | CSL_Aif2EeCdInt |
| | This object contains the aif2 EE CD(PKTDMA module) Interrupt data information. More...
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| struct | CSL_Aif2EeSdInt |
| | This object contains the aif2 EE SD Interrupt data information. More...
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| struct | CSL_Aif2EeVcInt |
| | This object contains the aif2 EE VC Interrupt data information. More...
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| struct | CSL_Aif2EeAif2Run |
| | This object contains the EE aif2 run control data information. More...
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| struct | CSL_Aif2EeLinkAInt |
| | This object contains the aif2 EE Link A Interrupt data information. More...
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| struct | CSL_Aif2EeLinkBInt |
| | This object contains the aif2 EE Link B Interrupt data information. More...
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| struct | CSL_Aif2EeAtInt |
| | This object contains the aif2 EE AT Interrupt data information. More...
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| struct | CSL_Aif2EePdInt |
| | This object contains the aif2 EE PD Interrupt data information. More...
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| struct | CSL_Aif2EePeInt |
| | This object contains the aif2 EE PE Interrupt data information. More...
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| struct | CSL_Aif2PidStatus |
| | This object contains the aif2 PID information. More...
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| struct | CSL_Aif2SdRxStatus |
| | This object contains the aif2 SERDES Rx link status information. More...
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| struct | CSL_Aif2SdTxStatus |
| | This object contains the aif2 SERDES Tx link status information. More...
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| struct | CSL_Aif2RmStatus0 |
| | This object contains the aif2 Rm link status0 information. More...
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| struct | CSL_Aif2RmStatus1 |
| | This object contains the aif2 Rm link status1 information. More...
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| struct | CSL_Aif2RmStatus2 |
| | This object contains the aif2 Rm link status2 information. More...
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| struct | CSL_Aif2RmStatus3 |
| | This object contains the aif2 Rm link status3 information. More...
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| struct | CSL_Aif2RmStatus4 |
| | This object contains the aif2 Rm link status4 information. More...
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| struct | CSL_Aif2TmStatus |
| | This object contains the aif2 Tm link status information. More...
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| struct | CSL_Aif2RtHeaderStatus |
| | This object contains the aif2 Rt header error status information. More...
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| struct | CSL_Aif2RtStatus |
| | This object contains the aif2 Rt link status information. More...
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| struct | CSL_Aif2AtCaptRadt |
| | This object contains the aif2 radt capture value information. More...
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| struct | CSL_Aif2AtWcdmaCount |
| | This object contains the aif2 wcdma count value information. More...
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| struct | CSL_Aif2EeOrigin |
| | This object contains the aif2 EE error and alarm origination information. More...
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Typedefs |
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typedef volatile CSL_Aif2Regs * | CSL_Aif2RegsOvly |
| | pointer to the csl aif2 register global structure
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typedef CSL_Aif2Obj * | CSL_Aif2Handle |
| | handle pointer to aif2 object
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typedef void * | CSL_Aif2Context |
| | Aif2 context info is a pointer.
|
Enumerations |
| enum | CSL_Aif2FrameMode { CSL_AIF2_FRAME_MODE_NORMAL = 0,
CSL_AIF2_FRAME_MODE_SHORT
} |
| | Frame model supported. More...
|
| enum | CSL_Aif2LinkProtocol { CSL_AIF2_LINK_PROTOCOL_CPRI = 0,
CSL_AIF2_LINK_PROTOCOL_OBSAI
} |
| | Link Protocol supported. More...
|
| enum | CSL_Aif2DataWidth { CSL_AIF2_DATA_WIDTH_7_BIT = 0,
CSL_AIF2_DATA_WIDTH_8_BIT,
CSL_AIF2_DATA_WIDTH_15_BIT,
CSL_AIF2_DATA_WIDTH_16_BIT
} |
| | data width format supported More...
|
| enum | CSL_Aif2LinkIndex {
CSL_AIF2_LINK_0 = 0,
CSL_AIF2_LINK_1,
CSL_AIF2_LINK_2,
CSL_AIF2_LINK_3,
CSL_AIF2_LINK_4,
CSL_AIF2_LINK_5,
CSL_AIF2_NO_LINK = 0xF
} |
| | aif2 link indices supported More...
|
| enum | CSL_Aif2LinkRate { CSL_AIF2_LINK_RATE_8x = 0,
CSL_AIF2_LINK_RATE_4x,
CSL_AIF2_LINK_RATE_2x,
CSL_AIF2_LINK_RATE_5x
} |
| | link rates supported More...
|
| enum | CSL_Aif2TmSyncState { CSL_AIF2_TM_ST_OFF = 0x1,
CSL_AIF2_TM_ST_IDLE = 0x2,
CSL_AIF2_TM_ST_RE_SYNC = 0x4,
CSL_AIF2_TM_ST_FRAME_SYNC = 0x8
} |
| | TM states. More...
|
| enum | CSL_Aif2RmFifoThold { CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY = 0,
CSL_AIF2_RM_FIFO_THOLD_4DUAL,
CSL_AIF2_RM_FIFO_THOLD_8DUAL,
CSL_AIF2_RM_FIFO_THOLD_16DUAL
} |
| | setup Rm fifo threshold word size for reading received data More...
|
| enum | CSL_Aif2RmErrorSuppress { CSL_AIF2_RM_ERROR_ALLOW = 0,
CSL_AIF2_RM_ERROR_SUPPRESS
} |
| | Suppress error reporting when the receiver state machine is not in state ST3. More...
|
| enum | CSL_Aif2RmSyncState {
CSL_AIF2_RM_ST_0 = 8,
CSL_AIF2_RM_ST_1 = 4,
CSL_AIF2_RM_ST_2 = 2,
CSL_AIF2_RM_ST_3 = 1,
CSL_AIF2_RM_ST_4 = 16,
CSL_AIF2_RM_ST_5 = 32
} |
| | RM sync states. More...
|
| enum | CSL_Aif2LinkDataType { CSL_AIF2_LINK_DATA_TYPE_NORMAL = 0,
CSL_AIF2_LINK_DATA_TYPE_RSA
} |
| | Link data type supported. More...
|
| enum | CSL_Aif2GSMDataFormat { CSL_AIF2_GSM_DATA_OTHER = 0,
CSL_AIF2_GSM_DATA_UL
} |
| | GSM data type supported. More...
|
| enum | CSL_Aif2RtConfig { CSL_AIF2_RT_MODE_RETRANSMIT,
CSL_AIF2_RT_MODE_AGGREGATE,
CSL_AIF2_RT_MODE_TRANSMIT
} |
| | Retransmitter Mode used. More...
|
| enum | CSL_Aif2SdRxTerm { CSL_AIF2_SD_RX_TERM_COMMON_POINT_VDDT = 0,
CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 = 1,
CSL_AIF2_SD_RX_TERM_COMMON_POINT_FLOATING = 3
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdRxEqConfig { CSL_AIF2_SD_RX_EQ_MAXIMUM = 0,
CSL_AIF2_SD_RX_EQ_ADAPTIVE,
CSL_AIF2_SD_RX_EQ_PRECURSOR,
CSL_AIF2_SD_RX_EQ_POSTCURSOR
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdRxInvertPolarity { CSL_AIF2_SD_RX_NORMAL_POLARITY = 0,
CSL_AIF2_SD_RX_INVERTED_POLARITY
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdRxAlign { CSL_AIF2_SD_RX_ALIGNMENT_DISABLE = 0,
CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE,
CSL_AIF2_SD_RX_ALIGNMENT_JOG
} |
| | Sd module rx alignment. More...
|
| enum | CSL_Aif2SdRxLos { CSL_AIF2_SD_RX_LOS_DISABLE = 0,
CSL_AIF2_SD_RX_LOS_ENABLE = 4
} |
| | Sd module rx LOS. More...
|
| enum | CSL_Aif2SdRxCdrAlg { CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1 = 0,
CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_17 = 1,
CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_1 = 4,
CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_17 = 5
} |
| | Sd clock recovery algorithm. More...
|
| enum | CSL_Aif2SdTxOutputSwing {
CSL_AIF2_SD_TX_OUTPUT_SWING_0 = 0,
CSL_AIF2_SD_TX_OUTPUT_SWING_1,
CSL_AIF2_SD_TX_OUTPUT_SWING_2,
CSL_AIF2_SD_TX_OUTPUT_SWING_3,
CSL_AIF2_SD_TX_OUTPUT_SWING_4,
CSL_AIF2_SD_TX_OUTPUT_SWING_5,
CSL_AIF2_SD_TX_OUTPUT_SWING_6,
CSL_AIF2_SD_TX_OUTPUT_SWING_7,
CSL_AIF2_SD_TX_OUTPUT_SWING_8,
CSL_AIF2_SD_TX_OUTPUT_SWING_9,
CSL_AIF2_SD_TX_OUTPUT_SWING_10,
CSL_AIF2_SD_TX_OUTPUT_SWING_11,
CSL_AIF2_SD_TX_OUTPUT_SWING_12,
CSL_AIF2_SD_TX_OUTPUT_SWING_13,
CSL_AIF2_SD_TX_OUTPUT_SWING_14,
CSL_AIF2_SD_TX_OUTPUT_SWING_15
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdTxInvertPolarity { CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY = 0,
CSL_AIF2_SD_TX_PAIR_INVERTED_POLARITY
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdTxPostcursorTabWeight {
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_0 = 0,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_1,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_2,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_3,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_4,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_5,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_6,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_7,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_8,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_9,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_10,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_11,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_12,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_13,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_14,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_15,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_16,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_17,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_18,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_19,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_20,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_21,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_22,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_23,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_25,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_26,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_27,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_28,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_29,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_30,
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_31
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdTxPrecursorTabWeight {
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_0 = 0,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_1,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_3,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_4,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_5,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_6,
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_7
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdTestPattern {
CSL_AIF2_SD_TEST_DISABLED = 0,
CSL_AIF2_SD_ALTERNATING_0_1,
CSL_AIF2_SD_PRBS_7BIT_LFSR,
CSL_AIF2_SD_PRBS_23BIT_LFSR,
CSL_AIF2_SD_PRBS_31BIT_LFSR
} |
| | Sd link test pattern index. More...
|
| enum | CSL_Aif2PllMpyFactor {
CSL_AIF2_PLL_MUL_FACTOR_4X = 16,
CSL_AIF2_PLL_MUL_FACTOR_5X = 20,
CSL_AIF2_PLL_MUL_FACTOR_6X = 24,
CSL_AIF2_PLL_MUL_FACTOR_8X = 32,
CSL_AIF2_PLL_MUL_FACTOR_8_25X = 33,
CSL_AIF2_PLL_MUL_FACTOR_10X = 40,
CSL_AIF2_PLL_MUL_FACTOR_12X = 48,
CSL_AIF2_PLL_MUL_FACTOR_12_5X = 50,
CSL_AIF2_PLL_MUL_FACTOR_15X = 60,
CSL_AIF2_PLL_MUL_FACTOR_16X = 64,
CSL_AIF2_PLL_MUL_FACTOR_16_5X = 66,
CSL_AIF2_PLL_MUL_FACTOR_20X = 80,
CSL_AIF2_PLL_MUL_FACTOR_22X = 88,
CSL_AIF2_PLL_MUL_FACTOR_25X = 100
} |
| | Sd module index. More...
|
| enum | CSL_Aif2SdVoltRange { CSL_AIF2_PLL_VOLTAGE_LOW = 0,
CSL_AIF2_PLL_VOLTAGE_HIGH
} |
| | Sd pll voltage range. More...
|
| enum | CSL_Aif2SdSleepPll { CSL_AIF2_PLL_AWAKE = 0,
CSL_AIF2_PLL_SLEEP
} |
| | Sd pll sleep. More...
|
| enum | CSL_Aif2SdLoopBandwidth { CSL_AIF2_PLL_LOOP_BAND_MID = 0,
CSL_AIF2_PLL_LOOP_BAND_UHIGH,
CSL_AIF2_PLL_LOOP_BAND_LOW,
CSL_AIF2_PLL_LOOP_BAND_HIGH
} |
| | Sd pll loop bandwidth selection. More...
|
| enum | CSL_Aif2SdClockBypass |
| | Sd pll clock bypass selection. More...
|
| enum | CSL_Aif2SdClockSelect |
| | Sd sys clock select from either B8 or B4.
|
| enum | CSL_Aif2CpriCwPktDelim { CSL_AIF2_CW_DELIM_NO_CW = 0,
CSL_AIF2_CW_DELIM_4B5B,
CSL_AIF2_CW_DELIM_NULLDELM,
CSL_AIF2_CW_DELIM_HYP_FRM
} |
| | CRPI Control Word 4B/5B encoding enable. More...
|
| enum | CSL_Aif2PdDataMode { CSL_AIF2_PD_DATA_AXC = 0,
CSL_AIF2_PD_DATA_PKT
} |
| | dicates the payload is to be used as AxC (normal) or Packet traffic More...
|
| enum | CSL_Aif2CppiDio { CSL_AIF2_CPPI = 0,
CSL_AIF2_DIO
} |
| | select mode between CPPI and DIO More...
|
| enum | CSL_Aif2PdWatchDogReport { CSL_AIF2_PD_WD_REPORT_ALL = 0,
CSL_AIF2_PD_WD_REPORT_EOP
} |
| | Report every missed WDog fail, or report only fails of missing EOP. More...
|
| enum | CSL_Aif2ObsaiTsMask { CSL_AIF2_TSTAMP_MASK_FULL_GEN = 0,
CSL_AIF2_TSTAMP_MASK_4INS_2GEN,
CSL_AIF2_TSTAMP_MASK_FULL_INS
} |
| | PD or PE Obsai time stamp mask supported. More...
|
| enum | CSL_Aif2TstampFormat {
CSL_AIF2_TSTAMP_FORMAT_NO_TS = 0,
CSL_AIF2_TSTAMP_FORMAT_NORM_TS,
CSL_AIF2_TSTAMP_FORMAT_GSM,
CSL_AIF2_TSTAMP_FORMAT_GEN_PKT,
CSL_AIF2_TSTAMP_FORMAT_ETHERNET,
CSL_AIF2_TSTAMP_FORMAT_ROUTE_CHECK,
CSL_AIF2_TSTAMP_FORMAT_GSM_DL
} |
| | PD or PE time stamp format supported. More...
|
| enum | CSL_Aif2RouteMask { CSL_AIF2_ROUTE_MASK_NONE = 0,
CSL_AIF2_ROUTE_MASK_4LSB,
CSL_AIF2_ROUTE_MASK_ALL,
CSL_AIF2_ROUTE_MASK_RESERVED
} |
| | controls how many OBSAI time stamp bits to use in the reception routing. More...
|
| enum | CSL_Aif2CpriAxCPack { CSL_AIF2_CPRI_7BIT_SAMPLE = 0,
CSL_AIF2_CPRI_8BIT_SAMPLE,
CSL_AIF2_CPRI_15BIT_SAMPLE,
CSL_AIF2_CPRI_16BIT_SAMPLE
} |
| | select CPRI AxC data pack type More...
|
| enum | CSL_Aif2PeRtContol { CSL_AIF2_PE_RT_RETRANS = 0,
CSL_AIF2_PE_RT_INSERT,
CSL_AIF2_PE_RT_ADD8,
CSL_AIF2_PE_RT_ADD16
} |
| | Controls RT to perform appropriate insterion/aggregation into PHY. More...
|
| enum | CSL_Aif2CrcLen { CSL_AIF2_CRC_32BIT = 0,
CSL_AIF2_CRC_16BIT,
CSL_AIF2_CRC_8BIT
} |
| | CRC: length of CRC. More...
|
| enum | CSL_Aif2DbFifoDepth {
CSL_AIF2_DB_FIFO_DEPTH_QW8 = 0,
CSL_AIF2_DB_FIFO_DEPTH_QW16,
CSL_AIF2_DB_FIFO_DEPTH_QW32,
CSL_AIF2_DB_FIFO_DEPTH_QW64,
CSL_AIF2_DB_FIFO_DEPTH_QW128,
CSL_AIF2_DB_FIFO_DEPTH_QW256
} |
| | DB FIFO bufffer depth. More...
|
| enum | CSL_Aif2DbDataSwap { CSL_AIF2_DB_NO_SWAP = 0,
CSL_AIF2_DB_BYTE_SWAP,
CSL_AIF2_DB_HALF_WORD_SWAP,
CSL_AIF2_DB_WORD_SWAP
} |
| | DB Big endian swapping control. More...
|
| enum | CSL_Aif2DbIqOrder { CSL_AIF2_DB_IQ_NO_SWAP = 0,
CSL_AIF2_DB_IQ_NO_SWAP1,
CSL_AIF2_DB_IQ_BYTE_SWAP,
CSL_AIF2_DB_IQ_16BIT_SWAP
} |
| | Internally changing IQ data order control. More...
|
| enum | CSL_Aif2DioLen { CSL_AIF2_DB_DIO_LEN_128 = 0,
CSL_AIF2_DB_DIO_LEN_256
} |
| | DB DIO length type. More...
|
| enum | CSL_Aif2DbPmControl { CSL_AIF2_DB_PM_TOKEN_FIFO = 0,
CSL_AIF2_DB_AXC_TOKEN_FIFO
} |
| | DB Packet mode control type. More...
|
| enum | CSL_Aif2AdFailMode { CSL_AIF2_AD_DROP = 0,
CSL_AIF2_AD_MARK
} |
| | This field tells how the Ingress Scheduler handles packets marked as failed by the PD. More...
|
| enum | CSL_Aif2AdIngrPriority { CSL_AIF2_AD_DIO_PRI = 0,
CSL_AIF2_AD_PKT_PRI
} |
| | AD Ingress Scheduler aribitration priority. More...
|
| enum | CSL_Aif2AdEgrPriority { CSL_AIF2_AD_AXC_PRI = 0,
CSL_AIF2_AD_NON_AXC_PRI
} |
| | AD Egress Scheduler aribitration priority. More...
|
| enum | CSL_Aif2AdNumQWord { CSL_AIF2_AD_1QUAD = 0,
CSL_AIF2_AD_2QUAD,
CSL_AIF2_AD_4QUAD
} |
| | AD DIO Quad word number for each AxC data. More...
|
| enum | CSL_Aif2AdBcnTable |
| | AD DIO BCN TABLE SEL type. More...
|
| enum | CSL_Aif2DioEngineIndex { CSL_AIF2_DIO_ENGINE_0 = 0,
CSL_AIF2_DIO_ENGINE_1,
CSL_AIF2_DIO_ENGINE_2
} |
| | aif2 dio engine index supported More...
|
| enum | CSL_Aif2AtEvtStrobe {
CSL_AIF2_RADT_SYMBOL = 0,
CSL_AIF2_RADT_FRAME,
CSL_AIF2_ULRADT_SYMBOL,
CSL_AIF2_ULRADT_FRAME,
CSL_AIF2_DLRADT_SYMBOL,
CSL_AIF2_DLRADT_FRAME,
CSL_AIF2_PHYT_FRAME
} |
| | AT Rad event strobe selection type. More...
|
| enum | CSL_Aif2AtEventIndex {
CSL_AIF2_EVENT_0 = 0,
CSL_AIF2_EVENT_1,
CSL_AIF2_EVENT_2,
CSL_AIF2_EVENT_3,
CSL_AIF2_EVENT_4,
CSL_AIF2_EVENT_5,
CSL_AIF2_EVENT_6,
CSL_AIF2_EVENT_7,
CSL_AIF2_EVENT_8,
CSL_AIF2_EVENT_9,
CSL_AIF2_EVENT_10,
CSL_AIF2_IN_DIO_EVENT_0,
CSL_AIF2_IN_DIO_EVENT_1,
CSL_AIF2_IN_DIO_EVENT_2,
CSL_AIF2_E_DIO_EVENT_0,
CSL_AIF2_E_DIO_EVENT_1,
CSL_AIF2_E_DIO_EVENT_2
} |
| | AT Event selection type. More...
|
| enum | CSL_Aif2AtSyncSource {
CSL_AIF2_RP1_SYNC = 0,
CSL_AIF2_CHIP_INPUT_SYNC,
CSL_AIF2_SW_SYNC,
CSL_AIF2_RM_AT_SYNC,
CSL_AIF2_PHYT_CMP_SYNC
} |
| | Timer sync sources in AT. More...
|
| enum | CSL_Aif2AtSyncMode { CSL_AIF2_NON_RP1_MODE = 0,
CSL_AIF2_RP1_MODE
} |
| | Sync mode for AT. More...
|
| enum | CSL_Aif2AtReSyncMode { CSL_AIF2_NO_AUTO_RESYNC_MODE = 0,
CSL_AIF2_AUTO_RESYNC_MODE
} |
| | Re-Sync mode for AT. More...
|
| enum | CSL_Aif2AtCrcUse { CSL_AIF2_AT_CRC_DONT_USE = 0,
CSL_AIF2_AT_CRC_USE
} |
| | select CRC mode on / off More...
|
| enum | CSL_Aif2AtCrcFlip { CSL_AIF2_AT_CRC_NORMAL = 0,
CSL_AIF2_AT_CRC_REVERSE
} |
| | select CRC flip mode between normal and reverse More...
|
| enum | CSL_Aif2AtCrcInitOnes { CSL_AIF2_AT_CRC_INIT0 = 0,
CSL_AIF2_AT_CRC_INIT1
} |
| | select CRC init value More...
|
| enum | CSL_Aif2AtCrcInvert { CSL_AIF2_AT_CRC_NOINVERT = 0,
CSL_AIF2_AT_CRC_INVERT
} |
| | select CRC invert mode More...
|
| enum | CSL_Aif2AtRp1CRCUsage { CSL_AIF2_USE_SYNC_BURST_ON_CRC_FAIL = 0,
CSL_AIF2_DISCARD_SYNC_BURST_ON_CRC_FAIL
} |
| | CRC usage in RP1 sync mode for AT. More...
|
| enum | CSL_Aif2AtRp1TypeField {
CSL_AIF2_RP1_TYPE_NOT_USED = 0x00,
CSL_AIF2_RP1_TYPE_RP3_FRAME_NUM = 0x01,
CSL_AIF2_RP1_TYPE_WCDMA_FDD_FRAME_NUM = 0x02,
CSL_AIF2_RP1_TYPE_GSM_EDGE_1_FRAME_NUM = 0x03,
CSL_AIF2_RP1_TYPE_GSM_EDGE_2_FRAME_NUM = 0x04,
CSL_AIF2_RP1_TYPE_GSM_EDGE_3_FRAME_NUM = 0x05,
CSL_AIF2_RP1_TYPE_WCDMA_TDD_FRAME_NUM = 0x06,
CSL_AIF2_RP1_TYPE_CDMA_2000_FRAME_NUM = 0x07,
CSL_AIF2_RP1_TYPE_TOD = 0x08,
CSL_AIF2_RP1_TYPE_RESERVED_FIRST = 0x09,
CSL_AIF2_RP1_TYPE_RESERVED_LAST = 0x7F,
CSL_AIF2_RP1_TYPE_SPARE_FIRST = 0x80,
CSL_AIF2_RP1_TYPE_SPARE_LAST = 0xFF
} |
| | Type field definitions for RP1 sync burst. More...
|
| enum | CSL_Aif2EeArgIndex {
CSL_AIF2_EE_INT_RAW_STATUS = 0,
CSL_AIF2_EE_INT_SET,
CSL_AIF2_EE_INT_CLR,
CSL_AIF2_EE_INT_EN_STATUS_EV0,
CSL_AIF2_EE_INT_EN_STATUS_EV1,
CSL_AIF2_EE_INT_EN_EV0,
CSL_AIF2_EE_INT_EN_EV1,
CSL_AIF2_EE_INT_EN_SET_EV0,
CSL_AIF2_EE_INT_EN_SET_EV1,
CSL_AIF2_EE_INT_EN_CLR_EV0,
CSL_AIF2_EE_INT_EN_CLR_EV1
} |
| | select EE module working function More...
|
| enum | CSL_Aif2HwControlCmd {
CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK = 0,
CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK,
CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK,
CSL_AIF2_CMD_ENABLE_DISABLE_SD_B8_PLL,
CSL_AIF2_CMD_ENABLE_DISABLE_SD_B4_PLL,
CSL_AIF2_CMD_VC_EMU_CONTROL,
CSL_AIF2_CMD_SD_LINK_TX_TEST_PATTERN,
CSL_AIF2_CMD_SD_LINK_RX_TEST_PATTERN,
CSL_AIF2_CMD_RM_FORCE_STATE,
CSL_AIF2_CMD_TM_L1_INBAND_SET,
CSL_AIF2_CMD_TM_FLUSH_FIFO,
CSL_AIF2_CMD_TM_IDLE,
CSL_AIF2_CMD_TM_RESYNC,
CSL_AIF2_CMD_PD_CPRI_ID_LUT_SETUP,
CSL_AIF2_CMD_PD_CPRI_CW_LUT_SETUP,
CSL_AIF2_CMD_PD_LINK_DBMR_SETUP,
CSL_AIF2_CMD_PD_CH_CONFIG_SETUP,
CSL_AIF2_CMD_PE_CPRI_CW_LUT_SETUP,
CSL_AIF2_CMD_PE_OBSAI_HEADER_SETUP,
CSL_AIF2_CMD_PE_LINK_DBMR_SETUP,
CSL_AIF2_CMD_PE_MODULO_RULE_SETUP,
CSL_AIF2_CMD_PE_CH_CONFIG_SETUP,
CSL_AIF2_CMD_PE_CH_RULE_LUT_SETUP,
CSL_AIF2_CMD_ENABLE_DISABLE_LINK_DATA_CAPTURE,
CSL_AIF2_CMD_ENABLE_DISABLE_DATA_TRACE_SYNC,
CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_DEBUG_MODE,
CSL_AIF2_CMD_DB_IN_DEBUG_DATA_SETUP,
CSL_AIF2_CMD_DB_IN_DEBUG_SIDE_DATA_SETUP,
CSL_AIF2_CMD_DB_IN_DEBUG_WRITE,
CSL_AIF2_CMD_DB_IN_DEBUG_OFFSET_ADDR,
CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_CHANNEL,
CSL_AIF2_CMD_DB_IN_CHANNEL_SETUP,
CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_DEBUG_MODE,
CSL_AIF2_CMD_DB_E_DEBUG_READ_CONTROL,
CSL_AIF2_CMD_DB_E_DEBUG_WRITE_TOKEN,
CSL_AIF2_CMD_DB_E_DEBUG_READ,
CSL_AIF2_CMD_DB_E_DEBUG_OFFSET_ADDR,
CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_CHANNEL,
CSL_AIF2_CMD_DB_E_CHANNEL_SETUP,
CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL,
CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL,
CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_DIO_GLOBAL,
CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_DIO_GLOBAL,
CSL_AIF2_CMD_AD_IN_DIO_TABLE_SELECT,
CSL_AIF2_CMD_AD_IN_DIO_NUM_AXC_CHANGE,
CSL_AIF2_CMD_AD_IN_DIO_BCN_TABLE_CHANGE,
CSL_AIF2_CMD_AD_E_DIO_TABLE_SELECT,
CSL_AIF2_CMD_AD_E_DIO_NUM_AXC_CHANGE,
CSL_AIF2_CMD_AD_E_DIO_BCN_TABLE_CHANGE,
CSL_AIF2_CMD_AD_TRACE_DATA_DMA_CHANNEL_ON_OFF,
CSL_AIF2_CMD_AD_TRACE_DATA_BASE_ADDR,
CSL_AIF2_CMD_AD_TRACE_FRAMING_DATA_BASE_ADDR,
CSL_AIF2_CMD_AD_TRACE_CPPI_DMA_BURST_WRAP,
CSL_AIF2_CMD_AT_EVENT_SETUP,
CSL_AIF2_CMD_AT_DELTA_SETUP,
CSL_AIF2_CMD_AT_HALT_TIMER,
CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS,
CSL_AIF2_CMD_AT_ARM_TIMER,
CSL_AIF2_CMD_AT_DEBUG_SYNC,
CSL_AIF2_CMD_AT_RAD_WCDMA_DIV,
CSL_AIF2_CMD_AT_RAD_TC_SETUP,
CSL_AIF2_CMD_AT_GSM_TCOUNT_SETUP,
CSL_AIF2_CMD_AT_ENABLE_EVENT,
CSL_AIF2_CMD_AT_DISABLE_EVENT,
CSL_AIF2_CMD_AT_FORCE_EVENT,
CSL_AIF2_CMD_EE_EOI_SETUP,
CSL_AIF2_CMD_EE_AIF2_ERROR_INT,
CSL_AIF2_CMD_EE_DB_INT,
CSL_AIF2_CMD_EE_AD_INT,
CSL_AIF2_CMD_EE_CD_INT,
CSL_AIF2_CMD_EE_SD_INT,
CSL_AIF2_CMD_EE_VC_INT,
CSL_AIF2_CMD_EE_AIF2_RUN,
CSL_AIF2_CMD_EE_LINKA_INT,
CSL_AIF2_CMD_EE_LINKB_INT,
CSL_AIF2_CMD_EE_AT_INT,
CSL_AIF2_CMD_EE_PD_INT,
CSL_AIF2_CMD_EE_PE_INT
} |
| enum | CSL_Aif2HwStatusQuery {
CSL_AIF2_QUERY_VERSION = 0,
CSL_AIF2_QUERY_VC_STAT,
CSL_AIF2_QUERY_SD_RX_LINK_STATUS,
CSL_AIF2_QUERY_SD_TX_LINK_STATUS,
CSL_AIF2_QUERY_SD_B8_PLL_LOCK,
CSL_AIF2_QUERY_SD_B4_PLL_LOCK,
CSL_AIF2_QUERY_RM_LINK_STATUS_0,
CSL_AIF2_QUERY_RM_LINK_STATUS_1,
CSL_AIF2_QUERY_RM_LINK_STATUS_2,
CSL_AIF2_QUERY_RM_LINK_STATUS_3,
CSL_AIF2_QUERY_RM_LINK_STATUS_4,
CSL_AIF2_QUERY_TM_LINK_CPRI_HFN,
CSL_AIF2_QUERY_TM_LINK_STATUS,
CSL_AIF2_QUERY_RT_FIFO_DEPTH_STATUS,
CSL_AIF2_QUERY_RT_HEADER_ERROR_STATUS,
CSL_AIF2_QUERY_RT_LINK_STATUS,
CSL_AIF2_QUERY_PD_CHANNEL_STATUS,
CSL_AIF2_QUERY_PD_PACKET_STATUS,
CSL_AIF2_QUERY_PE_CHANNEL_STATUS,
CSL_AIF2_QUERY_PE_PACKET_STATUS,
CSL_AIF2_QUERY_DB_IN_DEBUG_OFFSET_DATA,
CSL_AIF2_QUERY_DB_E_DEBUG_DATA,
CSL_AIF2_QUERY_DB_E_DEBUG_SIDE_DATA,
CSL_AIF2_QUERY_DB_E_DEBUG_OFFSET_DATA,
CSL_AIF2_QUERY_DB_E_EOP_COUNT,
CSL_AIF2_QUERY_AD_I_EOP_COUNT,
CSL_AIF2_QUERY_AT_LINK_PI_CAPTURE,
CSL_AIF2_QUERY_AT_RADT_CAPTURE,
CSL_AIF2_QUERY_AT_RP1_TYPE_CAPTURE,
CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_LSB,
CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_MSB,
CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_LSB,
CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_MSB,
CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_LSB,
CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_MSB,
CSL_AIF2_QUERY_AT_PHY_CLOCK_COUNT,
CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_LSB,
CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_MSB,
CSL_AIF2_QUERY_AT_RAD_CLOCK_COUNT,
CSL_AIF2_QUERY_AT_RAD_SYMBOL_COUNT,
CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_LSB,
CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_MSB,
CSL_AIF2_QUERY_AT_ULRAD_CLOCK_COUNT,
CSL_AIF2_QUERY_AT_ULRAD_SYMBOL_COUNT,
CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_LSB,
CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_MSB,
CSL_AIF2_QUERY_AT_DLRAD_CLOCK_COUNT,
CSL_AIF2_QUERY_AT_DLRAD_SYMBOL_COUNT,
CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_LSB,
CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_MSB,
CSL_AIF2_QUERY_AT_RAD_WCDMA_VALUE,
CSL_AIF2_QUERY_AT_ULRAD_WCDMA_VALUE,
CSL_AIF2_QUERY_AT_DLRAD_WCDMA_VALUE,
CSL_AIF2_QUERY_AT_RAD_TSTAMP_CLOCK_COUNT,
CSL_AIF2_QUERY_AT_GSM_TCOUNT_VALUE,
CSL_AIF2_QUERY_EE_DB_INT_STATUS,
CSL_AIF2_QUERY_EE_AD_INT_STATUS,
CSL_AIF2_QUERY_EE_CD_INT_STATUS,
CSL_AIF2_QUERY_EE_SD_INT_STATUS,
CSL_AIF2_QUERY_EE_VC_INT_STATUS,
CSL_AIF2_QUERY_EE_AIF2_RUN_STATUS,
CSL_AIF2_QUERY_EE_AIF2_ORIGINATION,
CSL_AIF2_QUERY_EE_LINKA_INT_STATUS,
CSL_AIF2_QUERY_EE_LINKB_INT_STATUS,
CSL_AIF2_QUERY_EE_AT_INT_STATUS
} |
| enum | CSL_Aif2RmForceSyncState {
CSL_AIF2_RM_FORCE_ST0 = 4,
CSL_AIF2_RM_FORCE_ST1 = 5,
CSL_AIF2_RM_FORCE_ST2 = 6,
CSL_AIF2_RM_FORCE_ST3 = 7,
CSL_AIF2_RM_FORCE_ST4 = 2,
CSL_AIF2_RM_FORCE_ST5 = 3
} |
| | RM force sync states. More...
|
Functions |
|
| CSL_Status | CSL_aif2Init (CSL_Aif2Context *pContext) |
| | Peripheral specific initialization function.
|
| CSL_Aif2Handle | CSL_aif2Open (CSL_Aif2Obj *pAif2Obj, CSL_InstNum aif2Num, CSL_Aif2Param *paif2Param, CSL_Status *pStatus) |
| | Opens the instance of AIF2 requested.
|
| CSL_Status | CSL_aif2Reset (CSL_Aif2Handle hAif2) |
| | Reset whole AIF2 module.
|
| CSL_Status | CSL_aif2Close (CSL_Aif2Handle hAif2) |
| CSL_Status | CSL_aif2HwSetup (CSL_Aif2Handle hAif2, CSL_Aif2Setup *aif2Setup) |
| CSL_Status | CSL_aif2HwControl (CSL_Aif2Handle hAif2, CSL_Aif2HwControlCmd ctrlCmd, void *arg) |
| | Controls AIF operation based on the control command.
|
|
| CSL_Status | CSL_aif2GetHwStatus (CSL_Aif2Handle hAif2, CSL_Aif2HwStatusQuery Query, void *response) |
| | Get the status of different operations.
|
