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#include <ti/csl/csl_aif2.h>
============================================================================
| static void CSL_aif2AdDataTraceBaseAddr | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 | addr | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdDataTraceBaseAddr
Description
Sets the destination VBUS base address (upper 28 bits of 32 bit data bus) for Rx data trace receive data.
Arguments
hAif2 Handle to the aif2 instance.
Uint32 upper 28 bits of 32 bit data bus (lower 4 bits will be set to zero)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_DT_DMA_CFG1_DT_DMA_RD_BASE_ADDR
Example
Uint32 addr = 0x00480000;//could be L2, DDR3 or other type of memory address
CSL_aif2AdDataTraceBaseAddr(hAif2, addr);
| static void CSL_aif2AdDtDmaWrap | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 | dma_wrap | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdDtDmaWrap
Description
Sets the number of burst transfers before the destination address wraps back to the base address
Arguments
hAif2 Handle to the aif2 instance.
Uint32 Dma burst wrap(terminal count) value for DT
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_DT_DMA_CFG3_DT_DMA_WRAP
Example
Uint32 wrap = 32;
CSL_aif2AdDtDmaChNum(hAif2, wrap);
| static void CSL_aif2AdEDioBcnTableSetup | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 * | DBCN | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEDioBcnTableSetup
Description
Change Egress DIO BCN table dynamically. this function will write new DBCN value to the table which is not used.
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8* DBCN array which has 64 length
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN0,AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN1, AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN2,AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN3, AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN4,AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN5, AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN6,AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN7, AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN8,AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN9, AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN10,AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN11, AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN12,AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN13, AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN14,AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN15, AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN16,AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN17, AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN18,AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN19, AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN20,AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN21, AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN22,AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN23, AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN24,AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN25, AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN26,AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN27, AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN28,AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN29, AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN30,AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN31, AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN32,AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN33, AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN34,AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN35, AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN36,AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN37, AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN38,AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN39, AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN40,AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN41, AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN42,AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN43, AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN44,AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN45, AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN46,AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN47, AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN48,AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN49, AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN50,AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN51, AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN52,AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN53, AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN54,AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN55, AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN56,AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN57, AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN58,AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN59, AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN60,AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN61, AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN62,AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN63;
AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN0,AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN1, AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN2,AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN3, AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN4,AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN5, AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN6,AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN7, AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN8,AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN9, AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN10,AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN11, AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN12,AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN13, AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN14,AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN15, AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN16,AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN17, AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN18,AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN19, AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN20,AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN21, AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN22,AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN23, AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN24,AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN25, AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN26,AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN27, AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN28,AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN29, AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN30,AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN31, AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN32,AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN33, AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN34,AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN35, AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN36,AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN37, AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN38,AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN39, AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN40,AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN41, AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN42,AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN43, AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN44,AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN45, AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN46,AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN47, AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN48,AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN49, AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN50,AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN51, AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN52,AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN53, AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN54,AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN55, AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN56,AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN57, AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN58,AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN59, AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN60,AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN61, AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN62,AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN63; Example
Uint8 DBCN[64];
DBCN[0] = .....
DBCN[1] = .....
..............
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdEDioBcnTableSetup(hAif2, &DBCN[0]);
| static void CSL_aif2AdEDioGlobalEnableDisable | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEDioGlobalEnableDisable
Description
Enable or Disable Global Egress DIO mode dynamically to support DIO channel tearing down
Arguments
hAif2 Handle to the aif2 instance.
Bool true : Enable false : Disable
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_E_GLOBAL_EN_SET_DONT_CARE;AIF2_AD_DIO_E_GLOBAL_EN_CLR_DONT_CARE
Example
Bool arg = false;
CSL_aif2AdEDioGlobalEnableDisable(hAif2, arg);
| static void CSL_aif2AdEDioNumAxC | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEDioNumAxC
Description
Change Egress DIO AxC number dynamically
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8 total number of Antenna carrier
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_E_TABLE_LOOP_CFG_NUM_AXC
Example
Uint8 numAxC = 8;
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdEDioNumAxC(hAif2, numAxC);
| static void CSL_aif2AdEDioTableSelect | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEDioTableSelect
Description
Change Egress DIO table selection dynamically. NumAxC and BCN table setup should be done before changing table select
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8 0 : Table0 1 : Table1
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open(), CSL_aif2AdEDioNumAxC(), CSL_aif2AdEDioBcnTableSetup()
Post Condition
None
Writes
AIF2_AD_DIO_E_TABLE_SEL_BCN_TABLE_SEL
Example
Uint8 table = 1;
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdEDioTableSelect(hAif2, table);
| static void CSL_aif2AdEGlobalEnableDisable | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEGlobalEnableDisable
Description
Enable or Disable Global Egress AD module dynamically to support CPPI channel tearing down
Arguments
hAif2 Handle to the aif2 instance.
Bool true : Enable false : Disable
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_ESCH_GLOBAL_EN_SET_DONT_CARE;AIF2_AD_ESCH_GLOBAL_EN_CLR_DONT_CARE
Example
Bool arg = false;
CSL_aif2AdEGlobalEnableDisable(hAif2, arg);
| static void CSL_aif2AdEnDisDtDmaCh | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdEnDisDtDmaCh
Description
Sets Enable or Disable Data trace DMA Channel for data and framing data
Arguments
hAif2 Handle to the aif2 instance.
Bool true or false
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_DT_DMA_CFG0_DT_DMA_RD_CH_EN,
Example
CSL_aif2AdEnDisDtDmaCh(hAif2, true);
| static void CSL_aif2AdFramingDataBaseAddr | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 | addr | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdFramingDataBaseAddr
Description
Sets the destination VBUS base address (upper 28 bits of 32 bit data bus) for Rx framing data trace receive data.
Arguments
hAif2 Handle to the aif2 instance.
Uint32 upper 28 bits of 32 bit data bus (lower 4 bits will be set to zero)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_DT_DMA_CFG2_DT_DMA_FM_BASE_ADDR
Example
Uint32 addr = 0x00480000;//could be L2, DDR3 or other type of memory address
CSL_aif2AdFramingDataBaseAddr(hAif2, addr);
| static void CSL_aif2AdInDioBcnTableSetup | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 * | DBCN | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdInDioBcnTableSetup
Description
Change Ingress DIO BCN table dynamically. this function will write new DBCN value to the table which is not used.
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8* DBCN array which has 64 length
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN0,AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN1, AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN2,AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN3, AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN4,AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN5, AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN6,AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN7, AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN8,AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN9, AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN10,AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN11, AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN12,AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN13, AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN14,AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN15, AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN16,AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN17, AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN18,AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN19, AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN20,AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN21, AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN22,AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN23, AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN24,AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN25, AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN26,AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN27, AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN28,AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN29, AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN30,AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN31, AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN32,AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN33, AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN34,AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN35, AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN36,AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN37, AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN38,AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN39, AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN40,AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN41, AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN42,AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN43, AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN44,AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN45, AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN46,AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN47, AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN48,AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN49, AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN50,AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN51, AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN52,AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN53, AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN54,AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN55, AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN56,AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN57, AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN58,AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN59, AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN60,AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN61, AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN62,AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN63;
AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN0,AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN1, AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN2,AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN3, AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN4,AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN5, AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN6,AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN7, AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN8,AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN9, AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN10,AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN11, AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN12,AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN13, AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN14,AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN15, AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN16,AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN17, AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN18,AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN19, AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN20,AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN21, AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN22,AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN23, AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN24,AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN25, AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN26,AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN27, AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN28,AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN29, AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN30,AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN31, AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN32,AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN33, AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN34,AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN35, AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN36,AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN37, AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN38,AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN39, AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN40,AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN41, AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN42,AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN43, AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN44,AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN45, AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN46,AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN47, AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN48,AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN49, AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN50,AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN51, AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN52,AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN53, AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN54,AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN55, AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN56,AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN57, AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN58,AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN59, AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN60,AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN61, AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN62,AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN63; Example
Uint8 DBCN[64];
DBCN[0] = .....
DBCN[1] = .....
..............
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdInDioBcnTableSetup(hAif2, &DBCN[0]);
| static void CSL_aif2AdInDioGlobalEnableDisable | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdInDioGlobalEnableDisable
Description
Enable or Disable Global Ingress DIO mode dynamically to support DIO channel tearing down
Arguments
hAif2 Handle to the aif2 instance.
Bool true : Enable false : Disable
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_I_GLOBAL_EN_SET_DONT_CARE;AIF2_AD_DIO_I_GLOBAL_EN_CLR_DONT_CARE
Example
Bool arg = false;
CSL_aif2AdInDioGlobalEnableDisable(hAif2, arg);
| static void CSL_aif2AdInDioNumAxC | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdInDioNumAxC
Description
Change Ingress DIO AxC number dynamically
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8 total number of Antenna carrier
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_I_TABLE_LOOP_CFG_NUM_AXC
Example
Uint8 numAxC = 8;
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdInDioNumAxC(hAif2, numAxC);
| static void CSL_aif2AdInDioTableSelect | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdInDioTableSelect
Description
Change Ingress DIO table selection dynamically. NumAxC and BCN table setup should be done before changing table select
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_dioEngine to select dio engine
Uint8 0 : Table0 1 : Table1
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open() , CSL_aif2AdInDioNumAxC(), CSL_aif2AdInDioBcnTableSetup()
Post Condition
None
Writes
AIF2_AD_DIO_I_TABLE_SEL_BCN_TABLE_SEL
Example
Uint8 table = 1;
hAif2->arg_dioEngine = 1;//Engine 1
CSL_aif2AdInDioTableSelect(hAif2, table);
| static void CSL_aif2AdInGlobalEnableDisable | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AdInGlobalEnableDisable
Description
Enable or Disable Global Ingress AD module dynamically to support CPPI channel tearing down
Arguments
hAif2 Handle to the aif2 instance.
Bool true : Enable false : Disable
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_ISCH_GLOBAL_EN_SET_DONT_CARE;AIF2_AD_ISCH_GLOBAL_EN_CLR_DONT_CARE
Example
Bool arg = false;
CSL_aif2AdInGlobalEnableDisable(hAif2, arg);
| static void CSL_aif2AtArmTimer | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arm | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtArmTimer
Description
Arm AT timers
Arguments
hAif2 Handle to the aif2 instance.
Bool Enable Arm timers
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_CONTROL2_ARM_TIMER,AIF2_AT_CONTROL2_HALT_TIMER
Example
Bool arm = true;
CSL_aif2AtArmTimer(hAif2, arm);
| static void CSL_aif2AtDeltaSetup | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 | delta | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtDeltaSetup
Description
Sets Delta offset for specified link
Arguments
hAif2 Handle to the aif2 instance. should use hAif2->arg_link to select link
Uint32 New Delta offset value
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET,AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO
Example
Uint32 delta = 0x80;
CSL_aif2AtDeltaSetup(hAif2, delta);
| static void CSL_aif2AtDisableAllEvents | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtDisableAllEvents
Description
Disable All AT Events
Arguments
hAif2 Handle to the aif2 instance.
Bool Disable all events
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE,AIF2_AT_EVT_ENABLE_EVENTENABLE
Example
Bool arg = true;
CSL_aif2AtDisableAllEvents(hAif2, arg);
| static void CSL_aif2AtDisableEvent | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtEventIndex | event_index | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtDisableEvent
Description
Disable Eight Rad and Six DIO Events
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtEventIndex Event index to select event
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_EVT_ENABLE_EVENTENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Reads
AIF2_AT_EVT_ENABLE_EVENTENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Example
CSL_Aif2AtEventIndex event = 1; //Rad event 1
CSL_aif2AtDisableEvent(hAif2, event);
| static void CSL_aif2AtEnableEvent | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtEventIndex | event_index | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtEnableEvent
Description
Enable Eight Rad and Six DIO Events
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtEventIndex Event index to select event
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_EVT_ENABLE_EVENTENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Reads
AIF2_AT_EVT_ENABLE_EVENTENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE;AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Example
CSL_Aif2AtEventIndex event = 1; //Rad event 1
CSL_aif2AtEnableEvent(hAif2, event);
| static void CSL_aif2AtEventSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtEvent | Event | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtEventSetup
Description
Sets AT External Rad timer event and dio event dynamically. EventMask should be set to zero if the Event is not for GSM
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtEvent At event structure to setup offset, modulus and strobe select
* Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_EVENT_OFFSET_EVENTINDEX,AIF2_AT_EVENT_OFFSET_STROBESELECT,AIF2_AT_EVENT_MOD_TC_EVENTMODULO, AIF2_AT_EVENT_MASK_LSBS_EVENTMASK_LSBS,AIF2_AT_EVENT_MASK_MSBS_EVENTMASK_MSBS; AIF2_AT_AD_INGR_EVENT_OFFSET_EVENTINDEX,AIF2_AT_AD_INGR_EVENT_OFFSET_STROBESELECT, AIF2_AT_AD_INGR_EVENT_MOD_TC_EVENTMODULO; AIF2_AT_AD_EGR_EVENT_OFFSET_EVENTINDEX, AIF2_AT_AD_EGR_EVENT_OFFSET_STROBESELECT, AIF2_AT_AD_EGR_EVENT_MOD_TC_EVENTMODULO; Example
CSL_Aif2AtEvent Event;
Event.EventSelect = CSL_AIF2_EVENT_7;
Event.Eventoffset = ....
Event.EventModulo = ....
........
Event.EventMaskLsb = 0;//if it is not GSM event, it should be zero
Event.EventMaskLsb = 0;
CSL_aif2AtEventSetup(hAif2, Event);
| static void CSL_aif2AtForceEvent | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtEventIndex | event_index | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtForceEvent
Description
Force set Eight Rad and Six DIO Events
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtEventIndex Event index to select event
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_EVT_FORCE_EVENTFORCE;AIF2_AT_INTERNAL_EVT_FORCE_ADINGR_EVENT_FORCE;AIF2_AT_INTERNAL_EVT_FORCE_ADEGR_EVENT_FORCE
Example
CSL_Aif2AtEventIndex event = 1; //Rad event 1
CSL_aif2AtForceEvent(hAif2, event);
| static void CSL_aif2AtGsmTcountSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtGsmTCount | tc | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtGsmTcountSetup
Description
Setup AT GSM Tcount
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtGsmTCount Tcount value structure
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_GSM_TCOUNT_INIT_T1,AIF2_AT_GSM_TCOUNT_INIT_T2, AIF2_AT_GSM_TCOUNT_INIT_T3
Example
CSL_Aif2AtGsmTCount Tcount;
Tcount.t1 = 13;
Tcount.t2= 25;
Tcount.t3 = 2048;
.........
CSL_aif2AtGsmTcountSetup(hAif2, Tcount);
| static void CSL_aif2AtHaltTimer | ( | CSL_Aif2Handle | hAif2, | |
| Bool | halt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtHaltTimer
Description
Halt AT timers
Arguments
hAif2 Handle to the aif2 instance.
Bool Enable Halt timers
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_CONTROL2_HALT_TIMER,AIF2_AT_CONTROL2_ARM_TIMER
Example
Bool halt = true;
CSL_aif2AtHaltTimer(hAif2, halt);
| static void CSL_aif2AtRadTcSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2AtTcObj | tc | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtRadTcSetup
Description
trigger Rad timer SW debug sync
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2AtTcObj Trigger Rad debug sync
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_RADT_SYMB_LUT_INDEX_TC_LUTINDEX_TC,AIF2_AT_RADT_SYMB_LUT_INDEX_TC_SYMBOLTC, AIF2_AT_RADT_FRAME_TC_LSBS_RADTFRAME_TC_LSBS,AIF2_AT_RADT_FRAME_TC_MSBS_RADTFRAME_TC_MSBS, AIF2_AT_RADT_SYM_LUT_RAM_RADT_CLOCK_TC
Example
CSL_Aif2AtTcObj Tc;
CSL_Aif2AtCountObj Count;
Count.LutIndexNum = ....;
...................
Tc.pRadTimerTc = &Count;
Tc.RadClockCountTc[0] = ....;
Tc.RadClockCountTc[1] = ....;
.........
CSL_aif2AtRadTcSetup(hAif2, Tc);
| static void CSL_aif2AtRadWcdmaDiv | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | tc | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtRadWcdmaDiv
Description
at radt wcdma clock divider terminal count. This counter divides dualbyte clock down to 3.84MHz chip rate for wcdma counters
Arguments
hAif2 Handle to the aif2 instance.
Uint8 Terminal count
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_RADT_WCDMA_DIV_TERMINALCOUNT
Example
Uint8 tc = 80;
CSL_aif2AtRadWcdmaDiv(hAif2, tc); //lower down 307.2 MHz to 3.84 MHz
| static void CSL_aif2AtSwDebugSync | ( | CSL_Aif2Handle | hAif2, | |
| Bool | sync | |||
| ) | [inline, static] |
============================================================================
CSL_aif2AtSwDebugSync
Description
trigger Phy and Rad timer SW debug sync
Arguments
hAif2 Handle to the aif2 instance.
Bool Trigger debug sync
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_SW_SYNC_PHY_SYNC,AIF2_AT_SW_SYNC_RAD_SYNC
Example
Bool sync = true;
CSL_aif2AtSwDebugSync(hAif2, sync);
| static void CSL_aif2EDbChannelSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2DbChannel | channel_setup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbChannelSetup
Description
Setup Egress DB channel to add or remove channel dynamically (argument type: CSL_Aif2DbChannel *)
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2DbChannel aif2 Db channel setup structure
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_PTR_CH_BASE_ADDR,AIF2_DB_EDB_PTR_CH_BUF_DEPTH, AIF2_DB_EDB_CFG_CH_DAT_SWAP, AIF2_DB_EDB_CFG_CH_IQ_ORDER,AIF2_DB_EDB_CFG_CH_DIO_OFFSET Example
CSL_Aif2DbChannel newChannel;
newChannel.ChannelNum = 3;
........................................
newChannel.EgressDioOffset = 0;
CSL_aif2EDbChannelSetup(hAif2, newChannel);
| static void CSL_aif2EDbChEnable | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 * | channel | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbChEnable
Description
Enable or Disable Egress DB channel to add or remove channel dynamically
Arguments
hAif2 Handle to the aif2 instance
Uint32* arg[0] ~ arg[3] : bit 0 ~ 127 for all channels
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_CH_EN_EN
Example
Uint32 InDbChannel[4];
InDbChannel[0] = 0x00000001;//channel 31 ~ 0
InDbChannel[1] = 0x0.... //channel 63 ~ 32
InDbChannel[2] = 0x0.... //channel 95 ~ 64
InDbChannel[3] = 0x0.... //channel 127 ~ 96
CSL_aif2EDbChEnable(hAif2, &InDbChannel[0]);
| static void CSL_aif2EDbDebugOffsetAddr | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 * | offset_addr | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbDebugOffsetAddr
Description
Set write and read Address(channel number) used to access write or read Offset RAM for DB Debug (getting debug ram offset could be useful function for sw developer) Real Offset value of DB debug Ram could be obtained using CSL_aif2EDbDebugGetOffsetData() function.
Arguments
hAif2 Handle to the aif2 instance
Uint8* arg[0] : write offset address(channel num), arg[1] : read offset address(channel num)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_DEBUG_OFS_WADDR, AIF2_DB_EDB_DEBUG_OFS_RADDR
Example
Uint8 debug_addr[2];
debug_addr[0] = write_address; //0~ 127
debug_addr[1] = read_address; //0~ 127
CSL_aif2EDbDebugOffsetAddr(hAif2, &debug_addr[0]);
| static void CSL_aif2EDbDebugRead | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbDebugRead
Description
Reads the data into the following registers from the Egress DB and sideband RAMS DB_EDB_DEBUG_D0, DB_EDB_DEBUG_D1, DB_EDB_DEBUG_D2, DB_EDB_DEBUG_D3, DB_EDB_DEBUG_SBDN
Arguments
hAif2 Handle to the aif2 instance
Bool True : Read data and side data in the debug data RAM
Return Value None
Pre Condition
*
CSL_aif2Init(), CSL_aif2Open(), CSL_aif2EDbDebugReadControl()
Post Condition
None
Writes
AIF2_DB_EDB_DEBUG_DB_RD_DONT_CARE,
Example
Bool arg = true;
CSL_aif2EDbDebugRead(hAif2, arg);
| static void CSL_aif2EDbDebugReadControl | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2DbSideData | side_data | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbDebugReadControl
Description
Setup Side band data control info like dio read enable and channel id
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2DbSideData only dio_rd_en, ch_id field will be used
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_DEBUG_RD_CNTL_DIO_RD_EN, AIF2_DB_EDB_DEBUG_RD_CNTL_CH_ID
Example
CSL_Aif2DbSideData side_control ;
side_control.bEnFifoBufferRead = true;
side_control.ChannelId = 0;
CSL_aif2EDbDebugReadControl(hAif2, side_control);
| static void CSL_aif2EDbDebugWrToken | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbDebugWrToken
Description
when this register is set to true, the value loaded into DB_EDB_DEBUG_RD_CNTL.CH_ID being issued to the AxC Token FIFO and 64 bytes of packet data will be transfered to Egress DB RAM from L2.
Arguments
hAif2 Handle to the aif2 instance
Bool True : Read data from L2 to Egress DB ram
* Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open(), CSL_aif2EDbEnDisDebug(), CSL_aif2EDbDebugReadControl()
Post Condition
None
Writes
AIF2_DB_EDB_DEBUG_WR_TOK_DONT_CARE
Example
Bool arg = true;
CSL_aif2EDbDebugWrToken(hAif2, arg);
| static void CSL_aif2EDbEnDisDebug | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EDbEnDisDebug
Description
Enables Egress DB Debug mode for customer SW debug
Arguments
hAif2 Handle to the aif2 instance
Bool true : Debug on false : Debug off
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_CFG_EDB_DEBUG_EN
Example
Bool arg = true;
CSL_aif2EDbEnDisDebug (hAif2, arg);
| static void CSL_aif2EeAdIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeAdInt | AdInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeAdIntSetup
Description
EE AD interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeAdInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_AD_IRS_SET_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_IRS_SET_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_IRS_SET_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_IRS_SET_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_IRS_SET_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_IRS_SET_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_IRS_SET_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_IRS_SET_AD_EE_E_DMA_2_ERR; AIF2_EE_AD_IRS_CLR_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_IRS_CLR_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_IRS_CLR_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_IRS_CLR_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_IRS_CLR_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_IRS_CLR_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_IRS_CLR_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_IRS_CLR_AD_EE_E_DMA_2_ERR;
AIF2_EE_AD_EN_SET_EV0_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_EN_SET_EV0_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_EN_SET_EV0_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_EN_SET_EV0_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_EN_SET_EV0_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_EN_SET_EV0_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_EN_SET_EV0_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_EN_SET_EV0_AD_EE_E_DMA_2_ERR; AIF2_EE_AD_EN_CLR_EV0_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_EN_CLR_EV0_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_EN_CLR_EV0_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_EN_CLR_EV0_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_EN_CLR_EV0_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_EN_CLR_EV0_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_EN_CLR_EV0_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_EN_CLR_EV0_AD_EE_E_DMA_2_ERR;
AIF2_EE_AD_EN_SET_EV1_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_EN_SET_EV1_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_EN_SET_EV1_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_EN_SET_EV1_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_EN_SET_EV1_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_EN_SET_EV1_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_EN_SET_EV1_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_EN_SET_EV1_AD_EE_E_DMA_2_ERR; AIF2_EE_AD_EN_CLR_EV1_AD_EE_I_CD_DATA_ERR,AIF2_EE_AD_EN_CLR_EV1_AD_EE_E_CD_SCH_ERR, AIF2_EE_AD_EN_CLR_EV1_AD_EE_I_DMA_0_ERR,AIF2_EE_AD_EN_CLR_EV1_AD_EE_I_DMA_1_ERR, AIF2_EE_AD_EN_CLR_EV1_AD_EE_I_DMA_2_ERR,AIF2_EE_AD_EN_CLR_EV1_AD_EE_E_DMA_0_ERR, AIF2_EE_AD_EN_CLR_EV1_AD_EE_E_DMA_1_ERR,AIF2_EE_AD_EN_CLR_EV1_AD_EE_E_DMA_2_ERR; Example
CSL_Aif2EeAdInt AdInt;
AdInt.ad_ee_i_cd_data_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeAdIntSetup(hAif2, AdInt);
| static void CSL_aif2EeAif2ErrorIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeAif2Int | Aif2ErrInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeAif2ErrorIntSetup
Description
EE VB error interrupt set or clear
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select between set and clear
CSL_Aif2EeAif2Int
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_VB_INTR_SET_ERR_INTR_SET,AIF2_EE_VB_INTR_SET_ALARM_INTR_SET,AIF2_EE_VB_INTR_SET_CDMA_INTR_SET; AIF2_EE_VB_INTR_CLR_ERR_INTR_CLR,AIF2_EE_VB_INTR_CLR_ALARM_INTR_CLR,AIF2_EE_VB_INTR_CLR_CDMA_INTR_CLR; Example
CSL_Aif2EeAif2Int Aif2ErrInt;
Aif2ErrInt.Error_intr = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeAif2ErrorIntSetup(hAif2, Aif2ErrInt);
| static void CSL_aif2EeAif2RunSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeAif2Run | Aif2Run | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeAif2RunSetup
Description
EE Aif2 run control register setup
Arguments
hAif2 Handle to the aif2 instance.
CSL_Aif2EeAif2Run phy run and global run setup
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_AIF2_RUN_CTL_AIF2_PHY_RUN,AIF2_EE_AIF2_RUN_CTL_AIF2_GLOBAL_RUN;
Example
CSL_Aif2EeVcInt Aif2Run;
Aif2Run.aif2_phy_run = true;
Aif2Run.aif2_global_run = true;
CSL_aif2EeAif2RunSetup(hAif2, Aif2Run);
| static void CSL_aif2EeAtIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeAtInt | AtInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeAtIntSetup
Description
EE AT interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeAtInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_IRS_SET_AT_EE_PI0_ERR,AIF2_EE_AT_IRS_SET_AT_EE_PI1_ERR,AIF2_EE_AT_IRS_SET_AT_EE_PI2_ERR, AIF2_EE_AT_IRS_SET_AT_EE_PI3_ERR,AIF2_EE_AT_IRS_SET_AT_EE_PI4_ERR,AIF2_EE_AT_IRS_SET_AT_EE_PI5_ERR, AIF2_EE_AT_IRS_SET_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_IRS_SET_AT_EE_RADT_SYNC_ERR;
AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_PI0_ERR,AIF2_EE_AT_IRS_CLR_AT_EE_PI1_ERR,AIF2_EE_AT_IRS_CLR_AT_EE_PI2_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_PI3_ERR,AIF2_EE_AT_IRS_CLR_AT_EE_PI4_ERR,AIF2_EE_AT_IRS_CLR_AT_EE_PI5_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_IRS_CLR_AT_EE_RADT_SYNC_ERR;
AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_PI0_ERR,AIF2_EE_AT_EN_SET_EV0_AT_EE_PI1_ERR,AIF2_EE_AT_EN_SET_EV0_AT_EE_PI2_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_PI3_ERR,AIF2_EE_AT_EN_SET_EV0_AT_EE_PI4_ERR,AIF2_EE_AT_EN_SET_EV0_AT_EE_PI5_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_EN_SET_EV0_AT_EE_RADT_SYNC_ERR;
AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI0_ERR,AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI1_ERR,AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI2_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI3_ERR,AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI4_ERR,AIF2_EE_AT_EN_CLR_EV0_AT_EE_PI5_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_EN_CLR_EV0_AT_EE_RADT_SYNC_ERR;
AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_PI0_ERR,AIF2_EE_AT_EN_SET_EV1_AT_EE_PI1_ERR,AIF2_EE_AT_EN_SET_EV1_AT_EE_PI2_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_PI3_ERR,AIF2_EE_AT_EN_SET_EV1_AT_EE_PI4_ERR,AIF2_EE_AT_EN_SET_EV1_AT_EE_PI5_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_EN_SET_EV1_AT_EE_RADT_SYNC_ERR;
AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_SYS_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_RP3_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_TOD_RCVD_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_UNSEL_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_SPARE_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_TYPE_RSVD_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_BIT_WIDTH_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_CRC_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_RP3_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RP1_SYS_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI0_ERR,AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI1_ERR,AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI2_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI3_ERR,AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI4_ERR,AIF2_EE_AT_EN_CLR_EV1_AT_EE_PI5_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_PHYT_SYNC_ERR, AIF2_EE_AT_EN_CLR_EV1_AT_EE_RADT_SYNC_ERR; Example
CSL_Aif2EeAtInt AtInt;
AtInt.ad_ee_i_cd_data_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeAtIntSetup(hAif2, AtInt);
| static void CSL_aif2EeCdIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeCdInt | CdInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeCdIntSetup
Description
EE CD(PKTDMA) interrupt set, clear, enable set or clear for EV0
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeCdInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_CD_IRS_SET_CD_EE_SOP_DESC_STARVE_ERR,AIF2_EE_CD_IRS_SET_CD_EE_MOP_DESC_STARVE_ERR; AIF2_EE_CD_IRS_CLR_CD_EE_SOP_DESC_STARVE_ERR,AIF2_EE_CD_IRS_CLR_CD_EE_MOP_DESC_STARVE_ERR;
AIF2_EE_CD_EN_SET_EV_CD_EE_SOP_DESC_STARVE_ERR,AIF2_EE_CD_EN_SET_EV_CD_EE_MOP_DESC_STARVE_ERR; AIF2_EE_CD_EN_CLR_EV_CD_EE_SOP_DESC_STARVE_ERR,AIF2_EE_CD_EN_CLR_EV_CD_EE_MOP_DESC_STARVE_ERR; Example
CSL_Aif2EeCdInt CdInt;
CdInt.cd_ee_sop_desc_starve_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeCdIntSetup(hAif2, CdInt);
| static void CSL_aif2EeDbIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeDbInt | DbInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeDbIntSetup
Description
EE DB interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeDbInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_DB_IRS_SET_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_IRS_SET_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_IRS_SET_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_IRS_SET_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_IRS_SET_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_IRS_SET_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_IRS_SET_DB_EE_E_CD_DATA_TYPE_ERR; AIF2_EE_DB_IRS_CLR_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_IRS_CLR_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_IRS_CLR_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_IRS_CLR_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_IRS_CLR_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_IRS_CLR_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_IRS_CLR_DB_EE_E_CD_DATA_TYPE_ERR; AIF2_EE_DB_EN_SET_EV0_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_EN_SET_EV0_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_EN_SET_EV0_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_EN_SET_EV0_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_EN_SET_EV0_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_EN_SET_EV0_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_EN_SET_EV0_DB_EE_E_CD_DATA_TYPE_ERR; AIF2_EE_DB_EN_CRL_EV0_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_EN_CRL_EV0_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_EN_CRL_EV0_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_EN_CRL_EV0_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_EN_CRL_EV0_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_EN_CRL_EV0_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_EN_CRL_EV0_DB_EE_E_CD_DATA_TYPE_ERR; AIF2_EE_DB_EN_SET_EV1_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_EN_SET_EV1_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_EN_SET_EV1_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_EN_SET_EV1_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_EN_SET_EV1_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_EN_SET_EV1_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_EN_SET_EV1_DB_EE_E_CD_DATA_TYPE_ERR; AIF2_EE_DB_EN_CRL_EV1_DB_EE_I_TRC_RAM_OVFL_ERR,AIF2_EE_DB_EN_CRL_EV1_DB_EE_I_TOKEN_OVFL_ERR, AIF2_EE_DB_EN_CRL_EV1_DB_EE_I_FIFO_OVFL_ERR,AIF2_EE_DB_EN_CRL_EV1_DB_EE_I_PD2DB_FULL_ERR, AIF2_EE_DB_EN_CRL_EV1_DB_EE_E_PS_AXC_ERR,AIF2_EE_DB_EN_CRL_EV1_DB_EE_E_CD_DATA_ERR, AIF2_EE_DB_EN_CRL_EV1_DB_EE_E_CD_DATA_TYPE_ERR; Example
CSL_Aif2EeDbInt DbInt;
DbInt.db_ee_i_trc_ram_ovfl_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeDbIntSetup(hAif2, DbInt);
| static void CSL_aif2EeEoiSetup | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | EOI | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeEoiSetup
Description
EE End of interrupt vector value setup
Arguments
hAif2 Handle to the aif2 instance.
Uint8 End of Interrupt value
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_VB_EOI_EOI_VECTOR
Example
Uint8 eoi = 0x1;
CSL_aif2EeEoiSetup(hAif2, eoi);
| static void CSL_aif2EeLinkAIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeLinkAInt | LinkAInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeLinkAIntSetup
Description
EE Link A interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function and hAif2->arg_link to select link
CSL_Aif2EeLinkAInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_LK_IRS_SET_A_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_LCV_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_LOC_DET_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_LOS_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_LOF_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_IRS_SET_A_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_IRS_SET_A_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_IRS_SET_A_TM_EE_FIFO_STARVE_ERR;
AIF2_EE_LK_IRS_CLR_A_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_LCV_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_LOC_DET_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_LOS_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_LOF_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_IRS_CLR_A_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_IRS_CLR_A_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_IRS_CLR_A_TM_EE_FIFO_STARVE_ERR;
AIF2_EE_LK_EN_A_SET_EV0_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_LCV_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_LOC_DET_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_LOS_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_LOF_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_EN_A_SET_EV0_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_EN_A_SET_EV0_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_EN_A_SET_EV0_TM_EE_FIFO_STARVE_ERR;
AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_LCV_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_LOC_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_LOS_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_LOF_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_EN_A_CLR_EV0_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_EN_A_CLR_EV0_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_EN_A_CLR_EV0_TM_EE_FIFO_STARVE_ERR;
AIF2_EE_LK_EN_A_SET_EV1_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_LCV_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_LOC_DET_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_LOS_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_LOF_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_EN_A_SET_EV1_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_EN_A_SET_EV1_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_EN_A_SET_EV1_TM_EE_FIFO_STARVE_ERR;
AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_SYNC_STATUS_CHANGE_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_NUM_LOS_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_LCV_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_FRAME_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_BLOCK_BNDRY_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_MISSING_K28P5_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_MISSING_K28P7_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_K30P7_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_LOC_DET_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_RX_FIFO_OVF_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_RCVD_LOS_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_RCVD_LOF_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_RCVD_RAI_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_RCVD_SDI_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_LOS_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_LOF_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_HFNSYNC_STATE_ERR, AIF2_EE_LK_EN_A_CLR_EV1_RM_EE_LOF_STATE_ERR, AIF2_EE_LK_EN_A_CLR_EV1_TM_EE_FRM_MISALIGN_ERR, AIF2_EE_LK_EN_A_CLR_EV1_TM_EE_FIFO_STARVE_ERR; Example
CSL_Aif2EeLinkAInt LinkAInt;
LinkAInt.rm_ee_sync_status_change_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
hAif2->arg_link = 0;//link 0
CSL_aif2EeLinkAIntSetup(hAif2, LinkAInt);
| static void CSL_aif2EeLinkBIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeLinkBInt | LinkBInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeLinkBIntSetup
Description
EE Link B interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function and hAif2->arg_link to select link
CSL_Aif2EeLinkBInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_LK_IRS_SET_B_PD_EE_EOP_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_CRC_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_SOP_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_IRS_SET_B_PD_EE_WR2DB_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_MODRULE_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_SYM_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_RT_IF_ERR, AIF2_EE_LK_IRS_SET_B_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_IRS_SET_B_RT_EE_FRM_ERR, AIF2_EE_LK_IRS_SET_B_RT_EE_OVFL_ERR, AIF2_EE_LK_IRS_SET_B_RT_EE_UNFL_ERR, AIF2_EE_LK_IRS_SET_B_RT_EE_EM_ERR, AIF2_EE_LK_IRS_SET_B_RT_EE_HDR_ERR;
AIF2_EE_LK_IRS_CLR_B_PD_EE_EOP_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_CRC_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_SOP_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_IRS_CLR_B_PD_EE_WR2DB_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_MODRULE_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_SYM_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_RT_IF_ERR, AIF2_EE_LK_IRS_CLR_B_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_IRS_CLR_B_RT_EE_FRM_ERR, AIF2_EE_LK_IRS_CLR_B_RT_EE_OVFL_ERR, AIF2_EE_LK_IRS_CLR_B_RT_EE_UNFL_ERR, AIF2_EE_LK_IRS_CLR_B_RT_EE_EM_ERR, AIF2_EE_LK_IRS_CLR_B_RT_EE_HDR_ERR;
AIF2_EE_LK_EN_B_SET_EV0_PD_EE_EOP_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_CRC_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_SOP_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_EN_B_SET_EV0_PD_EE_WR2DB_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_MODRULE_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_SYM_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_RT_IF_ERR, AIF2_EE_LK_EN_B_SET_EV0_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_EN_B_SET_EV0_RT_EE_FRM_ERR, AIF2_EE_LK_EN_B_SET_EV0_RT_EE_OVFL_ERR, AIF2_EE_LK_EN_B_SET_EV0_RT_EE_UNFL_ERR, AIF2_EE_LK_EN_B_SET_EV0_RT_EE_EM_ERR, AIF2_EE_LK_EN_B_SET_EV0_RT_EE_HDR_ERR;
AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_EOP_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_CRC_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_SOP_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PD_EE_WR2DB_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_MODRULE_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_SYM_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_RT_IF_ERR, AIF2_EE_LK_EN_B_CLR_EV0_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_EN_B_CLR_EV0_RT_EE_FRM_ERR, AIF2_EE_LK_EN_B_CLR_EV0_RT_EE_OVFL_ERR, AIF2_EE_LK_EN_B_CLR_EV0_RT_EE_UNFL_ERR, AIF2_EE_LK_EN_B_CLR_EV0_RT_EE_EM_ERR, AIF2_EE_LK_EN_B_CLR_EV0_RT_EE_HDR_ERR;
AIF2_EE_LK_EN_B_SET_EV1_PD_EE_EOP_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_CRC_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_SOP_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_EN_B_SET_EV1_PD_EE_WR2DB_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_MODRULE_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_SYM_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_RT_IF_ERR, AIF2_EE_LK_EN_B_SET_EV1_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_EN_B_SET_EV1_RT_EE_FRM_ERR, AIF2_EE_LK_EN_B_SET_EV1_RT_EE_OVFL_ERR, AIF2_EE_LK_EN_B_SET_EV1_RT_EE_UNFL_ERR, AIF2_EE_LK_EN_B_SET_EV1_RT_EE_EM_ERR, AIF2_EE_LK_EN_B_SET_EV1_RT_EE_HDR_ERR;
AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_EOP_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_CRC_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_CPRI_FRAME_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_AXC_FAIL_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_SOP_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_OBSAI_FRM_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PD_EE_WR2DB_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_MODRULE_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_SYM_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_MF_FIFO_OVERFLOW_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_MF_FIFO_UNDERFLOW_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_DB_STARVE_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_RT_IF_ERR, AIF2_EE_LK_EN_B_CLR_EV1_PE_EE_PKT_STARVE_ERR, AIF2_EE_LK_EN_B_CLR_EV1_RT_EE_FRM_ERR, AIF2_EE_LK_EN_B_CLR_EV1_RT_EE_OVFL_ERR, AIF2_EE_LK_EN_B_CLR_EV1_RT_EE_UNFL_ERR, AIF2_EE_LK_EN_B_CLR_EV1_RT_EE_EM_ERR, AIF2_EE_LK_EN_B_CLR_EV1_RT_EE_HDR_ERR; Example
CSL_Aif2EeLinkBInt LinkBInt;
LinkBInt.rm_ee_sync_status_change_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
hAif2->arg_link = 0; //link 0
CSL_aif2EeLinkBIntSetup(hAif2, LinkBInt);
| static void CSL_aif2EePdIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EePdInt | PdInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EePdIntSetup
Description
EE PD interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EePdInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_PD_COMMON_IRS_SET_PD_EE_TS_WDOG_ERR;AIF2_EE_PD_COMMON_IRS_CLR_PD_EE_TS_WDOG_ERR; AIF2_EE_PD_COMMON_EN_SET_EV0_PD_EE_TS_WDOG_ERR;AIF2_EE_PD_COMMON_EN_CLR_EV0_PD_EE_TS_WDOG_ERR; AIF2_EE_PD_COMMON_EN_SET_EV1_PD_EE_TS_WDOG_ERR;AIF2_EE_PD_COMMON_EN_CLR_EV1_PD_EE_TS_WDOG_ERR Example
CSL_Aif2EePdInt PdInt;
PdInt.pd_ee_ts_wdog_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EePdIntSetup(hAif2, PdInt);
| static void CSL_aif2EePeIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EePeInt | PeInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EePeIntSetup
Description
EE PE interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EePeInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_PE_COMMON_IRS_SET_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_IRS_SET_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_IRS_SET_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_IRS_SET_PE_EE_DAT_REQ_OVFL_ERR; AIF2_EE_PE_COMMON_IRS_CLR_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_IRS_CLR_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_IRS_CLR_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_IRS_CLR_PE_EE_DAT_REQ_OVFL_ERR; AIF2_EE_PE_COMMON_EN_SET_EV0_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_EN_SET_EV0_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_EN_SET_EV0_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_EN_SET_EV0_PE_EE_DAT_REQ_OVFL_ERR; AIF2_EE_PE_COMMON_EN_CLR_EV0_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_EN_CLR_EV0_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_EN_CLR_EV0_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_EN_CLR_EV0_PE_EE_DAT_REQ_OVFL_ERR; AIF2_EE_PE_COMMON_EN_SET_EV1_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_EN_SET_EV1_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_EN_SET_EV1_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_EN_SET_EV1_PE_EE_DAT_REQ_OVFL_ERR; AIF2_EE_PE_COMMON_EN_CLR_EV1_PE_EE_RD2DB_ERR,AIF2_EE_PE_COMMON_EN_CLR_EV1_PE_EE_TOKEN_REQ_OVFL_ERR, AIF2_EE_PE_COMMON_EN_CLR_EV1_PE_EE_TOKEN_WR_ERR,AIF2_EE_PE_COMMON_EN_CLR_EV1_PE_EE_DAT_REQ_OVFL_ERR; Example
CSL_Aif2EePeInt PeInt;
PeInt.pe_ee_rd2db_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EePeIntSetup(hAif2, PeInt);
| static void CSL_aif2EeSdIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeSdInt | SdInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeSdIntSetup
Description
EE SERDES interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeSdInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_SD_IRS_SET_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_IRS_SET_SD_EE_STSPLL_B8_ERR; AIF2_EE_SD_IRS_CLR_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_IRS_CLR_SD_EE_STSPLL_B8_ERR;
AIF2_EE_SD_EN_SET_EV0_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_EN_SET_EV0_SD_EE_STSPLL_B8_ERR; AIF2_EE_SD_EN_CLR_EV0_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_EN_CLR_EV0_SD_EE_STSPLL_B8_ERR; AIF2_EE_SD_EN_SET_EV1_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_EN_SET_EV1_SD_EE_STSPLL_B8_ERR; AIF2_EE_SD_EN_CLR_EV1_SD_EE_STSPLL_B4_ERR,AIF2_EE_SD_EN_CLR_EV1_SD_EE_STSPLL_B8_ERR; Example
CSL_Aif2EeSdInt SdInt;
SdInt.sd_ee_stspll_b4_err = true;
.........
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeSdIntSetup(hAif2, SdInt);
| static void CSL_aif2EeVcIntSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2EeVcInt | VcInt | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EeVcIntSetup
Description
EE VC interrupt set, clear, enable set or clear for EV0 and EV1
Arguments
hAif2 Handle to the aif2 instance. use hAif2->ee_arg to select function
CSL_Aif2EeVcInt
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_EE_VC_IRS_SET_VC_EE_VBUS_ERR;AIF2_EE_VC_IRS_CLR_VC_EE_VBUS_ERR;
AIF2_EE_VC_EN_SET_EV0_VC_EE_VBUS_ERR;AIF2_EE_VC_EN_CLR_EV0_VC_EE_VBUS_ERR;
AIF2_EE_VC_EN_SET_EV1_VC_EE_VBUS_ERR;AIF2_EE_VC_EN_CLR_EV1_VC_EE_VBUS_ERR; Example
CSL_Aif2EeVcInt VcInt;
VcInt.vc_ee_vbus_err = true;
hAif2->ee_arg = CSL_AIF2_EE_INT_SET;
CSL_aif2EeVcIntSetup(hAif2, VcInt);
| static void CSL_aif2EnDisLinkLoopback | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnDisLinkLoopback
Description
Enable or Disable link internal loopback and this function controls Rx and Tx side together
Arguments
hAif2 Handle to the aif2 instance. should use arg_link to select link
Bool arg: True or False
Return Value None Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_RX_R2_CFG_RXLOOPBACK=3,AIF2_SD_TX_R1_CFG_TXLOOPBACK=2,AIF2_SD_RX_R1_CFG_RXLOSS_OF_SIGNAL=0; AIF2_SD_RX_R2_CFG_RXLOOPBACK=0,AIF2_SD_TX_R1_CFG_TXLOOPBACK=0,AIF2_SD_RX_R1_CFG_RXLOSS_OF_SIGNAL=4
Example
hAif2->arg_link = 1;
CSL_aif2EnDisLinkLoopback (hAif2, true);
| static void CSL_aif2EnDisRxLink | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnDisRxLink
Description
This function Starts or Stop SERDES Rx link
Arguments
hAif2 Handle to the aif2 instance (should use hAif2->arg_link to select link)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_RX_EN_CFG_ENABLERX=1; AIF2_SD_RX_EN_CFG_ENABLERX=0 Example
Bool arg = true;
hAif2->arg_link =0; //enable link 0
CSL_aif2EnDisRxLink (hAif2, arg);
| static void CSL_aif2EnDisSdB4Pll | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnDisSdB4Pll
Description
This function enables or disables SD B4 PLL
Arguments
hAif2 Handle to the aif2 instance
arg True or False
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_PLL_B4_EN_CFG_ENABLEB4_PLL=1;AIF2_SD_PLL_B4_EN_CFG_ENABLEB4_PLL=0
Example
CSL_aif2EnDisSdB4Pll (hAif2, arg);
| static void CSL_aif2EnDisSdB8Pll | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnDisSdB8Pll
Description
This function enables or disables SD B8 PLL
Arguments
hAif2 Handle to the aif2 instance
arg True or False
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_PLL_B8_EN_CFG_ENABLEB8_PLL=1;AIF2_SD_PLL_B8_EN_CFG_ENABLEB8_PLL=0
Example
CSL_aif2EnDisSdB8Pll (hAif2, arg);
| static void CSL_aif2EnDisTxLink | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnDisTxLink
Description
This function Starts or stops SERDES Tx link
Arguments
hAif2 Handle to the aif2 instance (should use hAif2->arg_link to select link)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_TX_EN_CFG_ENABLETX=1; AIF2_SD_TX_EN_CFG_ENABLETX=0
Example
Bool arg = true;
hAif2->arg_link =0;
CSL_aif2EnDisTxLink (hAif2, arg);
| static void CSL_aif2EnRxLinkDataCapture | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnLinkDataCapture
Description
Enables Trace data and framing data capture for specific link
Arguments
hAif2 Handle to the aif2 instance and link argument (arg_link) should be used
Bool true : enable false : disable
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_RM_CFG_RAW_DATA_SEL,AIF2_DB_IDB_CFG_DTB_EN,AIF2_DB_IDB_CFG_DTF_EN, AIF2_DB_IDB_CFG_DT_EN
Example
Bool arg = true;
CSL_aif2EnLinkDataCapture (hAif2, (void *)&arg);
| static void CSL_aif2EnRxTraceDataSync | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2EnRxTraceDataSync
Description
Flushes all outbound pktsw fifo's if a memory leak is detected
Arguments
hAif2 Handle to the aif2 instance
Bool true : Enable data sync false : Disable data sync
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_CFG_DT_SYNC
Example
Bool arg = true;
CSL_aif2EnRxTraceDataSync (hAif2, (void *)&arg);
| static void CSL_aif2ForceTmFlush | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2ForceTmFlush
Description
This function force flush TM FIFO
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
Bool true
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_CTRL_TM_FLUSH
Example
Bool arg = TRUE;
hAif2->arg_link = LINK0;
CSL_aif2ForceTmFlush (hAif2, arg);
| static void CSL_aif2ForceTmIdle | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2ForceTmIdle
Description
This function force set TM IDLE state
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
Bool true
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_CTRL_TM_IDLE
Example
Bool arg = TRUE;
hAif2->arg_link = LINK0;
CSL_aif2ForceTmIdle (hAif2, arg);
| static void CSL_aif2ForceTmReSync | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2ForceTmReSync
Description
This function force set TM RESYNC state
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
Bool true
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_CTRL_TM_RESYNC
Example
Bool arg = TRUE;
hAif2->arg_link = LINK0;
CSL_aif2ForceTmReSync (hAif2, arg);
| static void CSL_aif2InDbChannelSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2DbChannel | channel_setup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbChannelSetup
Description
Setup Ingress DB channel to add or remove channel dynamically (argument type: CSL_Aif2DbChannel *)
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2DbChannel aif2 Db channel setup structure
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_PTR_CH_BASE_ADDR,AIF2_DB_IDB_PTR_CH_BUF_DEPTH, AIF2_DB_IDB_CFG_CH_DAT_SWAP, AIF2_DB_IDB_CFG_CH_IQ_ORDER, AIF2_DB_IDB_CFG_CH_PS_EN, AIF2_DB_IDB_CFG_CH_PKT_TYPE Example
CSL_Aif2DbChannel newChannel;
newChannel.ChannelNum = 3;
........................................
newChannel.PacketType = 0;
CSL_aif2InDbChannelSetup(hAif2, newChannel);
| static void CSL_aif2InDbChEnable | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 * | channel | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbChEnable
Description
Enable or Disable Ingress DB channel to add or remove channel dynamically
Arguments
hAif2 Handle to the aif2 instance
Uint32* arg[0] ~ arg[3] : bit 0 ~ 127 for all channels
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_CH_EN_EN
Example
Uint32 InDbChannel[4];
InDbChannel[0] = 0x00000001;//channel 31 ~ 0
InDbChannel[1] = 0x0.... //channel 63 ~ 32
InDbChannel[2] = 0x0.... //channel 95 ~ 64
InDbChannel[3] = 0x0.... //channel 127 ~ 96
CSL_aif2InDbChEnable(hAif2, &InDbChannel[0]);
| static void CSL_aif2InDbDebugDataSetup | ( | CSL_Aif2Handle | hAif2, | |
| Uint32 * | debug_data | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbDebugDataSetup
Description
Debug data written to bits 128:0 of Ingress DB RAM
Arguments
hAif2 Handle to the aif2 instance
*Uint32 128 bit Debug data
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_DEBUG_D0_DATA,AIF2_DB_IDB_DEBUG_D1_DATA, AIF2_DB_IDB_DEBUG_D2_DATA,AIF2_DB_IDB_DEBUG_D3_DATA
Example
Uint32 DebugData[4];
DebugData[0] = 0x.....;
DebugData[1] = 0x.....;
DebugData[2] = 0x.....;
DebugData[3] = 0x.....;
CSL_aif2InDbDebugDataSetup(hAif2, &DebugData[0]);
| static void CSL_aif2InDbDebugOffsetAddr | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 * | offset_addr | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbDebugOffsetAddr
Description
Set write and read Address(channel number) used to access write or read Offset RAM for DB Debug (getting debug ram offset could be useful function for sw developer) Real Offset value of DB debug Ram could be obtained using CSL_aif2InDbDebugGetOffsetData() function.
Arguments
hAif2 Handle to the aif2 instance
Uint8* arg[0] : write offset address(channel num), arg[1] : read offset address(channel num)
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open(), CSL_aif2InDbDebugDataSetup(), CSL_aif2InDbDebugSideDataSetup(), CSL_aif2InDbEnDisDebug(), CSL_aif2InDbDebugWrite()
Post Condition
None
Writes
AIF2_DB_IDB_DEBUG_OFS_WADDR, AIF2_DB_IDB_DEBUG_OFS_RADDR
Example
Uint8 debug_addr[2];
debug_addr[0] = write_address; //0~ 127
debug_addr[1] = read_address; //0~ 127
CSL_aif2InDbDebugOffsetAddr(hAif2, &debug_addr[0]);
| static void CSL_aif2InDbDebugSideDataSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2DbSideData | side_data | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbDebugSideDataSetup
Description
Ingress DB debug side band data setup
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2DbSideData Side data structure for debug
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_DEBUG_SBND_DIO_WR_EN,AIF2_DB_IDB_DEBUG_SBND_FIFO_WR_EN, AIF2_DB_IDB_DEBUG_SBND_SOP,AIF2_DB_IDB_DEBUG_SBND_EOP,AIF2_DB_IDB_DEBUG_SBND_CH_ID, AIF2_DB_IDB_DEBUG_SBND_DIO_ADDR,AIF2_DB_IDB_DEBUG_SBND_XCNT, AIF2_DB_IDB_DEBUG_SBND_SYMBOL
Example
CSL_Aif2DbSideData SideData;
............
CSL_aif2InDbDebugSideDataSetup(hAif2, SideData);
| static void CSL_aif2InDbDebugWrite | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbDebugWrite
Description
Writes the data in the following registers into the Ingress DB and sideband RAMS (for customer debug purpose only) DB_IDB_DEBUG_D0, DB_IDB_DEBUG_D1, DB_IDB_DEBUG_D2, DB_IDB_DEBUG_D3, DB_IDB_DEBUG_SBDN
Arguments
hAif2 Handle to the aif2 instance
Bool True : Write data and side data and it will be transferred to Egress Debug side
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open(), CSL_aif2InDbDebugDataSetup(), CSL_aif2InDbDebugSideDataSetup(), CSL_aif2InDbEnDisDebug()
Post Condition
None
Writes
AIF2_DB_IDB_DEBUG_DB_WR_DONT_CARE,
Example
Bool arg = true;
CSL_aif2InDbDebugWrite(hAif2, arg);
| static void CSL_aif2InDbEnDisDebug | ( | CSL_Aif2Handle | hAif2, | |
| Bool | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2InDbEnDisDebug
Description
Enables Ingress DB Debug mode
Arguments
hAif2 Handle to the aif2 instance
Bool true : Debug on false : Debug off
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_CFG_IDB_DEBUG_EN
Example
Bool arg = true;
CSL_aif2InDbEnDisDebug (hAif2, arg);
| static void CSL_aif2PdChConfigDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PdChannelConfig | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PdChConfigDynamicSetup
Description
Dynamic configuration of PD channel config registers
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PdChannelConfig
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PD_ROUTE_ROUTE_TS,AIF2_PD_ROUTE_ROUTE_TYPE,AIF2_PD_ROUTE_ROUTE_ADR, AIF2_PD_ROUTE_ROUTE_LK,AIF2_PD_ROUTE_ROUTE_MASK,AIF2_PD_DMACHAN_CHAN_EN, AIF2_PD_DMACHAN_DATA_FORMAT,AIF2_PD_DMACHAN_A_AXC_OFFSET,AIF2_PD_DMACHAN_B_TS_WDOG_EN, AIF2_PD_DMACHAN_B_GSM_UL,AIF2_PD_DMACHAN_B_FRM_GRP,AIF2_PD_DMACHAN_B_DIO_OFFSET, AIF2_PD_DMACHAN_B_TDD_EN,AIF2_PD_DMACHAN_C_TDD_EN,AIF2_PD_DMACHAN_D_TDD_EN, AIF2_PD_DMACHAN_E_TDD_EN,AIF2_PD_DMACHAN_F_TDD_EN Example
CSL_Aif2PdChannelConfig arg;
arg. DbmX= 3;
..........
CSL_aif2PdChConfigDynamicSetup (hAif2, arg);
| static void CSL_aif2PdCpriCwLutDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CpriCwLut | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PdCpriCwLutDynamicSetup
Description
Dynamic configuration of PD CPRI Control word lut register.
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
CSL_Aif2CpriCwLut
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PD_CW_LUT_CW_CHAN, AIF2_PD_CW_LUT_CW_EN
Example
CSL_Aif2CpriCwLut arg;
arg.ChannelNum = 2; //CW channel 0 ~ 255
arg.CpriCwChannel = 1;
arg.bEnableCpriCw = true;
hAif2->arg_link = LINK0;
CSL_aif2PdCpriCwLutDynamicSetup (hAif2, arg);
| static void CSL_aif2PdCpriIdLutDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PdCpriIdLut | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PdCpriIdLutDynamicSetup
Description
Dynamic configuration of PD CPRI id lut register.
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
CSL_Aif2PdCpriIdLut
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PD_CPRI_ID_LUT_CPRI_DMACHAN,AIF2_PD_CPRI_ID_LUT_CPRI_X_EN, AIF2_PD_CPRI_ID_LUT_CPRI_PKT_EN,AIF2_PD_CPRI_ID_LUT_CPRI_8WD_OFSET
Example
CSL_Aif2PdCpriIdLut arg;
arg.ChannelNum = 8; //add channel 8
arg.CpriDmaCh = 3;
..........
hAif2->arg_link = LINK0;
CSL_aif2PdCpriIdLutDynamicSetup (hAif2, arg);
| static void CSL_aif2PdLinkDbmDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2DualBitMap | dbm | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PdLinkDbmDynamicSetup
Description
Dynamic configuration of PD Link DBMR
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
CSL_Aif2DualBitMap
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PD_DBM_DBM_X,AIF2_PD_DBM_DBM_XBUBBLE,AIF2_PD_DBM_DBM_1MULT, AIF2_PD_DBM_DBM_1SIZE,AIF2_PD_DBM_DBM_2SIZE,AIF2_PD_DBM_1MAP_DBM_1MAP, AIF2_PD_DBM_2MAP_DBM_2MAP Example
CSL_Aif2DualBitMap dbm;
dbm. DbmX= 3;
..........
hAif2->arg_link = LINK0;
CSL_aif2PdLinkDbmDynamicSetup (hAif2, dbm);
| static void CSL_aif2PeChConfigDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PeChannelConfig | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeChConfigDynamicSetup
Description
Dynamic configuration of PE channel config registers
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PeChannelConfig
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_DMACHAN_EN_CH_EN,AIF2_PE_DMA0CHAN_CRC_EN,AIF2_PE_DMA0CHAN_FRM_TC, AIF2_PE_DMA0CHAN_RT_CTL,AIF2_PE_DMA0CHAN_CRC_TYPE,AIF2_PE_DMA0CHAN_ETHERNET,AIF2_PE_DMA0CHAN_CRC_HDR, AIF2_PE_IN_FIFO_MF_WMARK,AIF2_PE_IN_FIFO_MF_FULL_LEV, AIF2_PE_IN_FIFO_SYNC_SYM,AIF2_PE_AXC_OFFSET_AXC_OFFSET Example
CSL_Aif2PeChannelConfig arg;
arg.ChannelNum = 1;
........................
CSL_aif2PeChConfigDynamicSetup (hAif2, arg);
| static void CSL_aif2PeChRuleLutDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PeChRuleLut | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeChRuleLutDynamicSetup
Description
Dynamic configuration of PE channel rule LUT config registers
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PeChRuleLut
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_RULE_CHANLUT0_CHANINDEX,AIF2_PE_RULE_CHANLUT0_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT0_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT1_CHANINDEX,AIF2_PE_RULE_CHANLUT1_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT1_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT2_CHANINDEX,AIF2_PE_RULE_CHANLUT2_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT2_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT3_CHANINDEX,AIF2_PE_RULE_CHANLUT3_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT3_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT4_CHANINDEX,AIF2_PE_RULE_CHANLUT4_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT4_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT5_CHANINDEX,AIF2_PE_RULE_CHANLUT5_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT5_CPRI_PKT_EN; AIF2_PE_RULE_CHANLUT6_CHANINDEX,AIF2_PE_RULE_CHANLUT6_CHANINDEX_EN; AIF2_PE_RULE_CHANLUT7_CHANINDEX,AIF2_PE_RULE_CHANLUT7_CHANINDEX_EN
Example
CSL_Aif2PeChRuleLut arg;
arg.RuleNum = 64; //0 ~ 511
arg.LutNum = 3: //0 ~ 7
........................
CSL_aif2PeChRuleLutDynamicSetup (hAif2, arg);
| static void CSL_aif2PeCpriCwLutDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CpriCwLut | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeCpriCwLutDynamicSetup
Description
Dynamic configuration of PE CPRI Control word lut register.
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
CSL_Aif2CpriCwLut
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_CPRI_CW_LUT_CW_CHAN, AIF2_PE_CPRI_CW_LUT_CW_EN
Example
CSL_Aif2CpriCwLut arg;
arg.ChannelNum = 2; //CW channel 0 ~ 255
arg.CpriCwChannel = 1;
arg.bEnableCpriCw = true;
hAif2->arg_link = LINK0;
CSL_aif2PeCpriCwLutDynamicSetup (hAif2, arg);
| static void CSL_aif2PeDbmrDynamicSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PeDbmr | dbm | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeDbmrDynamicSetup
Description
Dynamic configuration of PE Link DBMR for CPRI and 64 DBMR for OBSAI
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PeDbmr
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_CPRI_DBM_CPRI_DBM_X,AIF2_PE_CPRI_DBM_CPRI_DBM_XBUBBLE,AIF2_PE_CPRI_DBM_CPRI_DBM_1MULT, AIF2_PE_CPRI_DBM_CPRI_DBM_1SIZE,AIF2_PE_CPRI_DBM_CPRI_DBM_2SIZE,AIF2_PE_CPRIDBM_1MAP_CPRI_DBM_1MAP, AIF2_PE_CPRIDBM_2MAP_CPRI_DBM_2MAP;
AIF2_PE_OBSAI_DBM_DBM_X,AIF2_PE_OBSAI_DBM_DBM_1MULT,AIF2_PE_OBSAI_DBM_DBM_1SIZE, AIF2_PE_OBSAI_DBM_DBM_2SIZE,AIF2_PE_DBM_MAP_DBM_BIT_MAP
Example
CSL_Aif2PeDbmr dbm;
dbm.isCpri = TRUE or FALSE; // true for CPRI and false for OBSAI
dbm.CpriLinkNum = LINK0; // CPRI only
dbm.RuleNum = 0; //OBSAI only
........................
CSL_aif2PeDbmrDynamicSetup (hAif2, dbm);
| static void CSL_aif2PeModuloTxRuleSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PeModuloRule | mrule | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeModuloTxRuleSetup
Description
Dynamic configuration of PE Modulo rule
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PeModuloRule
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_MODTXRULE_RULE_MOD,AIF2_PE_MODTXRULE_RULE_INDEX, AIF2_PE_MODTXRULE_RULE_LK,AIF2_PE_MODTXRULE_RULE_CTL_MSG,AIF2_PE_MODTXRULE_RULE_EN,
Example
CSL_Aif2PeModuloRule mrule;
mrule.RuleNum = 1;
........................
CSL_aif2PeModuloTxRuleSetup (hAif2, mrule);
| static void CSL_aif2PeObsaiHeaderSetup | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2PeObsaiHeader | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2PeObsaiHeaderSetup
Description
Dynamic configuration of PE OBSAI header register.
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2PeObsaiHeader
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_OBSAI_HDR_OBSAI_TS_ADR,AIF2_PE_OBSAI_HDR_OBSAI_TYPE,AIF2_PE_OBSAI_HDR_OBSAI_ADR, AIF2_PE_OBSAI_HDR_OBSAI_TS_MASK,AIF2_PE_OBSAI_HDR_OBSAI_TS_FRMT
Example
CSL_Aif2PeObsaiHeader arg;
arg.ChannelNum = 8; //add channel 8
........
CSL_aif2PeObsaiHeaderSetup (hAif2, arg);
| static void CSL_aif2RmLinkForceRxState | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2RmForceSyncState | arg | |||
| ) | [inline, static] |
============================================================================
CSL_aif2RmLinkForceRxState
Description
This function force set RM sync status
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
CSL_Aif2RmForceSyncState
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_RM_LK_CFG0_FORCE_RX_STATE
Example
Bool arg = CSL_AIF2_RM_FORCE_ST0;
hAif2->arg_link = LINK0;
CSL_aif2RmLinkForceRxState (hAif2, arg);
| static void CSL_aif2SdLinkRxTestPattern | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2SdTestPattern | test_pattern | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SdLinkRxTestPattern
Description
This function selects or disables SD Rx test pattern
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2SdTestPattern test patten
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_RX_R2_CFG_RXTEST_PATTERN
Example
CSL_Aif2SdTestPattern test = CSL_AIF2_SD_ALTERNATING_0_1;
hAif2->arg_link = 0;
CSL_aif2SdLinkRxTestPattern (hAif2, test);
| static void CSL_aif2SdLinkTxTestPattern | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2SdTestPattern | test_pattern | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SdLinkTxTestPattern
Description
This function selects or disables SD Tx test pattern
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2SdTestPattern test patten
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_TX_R1_CFG_TXTEST_PATTERN
Example
CSL_Aif2SdTestPattern test = CSL_AIF2_SD_ALTERNATING_0_1;
hAif2->arg_link = 0;
CSL_aif2SdLinkTxTestPattern (hAif2, test);
| static void CSL_aif2TmLinkL1InbandSet | ( | CSL_Aif2Handle | hAif2, | |
| Uint8 | bitmask | |||
| ) | [inline, static] |
============================================================================
CSL_aif2TmLinkL1InbandSet
Description
TM L1 Inband Control Signal Set for app testing
Arguments
hAif2 Handle to the aif2 instance (should use arg_link for link selection)
Uint8 5 bitmap for control signal
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_L1_CFG_L1_INBAND_CFG
Example
Uint8 bitmask = 0x1; //set bit 0 RESET
hAif2->arg_link = LINK0;
CSL_aif2TmLinkL1InbandSet (hAif2, bitmask);
| static void CSL_aif2VcEmuControl | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2VcEmu | Emu | |||
| ) | [inline, static] |
============================================================================
CSL_aif2VcEmuControl
Description
This function enables or disables EMU control fields
Arguments
hAif2 Handle to the aif2 instance
CSL_Aif2VcEmu Free, Soft, RtSel
Return Value None
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AIF2_EMU_FREERUN,AIF2_AIF2_EMU_SOFT,AIF2_AIF2_EMU_RT_SEL
Example
CSL_Aif2VcEmu Emu;
Emu.Freerun = FALSE;
Emu.Soft = TRUE;
Emu.RtSel = TRUE;
CSL_aif2VcEmuControl (hAif2, Emu);