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#include <ti/csl/csl_aif2.h>
#include <ti/csl/csl_aif2HwControlAux.h>
============================================================================
| static CSL_Status CSL_aif2SetupAdCommonRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAdCommonRegs
Description
AIF2 AD common setup
Arguments
commonSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_ISCH_CFG_FAIL_MODE,AIF2_AD_ISCH_CFG_PRI, AIF2_AD_ESCH_CFG_TXQ_QMGR,AIF2_AD_ESCH_CFG_TXQ_QNUM,AIF2_AD_ESCH_CFG_PRI, AIF2_AD_DIO_I_GLOBAL_EN_SET_DONT_CARE,AIF2_AD_DIO_E_GLOBAL_EN_SET_DONT_CARE, AIF2_AD_ISCH_GLOBAL_EN_SET_DONT_CARE,AIF2_AD_ESCH_GLOBAL_EN_SET_DONT_CARE Example
CSL_aif2SetupAdCommonRegs (commonSetup, hAif2);
| static CSL_Status CSL_aif2SetupAdEDioRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAdEDioRegs
Description
AIF2 AD Direct IO setup
Arguments
commonSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_E_TABLE_SEL_BCN_TABLE_SEL, AIF2_AD_DIO_E_TABLE_LOOP_CFG_NUM_QW,AIF2_AD_DIO_E_TABLE_LOOP_CFG_NUM_AXC, AIF2_AD_DIO_E_DMA_CFG0_DMA_BRST_LN,AIF2_AD_DIO_E_DMA_CFG0_RSA_EN,AIF2_AD_DIO_E_DMA_CFG0_DMA_CH_EN, AIF2_AD_DIO_E_DMA_CFG0_DMA_NUM_BLKS, AIF2_AD_DIO_E_DMA_CFG1_DMA_BASE_ADDR, AIF2_AD_DIO_E_DMA_CFG2_DMA_BRST_ADDR_STRIDE,AIF2_AD_DIO_E_DMA_CFG2_DMA_BLK_ADDR_STRIDE, AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN0,AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN1, AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN2,AIF2_AD_DIO_E_BCN_TABLE0_ROW0_DBCN3, AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN4,AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN5, AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN6,AIF2_AD_DIO_E_BCN_TABLE0_ROW1_DBCN7, AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN8,AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN9, AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN10,AIF2_AD_DIO_E_BCN_TABLE0_ROW2_DBCN11, AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN12,AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN13, AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN14,AIF2_AD_DIO_E_BCN_TABLE0_ROW3_DBCN15, AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN16,AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN17, AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN18,AIF2_AD_DIO_E_BCN_TABLE0_ROW4_DBCN19, AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN20,AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN21, AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN22,AIF2_AD_DIO_E_BCN_TABLE0_ROW5_DBCN23, AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN24,AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN25, AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN26,AIF2_AD_DIO_E_BCN_TABLE0_ROW6_DBCN27, AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN28,AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN29, AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN30,AIF2_AD_DIO_E_BCN_TABLE0_ROW7_DBCN31, AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN32,AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN33, AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN34,AIF2_AD_DIO_E_BCN_TABLE0_ROW8_DBCN35, AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN36,AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN37, AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN38,AIF2_AD_DIO_E_BCN_TABLE0_ROW9_DBCN39, AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN40,AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN41, AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN42,AIF2_AD_DIO_E_BCN_TABLE0_ROW10_DBCN43, AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN44,AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN45, AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN46,AIF2_AD_DIO_E_BCN_TABLE0_ROW11_DBCN47, AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN48,AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN49, AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN50,AIF2_AD_DIO_E_BCN_TABLE0_ROW12_DBCN51, AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN52,AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN53, AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN54,AIF2_AD_DIO_E_BCN_TABLE0_ROW13_DBCN55, AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN56,AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN57, AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN58,AIF2_AD_DIO_E_BCN_TABLE0_ROW14_DBCN59, AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN60,AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN61, AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN62,AIF2_AD_DIO_E_BCN_TABLE0_ROW15_DBCN63;
AIF2_AD_DIO_E_TABLE_SEL_BCN_TABLE_SEL, AIF2_AD_DIO_E_TABLE_LOOP_CFG_NUM_QW,AIF2_AD_DIO_E_TABLE_LOOP_CFG_NUM_AXC, AIF2_AD_DIO_E_DMA_CFG0_DMA_BRST_LN,AIF2_AD_DIO_E_DMA_CFG0_RSA_EN,AIF2_AD_DIO_E_DMA_CFG0_DMA_CH_EN, AIF2_AD_DIO_E_DMA_CFG0_DMA_NUM_BLKS, AIF2_AD_DIO_E_DMA_CFG1_DMA_BASE_ADDR, AIF2_AD_DIO_E_DMA_CFG2_DMA_BRST_ADDR_STRIDE,AIF2_AD_DIO_E_DMA_CFG2_DMA_BLK_ADDR_STRIDE, AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN0,AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN1, AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN2,AIF2_AD_DIO_E_BCN_TABLE1_ROW0_DBCN3, AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN4,AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN5, AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN6,AIF2_AD_DIO_E_BCN_TABLE1_ROW1_DBCN7, AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN8,AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN9, AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN10,AIF2_AD_DIO_E_BCN_TABLE1_ROW2_DBCN11, AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN12,AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN13, AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN14,AIF2_AD_DIO_E_BCN_TABLE1_ROW3_DBCN15, AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN16,AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN17, AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN18,AIF2_AD_DIO_E_BCN_TABLE1_ROW4_DBCN19, AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN20,AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN21, AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN22,AIF2_AD_DIO_E_BCN_TABLE1_ROW5_DBCN23, AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN24,AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN25, AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN26,AIF2_AD_DIO_E_BCN_TABLE1_ROW6_DBCN27, AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN28,AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN29, AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN30,AIF2_AD_DIO_E_BCN_TABLE1_ROW7_DBCN31, AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN32,AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN33, AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN34,AIF2_AD_DIO_E_BCN_TABLE1_ROW8_DBCN35, AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN36,AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN37, AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN38,AIF2_AD_DIO_E_BCN_TABLE1_ROW9_DBCN39, AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN40,AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN41, AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN42,AIF2_AD_DIO_E_BCN_TABLE1_ROW10_DBCN43, AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN44,AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN45, AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN46,AIF2_AD_DIO_E_BCN_TABLE1_ROW11_DBCN47, AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN48,AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN49, AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN50,AIF2_AD_DIO_E_BCN_TABLE1_ROW12_DBCN51, AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN52,AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN53, AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN54,AIF2_AD_DIO_E_BCN_TABLE1_ROW13_DBCN55, AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN56,AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN57, AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN58,AIF2_AD_DIO_E_BCN_TABLE1_ROW14_DBCN59, AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN60,AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN61, AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN62,AIF2_AD_DIO_E_BCN_TABLE1_ROW15_DBCN63;
Example
CSL_aif2SetupAdEDioRegs (commonSetup, hAif2);
| static CSL_Status CSL_aif2SetupAdInDioRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAdInDioRegs
Description
AIF2 AD Direct IO setup
Arguments
commonSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AD_DIO_I_TABLE_SEL_BCN_TABLE_SEL, AIF2_AD_DIO_I_TABLE_LOOP_CFG_NUM_QW,AIF2_AD_DIO_I_TABLE_LOOP_CFG_NUM_AXC, AIF2_AD_DIO_I_DMA_CFG0_DMA_BRST_LN,AIF2_AD_DIO_I_DMA_CFG0_DMA_CH,AIF2_AD_DIO_I_DMA_CFG0_DMA_NUM_BLKS, AIF2_AD_DIO_I_DMA_CFG1_DMA_BASE_ADDR, AIF2_AD_DIO_I_DMA_CFG2_DMA_BRST_ADDR_STRIDE,AIF2_AD_DIO_I_DMA_CFG2_DMA_BLK_ADDR_STRIDE, AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN0,AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN1, AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN2,AIF2_AD_DIO_I_BCN_TABLE0_ROW0_DBCN3, AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN4,AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN5, AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN6,AIF2_AD_DIO_I_BCN_TABLE0_ROW1_DBCN7, AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN8,AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN9, AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN10,AIF2_AD_DIO_I_BCN_TABLE0_ROW2_DBCN11, AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN12,AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN13, AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN14,AIF2_AD_DIO_I_BCN_TABLE0_ROW3_DBCN15, AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN16,AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN17, AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN18,AIF2_AD_DIO_I_BCN_TABLE0_ROW4_DBCN19, AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN20,AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN21, AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN22,AIF2_AD_DIO_I_BCN_TABLE0_ROW5_DBCN23, AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN24,AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN25, AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN26,AIF2_AD_DIO_I_BCN_TABLE0_ROW6_DBCN27, AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN28,AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN29, AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN30,AIF2_AD_DIO_I_BCN_TABLE0_ROW7_DBCN31, AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN32,AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN33, AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN34,AIF2_AD_DIO_I_BCN_TABLE0_ROW8_DBCN35, AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN36,AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN37, AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN38,AIF2_AD_DIO_I_BCN_TABLE0_ROW9_DBCN39, AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN40,AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN41, AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN42,AIF2_AD_DIO_I_BCN_TABLE0_ROW10_DBCN43, AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN44,AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN45, AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN46,AIF2_AD_DIO_I_BCN_TABLE0_ROW11_DBCN47, AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN48,AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN49, AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN50,AIF2_AD_DIO_I_BCN_TABLE0_ROW12_DBCN51, AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN52,AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN53, AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN54,AIF2_AD_DIO_I_BCN_TABLE0_ROW13_DBCN55, AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN56,AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN57, AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN58,AIF2_AD_DIO_I_BCN_TABLE0_ROW14_DBCN59, AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN60,AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN61, AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN62,AIF2_AD_DIO_I_BCN_TABLE0_ROW15_DBCN63;
AIF2_AD_DIO_I_TABLE_SEL_BCN_TABLE_SEL, AIF2_AD_DIO_I_TABLE_LOOP_CFG_NUM_QW,AIF2_AD_DIO_I_TABLE_LOOP_CFG_NUM_AXC, AIF2_AD_DIO_I_DMA_CFG0_DMA_BRST_LN,AIF2_AD_DIO_I_DMA_CFG0_DMA_CH,AIF2_AD_DIO_I_DMA_CFG0_DMA_NUM_BLKS, AIF2_AD_DIO_I_DMA_CFG1_DMA_BASE_ADDR, AIF2_AD_DIO_I_DMA_CFG2_DMA_BRST_ADDR_STRIDE,AIF2_AD_DIO_I_DMA_CFG2_DMA_BLK_ADDR_STRIDE, AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN0,AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN1, AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN2,AIF2_AD_DIO_I_BCN_TABLE1_ROW0_DBCN3, AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN4,AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN5, AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN6,AIF2_AD_DIO_I_BCN_TABLE1_ROW1_DBCN7, AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN8,AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN9, AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN10,AIF2_AD_DIO_I_BCN_TABLE1_ROW2_DBCN11, AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN12,AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN13, AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN14,AIF2_AD_DIO_I_BCN_TABLE1_ROW3_DBCN15, AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN16,AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN17, AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN18,AIF2_AD_DIO_I_BCN_TABLE1_ROW4_DBCN19, AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN20,AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN21, AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN22,AIF2_AD_DIO_I_BCN_TABLE1_ROW5_DBCN23, AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN24,AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN25, AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN26,AIF2_AD_DIO_I_BCN_TABLE1_ROW6_DBCN27, AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN28,AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN29, AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN30,AIF2_AD_DIO_I_BCN_TABLE1_ROW7_DBCN31, AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN32,AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN33, AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN34,AIF2_AD_DIO_I_BCN_TABLE1_ROW8_DBCN35, AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN36,AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN37, AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN38,AIF2_AD_DIO_I_BCN_TABLE1_ROW9_DBCN39, AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN40,AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN41, AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN42,AIF2_AD_DIO_I_BCN_TABLE1_ROW10_DBCN43, AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN44,AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN45, AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN46,AIF2_AD_DIO_I_BCN_TABLE1_ROW11_DBCN47, AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN48,AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN49, AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN50,AIF2_AD_DIO_I_BCN_TABLE1_ROW12_DBCN51, AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN52,AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN53, AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN54,AIF2_AD_DIO_I_BCN_TABLE1_ROW13_DBCN55, AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN56,AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN57, AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN58,AIF2_AD_DIO_I_BCN_TABLE1_ROW14_DBCN59, AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN60,AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN61, AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN62,AIF2_AD_DIO_I_BCN_TABLE1_ROW15_DBCN63; Example
CSL_aif2SetupAdInDioRegs (commonSetup, hAif2);
| static CSL_Status CSL_aif2SetupAtCommonRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAtCommonRegs
Description
AIF2 AT common setup
Arguments
commonSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_CONTROL1_PHYSYNCSEL,AIF2_AT_CONTROL1_RADSYNCSEL,AIF2_AT_CONTROL1_RP1MODE,AIF2_AT_CONTROL1_AUTORESYNC, AIF2_AT_CONTROL1_CRCUSE,AIF2_AT_CONTROL1_CRCFLIP,AIF2_AT_CONTROL1_CRCINIT_ONES,AIF2_AT_CONTROL1_CRCINVERT, AIF2_AT_CONTROL1_SYNC_SAMPL_WINDOW,AIF2_AT_CONTROL1_RP1RADT_FRAME_LOAD,AIF2_AT_CONTROL1_RP1PHYT_FRAME_LOAD, AIF2_AT_PHYT_CMP_RADSYNC_RP1RAD_TYPE_SELECT,AIF2_AT_RP1_TYPE_RP1RAD_TYPE_SELECT, AIF2_AT_PHYT_INIT_LSBS_PHYTCLOCK_COUNT_INIT;AIF2_AT_PHYT_INIT_MID_PHYTFRAME_INIT_LSBS, AIF2_AT_PHYT_INIT_MSBS_PHYTFRAME_INIT_MSBS, AIF2_AT_PHYT_TC_LSBS_PHYTCLOCK_COUNTER_TC,AIF2_AT_PHYT_FRAME_TC_LSBS_PHYTFRAME_TC_LSBS, AIF2_AT_PHYT_FRAME_TC_MSBS_PHYTFRAME_TC_MSBS,AIF2_AT_RADT_WCDMA_DIV_TERMINALCOUNT, AIF2_AT_RADT_INIT_LSBS_RADTCLOCK_COUNT_INIT,AIF2_AT_RADT_INIT_LSBS_RADTSYMBOL_COUNT_INIT, AIF2_AT_RADT_INIT_MID_RADTFRAME_INIT_LSBS,AIF2_AT_RADT_INIT_MSBS_RADTFRAME_INIT_MSBS, AIF2_AT_ULRADT_INIT_LSBS_ULRADTCLOCK_COUNT_INIT,AIF2_AT_ULRADT_INIT_LSBS_ULRADTSYMBOL_COUNT_INIT,AIF2_AT_ULRADT_INIT_LSBS_ULFCB_MINUSONE, AIF2_AT_ULRADT_INIT_MID_RADTFRAME_INIT_LSBS,AIF2_AT_ULRADT_INIT_MSBS_RADTFRAME_INIT_MSBS, AIF2_AT_DLRADT_INIT_LSBS_DLRADTCLOCK_COUNT_INIT,AIF2_AT_DLRADT_INIT_LSBS_DLRADTSYMBOL_COUNT_INIT,AIF2_AT_DLRADT_INIT_LSBS_DLFCB_MINUSONE, AIF2_AT_DLRADT_INIT_MID_RADTFRAME_INIT_LSBS,AIF2_AT_DLRADT_INIT_MSBS_RADTFRAME_INIT_MSBS, AIF2_AT_RADT_SYMB_LUT_INDEX_TC_LUTINDEX_TC,AIF2_AT_RADT_SYMB_LUT_INDEX_TC_SYMBOLTC, AIF2_AT_RADT_FRAME_TC_LSBS_RADTFRAME_TC_LSBS,AIF2_AT_RADT_FRAME_TC_MSBS_RADTFRAME_TC_MSBS, AIF2_AT_RADT_SYM_LUT_RAM_RADT_CLOCK_TC
Example
CSL_aif2SetupAtCommonRegs (commonSetup, hAif2);
| static CSL_Status CSL_aif2SetupAtEventRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAtEventRegs
Description
AIF2 AT Internal and External Event setup
Arguments
commonSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_EVENT_OFFSET_EVENTINDEX,AIF2_AT_EVENT_OFFSET_STROBESELECT, AIF2_AT_EVENT_MOD_TC_EVENTMODULO,AIF2_AT_EVENT_MASK_LSBS_EVENTMASK_LSBS,AIF2_AT_EVENT_MASK_MSBS_EVENTMASK_MSBS, AIF2_AT_EVT_ENABLE_EVENTENABLE, AIF2_AT_AD_INGR_EVENT_OFFSET_EVENTINDEX,AIF2_AT_AD_INGR_EVENT_OFFSET_STROBESELECT, AIF2_AT_AD_INGR_EVENT_MOD_TC_EVENTMODULO, AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE, AIF2_AT_AD_EGR_EVENT_OFFSET_EVENTINDEX,AIF2_AT_AD_EGR_EVENT_OFFSET_STROBESELECT, AIF2_AT_AD_EGR_EVENT_MOD_TC_EVENTMODULO, AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Reads
AIF2_AT_EVT_ENABLE_EVENTENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_ADINGR_EVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_ADEGR_EVENT_ENABLE
Example
CSL_aif2SetupAtEventRegs (commonSetup, hAif2);
| static CSL_Status CSL_aif2SetupAtLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupAtLinkRegs
Description
AIF2 Timer Link setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK0_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE; AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK1_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE; AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK2_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE; AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK3_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE; AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK4_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE; AIF2_AT_PIMAX_LK_PIMAX,AIF2_AT_PIMMIN_LK_PIMIN,AIF2_AT_TM_DELTA_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_TM_DELTA_EVENT_MOD_TC_EVENTMODULO = 0, AIF2_AT_PE_EVENT_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT_MOD_TC_EVENTMODULO = 0,AIF2_AT_PE_EVENT2_OFFSET_EVENTOFFSET, AIF2_AT_PE_EVENT2_MOD_TC_EVENTMODULO = 0,AIF2_AT_NEG_DELTA_LK5_DELTA, AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE;
Reads
AIF2_AT_INTERNAL_EVT_ENABLE_TMDELTA_EVENT_ENABLE,AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT_ENABLE, AIF2_AT_INTERNAL_EVT_ENABLE_PEEVENT2_ENABLE Example
CSL_aif2SetupAtLinkRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupEgrDbRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupEgrDbRegs
Description
AIF2 Egress Db setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_EDB_CFG_DIO_LEN,AIF2_DB_EDB_GLOBAL_EN_SET_DONT_CARE, AIF2_DB_EDB_CH_EN,AIF2_DB_EDB_CFG_PM_CTL, AIF2_DB_EDB_PTR_CH_BUF_DEPTH,AIF2_DB_EDB_PTR_CH_BASE_ADDR, AIF2_DB_EDB_CFG_CH_DAT_SWAP,AIF2_DB_EDB_CFG_CH_IQ_ORDER,AIF2_DB_EDB_CFG_CH_DIO_OFFSET Example
CSL_aif2SetupEgrDbRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupGlobalRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2GlobalSetup * | globalSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupGlobalRegs
Description
AIF2 Global setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_RM_CFG_SHORT_FRM_EN, AIF2_PD_GLOBAL_SHRT_FRM_MODE,AIF2_PE_GLOBAL_SHRT_FRM_MODE, AIF2_TM_FRM_MODE_FRM_MODE Example
CSL_aif2SetupGlobalRegs (aif2Setup, hAif2);
| static CSL_Status CSL_aif2SetupIngrDbRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupIngrDbRegs
Description
AIF2 ingress Db setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_IDB_CFG_DIO_LEN,AIF2_DB_IDB_GLOBAL_EN_SET_DONT_CARE, AIF2_DB_IDB_CH_EN, AIF2_DB_IDB_PTR_CH_BUF_DEPTH,AIF2_DB_IDB_PTR_CH_BASE_ADDR, AIF2_DB_IDB_CFG_CH_DAT_SWAP,AIF2_DB_IDB_CFG_CH_IQ_ORDER,AIF2_DB_IDB_CFG_CH_PS_EN,AIF2_DB_IDB_CFG_CH_PKT_TYPE Example
CSL_aif2SetupIngrDbRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupLinkRegs
Description
AIF2 Link common setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_CFG_OBSAI_CPRI, AIF2_RM_LK_CFG0_MODE_SEL,AIF2_RT_LK_CFG_OBSAI_CPRI,AIF2_PD_LINK_A_OBSAI_CPRI, AIF2_PE_LINK_OBSAI_CPRI,AIF2_CI_LK_CFG_OBSAI_CPRI,AIF2_CO_LK_CFG_OBSAI_CPRI,AIF2_SD_RX_R1_CFG_RXRATE, AIF2_TM_LK_CFG_LINKRATE,AIF2_RM_LK_CFG0_LINK_RATE,AIF2_RT_LK_CFG_LINK_RATE, AIF2_PD_LINK_B_CPRI_LK_RATE,AIF2_PE_LINK_LK_RATE,AIF2_CI_LK_CFG_LINK_RATE,AIF2_CO_LK_CFG_LINK_RATE, AIF2_RT_LK_CFG_SAMPLE_WIDTH,AIF2_PD_LINK_B_CPRI_AXC_PACK,AIF2_CI_LK_CFG_SAMPLE_WIDTH,AIF2_CO_LK_CFG_SAMPLE_WIDTH
Example
CSL_aif2SetupLinkRegs (linkSetup, hAif2);
pointer to common link setup
Configuring the link Rate
Configuring the sample width
| static CSL_Status CSL_aif2SetupPdCommonRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupPdCommonRegs
Description
AIF2 Protocol decoder common setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_DB_PD_GLOBAL_EN_SET_DONT_CARE,AIF2_PD_GLOBAL_SHRT_FRM_MODE, AIF2_PD_GLOBAL_DIO_CPPI,AIF2_PD_GLOBAL_AXCOFFSET_WIN,AIF2_PD_DMA_TS_WDOG_CNT,AIF2_PD_DMA_WDOG_EOP_ADD, AIF2_PD_DMA_WDOG_EE_CTRL,AIF2_PD_RADT_TC_RADT_TC,AIF2_PD_FRM_TC_FRM_INDEX_TC,AIF2_PD_FRM_TC_FRM_INDEX_SC, AIF2_PD_FRM_TC_FRM_SYM_TC,AIF2_PD_ROUTE_ROUTE_TS,AIF2_PD_ROUTE_ROUTE_TYPE, AIF2_PD_ROUTE_ROUTE_ADR,AIF2_PD_ROUTE_ROUTE_LK,AIF2_PD_ROUTE_ROUTE_MASK, AIF2_PD_DMACHAN_CHAN_EN,AIF2_PD_DMACHAN_DATA_FORMAT,AIF2_PD_DMACHAN_A_AXC_OFFSET, AIF2_PD_DMACHAN_B_TS_WDOG_EN,AIF2_PD_DMACHAN_B_GSM_UL,AIF2_PD_DMACHAN_B_FRM_GRP, AIF2_PD_DMACHAN_B_DIO_OFFSET,AIF2_PD_DMACHAN_B_TDD_EN, AIF2_PD_DMACHAN_C_TDD_EN,AIF2_PD_DMACHAN_D_TDD_EN,AIF2_PD_DMACHAN_E_TDD_EN, AIF2_PD_DMACHAN_F_TDD_EN,AIF2_PD_FRM_MSG_TC_FRME_MSG_TC Example
CSL_aif2SetupPdCommonRegs (linkSetup, hAif2);
pointer to Protocol decoder link setup
| static CSL_Status CSL_aif2SetupPdLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupPdLinkRegs
Description
AIF2 Protocol decoder link setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PD_LINK_A_OBSAI_CPRI,AIF2_PD_LINK_A_ETHNET_STRIP,AIF2_PD_LINK_A_CRC8_POLY,AIF2_PD_LINK_A_CRC8_SEED,AIF2_PD_LINK_B_CPRI_LK_RATE, AIF2_PD_LINK_B_CPRI_AXC_PACK,AIF2_PD_LINK_B_CPRI_NULLDELM,AIF2_PD_LINK_B_PKT_DELIM_CH0,AIF2_PD_LINK_B_PKT_DELIM_CH1, AIF2_PD_LINK_B_PKT_DELIM_CH2,AIF2_PD_LINK_B_PKT_DELIM_CH3, AIF2_PD_PACK_MAP_PACK0_DMA_CH,AIF2_PD_PACK_MAP_PACK0_EN, AIF2_PD_PACK_MAP_PACK1_DMA_CH,AIF2_PD_PACK_MAP_PACK1_EN, AIF2_PD_PACK_MAP_PACK2_DMA_CH,AIF2_PD_PACK_MAP_PACK2_EN, AIF2_PD_PACK_MAP_PACK3_DMA_CH,AIF2_PD_PACK_MAP_PACK3_EN, AIF2_PD_CPRI_CRC_CRC0_TYPE,AIF2_PD_CPRI_CRC_CRC0_EN,AIF2_PD_CPRI_CRC_CRC1_TYPE,AIF2_PD_CPRI_CRC_CRC1_EN, AIF2_PD_CPRI_CRC_CRC2_TYPE,AIF2_PD_CPRI_CRC_CRC2_EN,AIF2_PD_CPRI_CRC_CRC3_TYPE, AIF2_PD_CPRI_CRC_CRC3_EN, AIF2_PD_DBM_DBM_X,AIF2_PD_DBM_DBM_XBUBBLE,AIF2_PD_DBM_DBM_1MULT,AIF2_PD_DBM_DBM_1SIZE, AIF2_PD_DBM_DBM_2SIZE,AIF2_PD_DBM_1MAP_DBM_1MAP,AIF2_PD_DBM_2MAP_DBM_2MAP, AIF2_PD_TYPE_LUT_TS_FORMAT,AIF2_PD_TYPE_LUT_CRC_TYPE,AIF2_PD_TYPE_LUT_CRC_EN,AIF2_PD_TYPE_LUT_OBSAI_PKT_EN, AIF2_PD_TYPE_LUT_ENET_STRIP,AIF2_PD_TYPE_LUT_CRC_HDR,AIF2_PD_CPRI_ID_LUT_CPRI_DMACHAN, AIF2_PD_CPRI_ID_LUT_CPRI_X_EN,AIF2_PD_CPRI_ID_LUT_CPRI_PKT_EN, AIF2_PD_CPRI_ID_LUT_CPRI_8WD_OFSET,AIF2_PD_CW_LUT_CW_CHAN, AIF2_PD_CW_LUT_CW_EN,AIF2_PD_LINK_A_LINK_EN Example
CSL_aif2SetupPdLinkRegs (linkSetup, hAif2);
pointer to Protocol decoder link setup
| static CSL_Status CSL_aif2SetupPeCommonRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupPeCommonRegs
Description
AIF2 PE common setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_GLOBAL_EN_SET_DONT_CARE,AIF2_PE_GLOBAL_TOKEN_PHASE,AIF2_PE_GLOBAL_ENET_HDR_SEL,AIF2_PE_GLOBAL_DIO_LEN,AIF2_PE_FRM_TC_FRM_INDEX_TC, AIF2_PE_FRM_TC_FRM_INDEX_SC,AIF2_PE_FRM_TC_FRM_SYM_TC,AIF2_PE_DMACHAN_EN_CH_EN, AIF2_PE_DMA0CHAN_CRC_EN,AIF2_PE_DMA0CHAN_FRM_TC,AIF2_PE_DMA0CHAN_RT_CTL, AIF2_PE_DMA0CHAN_CRC_TYPE,AIF2_PE_DMA0CHAN_ETHERNET,AIF2_PE_DMA0CHAN_CRC_HDR, AIF2_PE_IN_FIFO_MF_WMARK,AIF2_PE_IN_FIFO_MF_FULL_LEV,AIF2_PE_IN_FIFO_SYNC_SYM,AIF2_PE_AXC_OFFSET_AXC_OFFSET, AIF2_PE_FRM_MSG_TC_FRME_MSG_TC,AIF2_PE_MODTXRULE_RULE_MOD,AIF2_PE_MODTXRULE_RULE_INDEX,AIF2_PE_MODTXRULE_RULE_LK, AIF2_PE_MODTXRULE_RULE_CTL_MSG,AIF2_PE_MODTXRULE_RULE_EN,AIF2_PE_OBSAI_HDR_OBSAI_TS_ADR,AIF2_PE_OBSAI_HDR_OBSAI_TYPE, AIF2_PE_OBSAI_HDR_OBSAI_ADR,AIF2_PE_OBSAI_HDR_OBSAI_TS_MASK,AIF2_PE_OBSAI_HDR_OBSAI_TS_FRMT, AIF2_PE_OBSAI_HDR_OBSAI_PKT,AIF2_PE_OBSAI_HDR_BB_HOP, AIF2_PE_OBSAI_DBM_DBM_X,AIF2_PE_OBSAI_DBM_DBM_1MULT, AIF2_PE_OBSAI_DBM_DBM_1SIZE,AIF2_PE_OBSAI_DBM_DBM_2SIZE,AIF2_PE_DBM_MAP_DBM_BIT_MAP, AIF2_PE_RULE_CHANLUT0_CHANINDEX,AIF2_PE_RULE_CHANLUT0_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT0_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT1_CHANINDEX,AIF2_PE_RULE_CHANLUT1_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT1_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT2_CHANINDEX,AIF2_PE_RULE_CHANLUT2_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT2_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT3_CHANINDEX,AIF2_PE_RULE_CHANLUT3_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT3_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT4_CHANINDEX,AIF2_PE_RULE_CHANLUT4_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT4_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT5_CHANINDEX,AIF2_PE_RULE_CHANLUT5_CHANINDEX_EN,AIF2_PE_RULE_CHANLUT5_CPRI_PKT_EN, AIF2_PE_RULE_CHANLUT6_CHANINDEX,AIF2_PE_RULE_CHANLUT6_CHANINDEX_EN, AIF2_PE_RULE_CHANLUT7_CHANINDEX,AIF2_PE_RULE_CHANLUT7_CHANINDEX_EN Example
CSL_aif2SetupPeCommonRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupPeLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupPeLinkRegs
Description
AIF2 PE setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_PE_LINK_OBSAI_CPRI,AIF2_PE_LINK_LK_RATE,AIF2_PE_LINK_DIO_CPPI,AIF2_PE_LINK_TDD_AXC, AIF2_PE_LINK_OBSAIBUBBLE_BW,AIF2_PE_LINK_MEMFETCH_DELAY,AIF2_PE_CRC_CRC8_POLY,AIF2_PE_CRC_CRC8_SEED, AIF2_PE_CPRI_DBM_CPRI_DBM_X,AIF2_PE_CPRI_DBM_CPRI_DBM_XBUBBLE,AIF2_PE_CPRI_DBM_CPRI_DBM_1MULT, AIF2_PE_CPRI_DBM_CPRI_DBM_1SIZE,AIF2_PE_CPRI_DBM_CPRI_DBM_2SIZE, AIF2_PE_CPRIDBM_1MAP_CPRI_DBM_1MAP,AIF2_PE_CPRIDBM_2MAP_CPRI_DBM_2MAP, AIF2_PE_CPRI0_CPRI_AXC_PACK,AIF2_PE_CPRI0_CPRI_NULLDELM,AIF2_PE_CPRI0_PKT_DELIM_CH0, AIF2_PE_CPRI0_PKT_DELIM_CH1,AIF2_PE_CPRI0_PKT_DELIM_CH2,AIF2_PE_CPRI0_PKT_DELIM_CH3, AIF2_PE_CPRI1_CPRI_PKT0_CH,AIF2_PE_CPRI1_CPRI_PKT1_CH,AIF2_PE_CPRI1_CPRI_PKT2_CH, AIF2_PE_CPRI1_CPRI_PKT3_CH,AIF2_PE_CPRI1_CPRI_PKT0_CH_EN,AIF2_PE_CPRI1_CPRI_PKT1_CH_EN, AIF2_PE_CPRI1_CPRI_PKT2_CH_EN,AIF2_PE_CPRI1_CPRI_PKT3_CH_EN,AIF2_PE_CPRI_CW_LUT_CW_CHAN,AIF2_PE_CPRI_CW_LUT_CW_EN, AIF2_PE_LINK_LK_EN Example
CSL_aif2SetupPeLinkRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupRmLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupRmLinkRegs
Description
AIF2 Rx MAC setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_RM_LK_CFG0_MODE_SEL,AIF2_RM_LK_CFG0_LINK_RATE,AIF2_RM_LK_CFG0_FIFO_THOLD,AIF2_RM_LK_CFG0_ERROR_SUPPRESS, AIF2_RM_LK_CFG0_SD_AUTO_ALIGN_EN,AIF2_RM_LK_CFG0_SCR_EN,AIF2_RM_LK_CFG0_LCV_UNSYNC_EN,AIF2_RM_LK_CFG0_LCV_CNTR_EN, AIF2_RM_LK_CFG1_WD_WRAP,AIF2_RM_LK_CFG1_WD_EN,AIF2_RM_LK_CFG1_CQ_EN,AIF2_RM_LK_CFG1_MON_WRAP, AIF2_RM_LK_CFG2_LOS_DET_THOLD,AIF2_RM_LK_CFG3_SYNC_T,AIF2_RM_LK_CFG3_FRAME_SYNC_T, AIF2_RM_LK_CFG4_UNSYNC_T,AIF2_RM_LK_CFG4_FRAME_UNSYNC_T,AIF2_RM_LK_CFG0_RX_EN, Example
CSL_aif2SetupRmLinkRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupRtLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupRtLinkRegs
Description
AIF2 retransmitter setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_RT_LK_CFG_CI_SELECT,AIF2_RT_LK_CFG_EM_ENABLE,AIF2_RT_LK_CFG_RT_CONFIG
Example
CSL_aif2SetupRtLinkRegs (linkSetup, hAif2);
| static CSL_Status CSL_aif2SetupSdCommonRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2CommonSetup * | commonSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupSdCommonRegs
Description
AIF2 SERDES pll setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_PLL_B8_CFG_B8PLL_MULTIPLY_FACTOR,AIF2_SD_PLL_B8_CFG_B8VOLTAGE_RANGE, AIF2_SD_PLL_B8_CFG_B8LOOP_BANDWIDTH,AIF2_SD_PLL_B8_CFG_B8PLL_BYPASS, AIF2_SD_PLL_B8_EN_CFG_ENABLEB8_PLL,AIF2_SD_TX_R1_CFG_TXRATE, AIF2_SD_PLL_B4_CFG_B4PLL_MULTIPLY_FACTOR,AIF2_SD_PLL_B4_CFG_B4VOLTAGE_RANGE, AIF2_SD_PLL_B4_CFG_B4LOOP_BANDWIDTH,AIF2_SD_PLL_B4_CFG_B4PLL_BYPASS, AIF2_SD_PLL_B4_EN_CFG_ENABLEB4_PLL,AIF2_SD_CLK_SEL_CFG_ENABLERX, AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_0,AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_1, AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_2,AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_3, AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_4,AIF2_SD_LK_CLK_DIS_CFG_DISABLELINK_CLOCK_5 Example
CSL_aif2SetupSdCommonRegs (linkSetup, hAif2);
pointer to Serdes setup
| static CSL_Status CSL_aif2SetupSdLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupSdLinkRegs
Description
AIF2 SERDES Link setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2 link
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_SD_RX_R1_CFG_RXRATE,AIF2_SD_RX_R1_CFG_RXBYTE_ALIGNMENT,AIF2_SD_RX_R1_CFG_RXLOSS_OF_SIGNAL, AIF2_SD_RX_R1_CFG_RXCLOCK_AND_DATA_RECOVER,AIF2_SD_RX_R2_CFG_RXINVERT_POLARITY, AIF2_SD_RX_R2_CFG_RXTERMINATION,AIF2_SD_RX_R2_CFG_RXEQUALIZER, AIF2_SD_RX_R2_CFG_RXEQUALIZER_HOLD,AIF2_SD_RX_R2_CFG_RXENABLE_OFFSET_COMPENSATION, AIF2_SD_TX_R1_CFG_TXRATE,AIF2_SD_TX_R1_CFG_TXSYNCHRONIZATION_MASTER,AIF2_SD_TX_R2_CFG_TXINVERT_POLARITY, AIF2_SD_TX_R2_CFG_TXOUTPUT_SWING,AIF2_SD_TX_R2_CFG_TXPRECURSOR_TAP_WEIGHT, AIF2_SD_TX_R2_CFG_ADJACENTPOST_CURSOR_TAP_WEIGHT,AIF2_SD_TX_R2_CFG_TXCURSOR_FIR
Example
CSL_aif2SetupSdLinkRegs (linkSetup, hAif2);
pointer to Serdes link setup
| static CSL_Status CSL_aif2SetupTmLinkRegs | ( | CSL_Aif2Handle | hAif2, | |
| CSL_Aif2LinkSetup * | linkSetup | |||
| ) | [inline, static] |
============================================================================
CSL_aif2SetupTmLinkRegs
Description
AIF2 Tx MAC setup
Arguments
linkSetup Instance containing "Setup" properties for AIF2.
hAif2 Handle to the aif2 instance
Return Value CSL_Status
Pre Condition
CSL_aif2Init(), CSL_aif2Open()
Post Condition
None
Writes
AIF2_TM_LK_CTRL_LOS_EN,AIF2_TM_LK_SCR_CTRL_SEED_VALUE, AIF2_TM_LK_SCR_CTRL_SCR_EN, AIF2_TM_LK_L1_EN_L1_INBAND_EN, AIF2_TM_LK_LOSERR_RM_LINK_LOSERR,AIF2_TM_LK_LOFERR_RM_LINK_LOFERR, AIF2_TM_LK_LOSRX_RM_LINK_LOSRX,AIF2_TM_LK_LOFRX_RM_LINK_LOFRX,AIF2_TM_LK_RAIRX_RM_LINK_RAIRX, AIF2_TM_LK_PTRP_PTR_P,AIF2_TM_LK_STRT_STARTUP,AIF2_TM_LK_PROT_PROT_VERS,AIF2_TM_LK_CFG_TM_EN Example
CSL_aif2SetupTmLinkRegs (linkSetup, hAif2);