AIF2 Enumerated Data Types
[AIF2]


Enumerations
enum	CSL_Aif2FrameMode { CSL_AIF2_FRAME_MODE_NORMAL = 0, CSL_AIF2_FRAME_MODE_SHORT }
	Frame model supported. More...
enum	CSL_Aif2LinkProtocol { CSL_AIF2_LINK_PROTOCOL_CPRI = 0, CSL_AIF2_LINK_PROTOCOL_OBSAI }
	Link Protocol supported. More...
enum	CSL_Aif2DataWidth { CSL_AIF2_DATA_WIDTH_7_BIT = 0, CSL_AIF2_DATA_WIDTH_8_BIT, CSL_AIF2_DATA_WIDTH_15_BIT, CSL_AIF2_DATA_WIDTH_16_BIT }
	data width format supported More...
enum	CSL_Aif2LinkIndex { CSL_AIF2_LINK_0 = 0, CSL_AIF2_LINK_1, CSL_AIF2_LINK_2, CSL_AIF2_LINK_3, CSL_AIF2_LINK_4, CSL_AIF2_LINK_5, CSL_AIF2_NO_LINK = 0xF }
	aif2 link indices supported More...
enum	CSL_Aif2LinkRate { CSL_AIF2_LINK_RATE_8x = 0, CSL_AIF2_LINK_RATE_4x, CSL_AIF2_LINK_RATE_2x, CSL_AIF2_LINK_RATE_5x }
	link rates supported More...
enum	CSL_Aif2TmSyncState { CSL_AIF2_TM_ST_OFF = 0x1, CSL_AIF2_TM_ST_IDLE = 0x2, CSL_AIF2_TM_ST_RE_SYNC = 0x4, CSL_AIF2_TM_ST_FRAME_SYNC = 0x8 }
	TM states. More...
enum	CSL_Aif2RmFifoThold { CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY = 0, CSL_AIF2_RM_FIFO_THOLD_4DUAL, CSL_AIF2_RM_FIFO_THOLD_8DUAL, CSL_AIF2_RM_FIFO_THOLD_16DUAL }
	setup Rm fifo threshold word size for reading received data More...
enum	CSL_Aif2RmErrorSuppress { CSL_AIF2_RM_ERROR_ALLOW = 0, CSL_AIF2_RM_ERROR_SUPPRESS }
	Suppress error reporting when the receiver state machine is not in state ST3. More...
enum	CSL_Aif2RmSyncState { CSL_AIF2_RM_ST_0 = 8, CSL_AIF2_RM_ST_1 = 4, CSL_AIF2_RM_ST_2 = 2, CSL_AIF2_RM_ST_3 = 1, CSL_AIF2_RM_ST_4 = 16, CSL_AIF2_RM_ST_5 = 32 }
	RM sync states. More...
enum	CSL_Aif2LinkDataType { CSL_AIF2_LINK_DATA_TYPE_NORMAL = 0, CSL_AIF2_LINK_DATA_TYPE_RSA }
	Link data type supported. More...
enum	CSL_Aif2GSMDataFormat { CSL_AIF2_GSM_DATA_OTHER = 0, CSL_AIF2_GSM_DATA_UL }
	GSM data type supported. More...
enum	CSL_Aif2RtConfig { CSL_AIF2_RT_MODE_RETRANSMIT, CSL_AIF2_RT_MODE_AGGREGATE, CSL_AIF2_RT_MODE_TRANSMIT }
	Retransmitter Mode used. More...
enum	CSL_Aif2SdRxTerm { CSL_AIF2_SD_RX_TERM_COMMON_POINT_VDDT = 0, CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 = 1, CSL_AIF2_SD_RX_TERM_COMMON_POINT_FLOATING = 3 }
	Sd module index. More...
enum	CSL_Aif2SdRxEqConfig { CSL_AIF2_SD_RX_EQ_MAXIMUM = 0, CSL_AIF2_SD_RX_EQ_ADAPTIVE, CSL_AIF2_SD_RX_EQ_PRECURSOR, CSL_AIF2_SD_RX_EQ_POSTCURSOR }
	Sd module index. More...
enum	CSL_Aif2SdRxInvertPolarity { CSL_AIF2_SD_RX_NORMAL_POLARITY = 0, CSL_AIF2_SD_RX_INVERTED_POLARITY }
	Sd module index. More...
enum	CSL_Aif2SdRxAlign { CSL_AIF2_SD_RX_ALIGNMENT_DISABLE = 0, CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE, CSL_AIF2_SD_RX_ALIGNMENT_JOG }
	Sd module rx alignment. More...
enum	CSL_Aif2SdRxLos { CSL_AIF2_SD_RX_LOS_DISABLE = 0, CSL_AIF2_SD_RX_LOS_ENABLE = 4 }
	Sd module rx LOS. More...
enum	CSL_Aif2SdRxCdrAlg { CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1 = 0, CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_17 = 1, CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_1 = 4, CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_17 = 5 }
	Sd clock recovery algorithm. More...
enum	CSL_Aif2SdTxOutputSwing { CSL_AIF2_SD_TX_OUTPUT_SWING_0 = 0, CSL_AIF2_SD_TX_OUTPUT_SWING_1, CSL_AIF2_SD_TX_OUTPUT_SWING_2, CSL_AIF2_SD_TX_OUTPUT_SWING_3, CSL_AIF2_SD_TX_OUTPUT_SWING_4, CSL_AIF2_SD_TX_OUTPUT_SWING_5, CSL_AIF2_SD_TX_OUTPUT_SWING_6, CSL_AIF2_SD_TX_OUTPUT_SWING_7, CSL_AIF2_SD_TX_OUTPUT_SWING_8, CSL_AIF2_SD_TX_OUTPUT_SWING_9, CSL_AIF2_SD_TX_OUTPUT_SWING_10, CSL_AIF2_SD_TX_OUTPUT_SWING_11, CSL_AIF2_SD_TX_OUTPUT_SWING_12, CSL_AIF2_SD_TX_OUTPUT_SWING_13, CSL_AIF2_SD_TX_OUTPUT_SWING_14, CSL_AIF2_SD_TX_OUTPUT_SWING_15 }
	Sd module index. More...
enum	CSL_Aif2SdTxInvertPolarity { CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY = 0, CSL_AIF2_SD_TX_PAIR_INVERTED_POLARITY }
	Sd module index. More...
enum	CSL_Aif2SdTxPostcursorTabWeight { CSL_AIF2_SD_TX_POST_TAP_WEIGHT_0 = 0, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_1, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_2, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_3, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_4, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_5, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_6, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_7, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_8, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_9, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_10, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_11, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_12, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_13, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_14, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_15, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_16, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_17, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_18, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_19, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_20, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_21, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_22, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_23, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_25, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_26, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_27, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_28, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_29, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_30, CSL_AIF2_SD_TX_POST_TAP_WEIGHT_31 }
	Sd module index. More...
enum	CSL_Aif2SdTxPrecursorTabWeight { CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_0 = 0, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_1, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_3, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_4, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_5, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_6, CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_7 }
	Sd module index. More...
enum	CSL_Aif2SdTestPattern { CSL_AIF2_SD_TEST_DISABLED = 0, CSL_AIF2_SD_ALTERNATING_0_1, CSL_AIF2_SD_PRBS_7BIT_LFSR, CSL_AIF2_SD_PRBS_23BIT_LFSR, CSL_AIF2_SD_PRBS_31BIT_LFSR }
	Sd link test pattern index. More...
enum	CSL_Aif2PllMpyFactor { CSL_AIF2_PLL_MUL_FACTOR_4X = 16, CSL_AIF2_PLL_MUL_FACTOR_5X = 20, CSL_AIF2_PLL_MUL_FACTOR_6X = 24, CSL_AIF2_PLL_MUL_FACTOR_8X = 32, CSL_AIF2_PLL_MUL_FACTOR_8_25X = 33, CSL_AIF2_PLL_MUL_FACTOR_10X = 40, CSL_AIF2_PLL_MUL_FACTOR_12X = 48, CSL_AIF2_PLL_MUL_FACTOR_12_5X = 50, CSL_AIF2_PLL_MUL_FACTOR_15X = 60, CSL_AIF2_PLL_MUL_FACTOR_16X = 64, CSL_AIF2_PLL_MUL_FACTOR_16_5X = 66, CSL_AIF2_PLL_MUL_FACTOR_20X = 80, CSL_AIF2_PLL_MUL_FACTOR_22X = 88, CSL_AIF2_PLL_MUL_FACTOR_25X = 100 }
	Sd module index. More...
enum	CSL_Aif2SdVoltRange { CSL_AIF2_PLL_VOLTAGE_LOW = 0, CSL_AIF2_PLL_VOLTAGE_HIGH }
	Sd pll voltage range. More...
enum	CSL_Aif2SdSleepPll { CSL_AIF2_PLL_AWAKE = 0, CSL_AIF2_PLL_SLEEP }
	Sd pll sleep. More...
enum	CSL_Aif2SdLoopBandwidth { CSL_AIF2_PLL_LOOP_BAND_MID = 0, CSL_AIF2_PLL_LOOP_BAND_UHIGH, CSL_AIF2_PLL_LOOP_BAND_LOW, CSL_AIF2_PLL_LOOP_BAND_HIGH }
	Sd pll loop bandwidth selection. More...
enum	CSL_Aif2SdClockBypass
	Sd pll clock bypass selection. More...
enum	CSL_Aif2SdClockSelect
	Sd sys clock select from either B8 or B4.
enum	CSL_Aif2CpriCwPktDelim { CSL_AIF2_CW_DELIM_NO_CW = 0, CSL_AIF2_CW_DELIM_4B5B, CSL_AIF2_CW_DELIM_NULLDELM, CSL_AIF2_CW_DELIM_HYP_FRM }
	CRPI Control Word 4B/5B encoding enable. More...
enum	CSL_Aif2PdDataMode { CSL_AIF2_PD_DATA_AXC = 0, CSL_AIF2_PD_DATA_PKT }
	dicates the payload is to be used as AxC (normal) or Packet traffic More...
enum	CSL_Aif2CppiDio { CSL_AIF2_CPPI = 0, CSL_AIF2_DIO }
	select mode between CPPI and DIO More...
enum	CSL_Aif2PdWatchDogReport { CSL_AIF2_PD_WD_REPORT_ALL = 0, CSL_AIF2_PD_WD_REPORT_EOP }
	Report every missed WDog fail, or report only fails of missing EOP. More...
enum	CSL_Aif2ObsaiTsMask { CSL_AIF2_TSTAMP_MASK_FULL_GEN = 0, CSL_AIF2_TSTAMP_MASK_4INS_2GEN, CSL_AIF2_TSTAMP_MASK_FULL_INS }
	PD or PE Obsai time stamp mask supported. More...
enum	CSL_Aif2TstampFormat { CSL_AIF2_TSTAMP_FORMAT_NO_TS = 0, CSL_AIF2_TSTAMP_FORMAT_NORM_TS, CSL_AIF2_TSTAMP_FORMAT_GSM, CSL_AIF2_TSTAMP_FORMAT_GEN_PKT, CSL_AIF2_TSTAMP_FORMAT_ETHERNET, CSL_AIF2_TSTAMP_FORMAT_ROUTE_CHECK, CSL_AIF2_TSTAMP_FORMAT_GSM_DL }
	PD or PE time stamp format supported. More...
enum	CSL_Aif2RouteMask { CSL_AIF2_ROUTE_MASK_NONE = 0, CSL_AIF2_ROUTE_MASK_4LSB, CSL_AIF2_ROUTE_MASK_ALL, CSL_AIF2_ROUTE_MASK_RESERVED }
	controls how many OBSAI time stamp bits to use in the reception routing. More...
enum	CSL_Aif2CpriAxCPack { CSL_AIF2_CPRI_7BIT_SAMPLE = 0, CSL_AIF2_CPRI_8BIT_SAMPLE, CSL_AIF2_CPRI_15BIT_SAMPLE, CSL_AIF2_CPRI_16BIT_SAMPLE }
	select CPRI AxC data pack type More...
enum	CSL_Aif2PeRtContol { CSL_AIF2_PE_RT_RETRANS = 0, CSL_AIF2_PE_RT_INSERT, CSL_AIF2_PE_RT_ADD8, CSL_AIF2_PE_RT_ADD16 }
	Controls RT to perform appropriate insterion/aggregation into PHY. More...
enum	CSL_Aif2CrcLen { CSL_AIF2_CRC_32BIT = 0, CSL_AIF2_CRC_16BIT, CSL_AIF2_CRC_8BIT }
	CRC: length of CRC. More...
enum	CSL_Aif2DbFifoDepth { CSL_AIF2_DB_FIFO_DEPTH_QW8 = 0, CSL_AIF2_DB_FIFO_DEPTH_QW16, CSL_AIF2_DB_FIFO_DEPTH_QW32, CSL_AIF2_DB_FIFO_DEPTH_QW64, CSL_AIF2_DB_FIFO_DEPTH_QW128, CSL_AIF2_DB_FIFO_DEPTH_QW256 }
	DB FIFO bufffer depth. More...
enum	CSL_Aif2DbDataSwap { CSL_AIF2_DB_NO_SWAP = 0, CSL_AIF2_DB_BYTE_SWAP, CSL_AIF2_DB_HALF_WORD_SWAP, CSL_AIF2_DB_WORD_SWAP }
	DB Big endian swapping control. More...
enum	CSL_Aif2DbIqOrder { CSL_AIF2_DB_IQ_NO_SWAP = 0, CSL_AIF2_DB_IQ_NO_SWAP1, CSL_AIF2_DB_IQ_BYTE_SWAP, CSL_AIF2_DB_IQ_16BIT_SWAP }
	Internally changing IQ data order control. More...
enum	CSL_Aif2DioLen { CSL_AIF2_DB_DIO_LEN_128 = 0, CSL_AIF2_DB_DIO_LEN_256 }
	DB DIO length type. More...
enum	CSL_Aif2DbPmControl { CSL_AIF2_DB_PM_TOKEN_FIFO = 0, CSL_AIF2_DB_AXC_TOKEN_FIFO }
	DB Packet mode control type. More...
enum	CSL_Aif2AdFailMode { CSL_AIF2_AD_DROP = 0, CSL_AIF2_AD_MARK }
	This field tells how the Ingress Scheduler handles packets marked as failed by the PD. More...
enum	CSL_Aif2AdIngrPriority { CSL_AIF2_AD_DIO_PRI = 0, CSL_AIF2_AD_PKT_PRI }
	AD Ingress Scheduler aribitration priority. More...
enum	CSL_Aif2AdEgrPriority { CSL_AIF2_AD_AXC_PRI = 0, CSL_AIF2_AD_NON_AXC_PRI }
	AD Egress Scheduler aribitration priority. More...
enum	CSL_Aif2AdNumQWord { CSL_AIF2_AD_1QUAD = 0, CSL_AIF2_AD_2QUAD, CSL_AIF2_AD_4QUAD }
	AD DIO Quad word number for each AxC data. More...
enum	CSL_Aif2AdBcnTable
	AD DIO BCN TABLE SEL type. More...
enum	CSL_Aif2DioEngineIndex { CSL_AIF2_DIO_ENGINE_0 = 0, CSL_AIF2_DIO_ENGINE_1, CSL_AIF2_DIO_ENGINE_2 }
	aif2 dio engine index supported More...
enum	CSL_Aif2AtEvtStrobe { CSL_AIF2_RADT_SYMBOL = 0, CSL_AIF2_RADT_FRAME, CSL_AIF2_ULRADT_SYMBOL, CSL_AIF2_ULRADT_FRAME, CSL_AIF2_DLRADT_SYMBOL, CSL_AIF2_DLRADT_FRAME, CSL_AIF2_PHYT_FRAME }
	AT Rad event strobe selection type. More...
enum	CSL_Aif2AtEventIndex { CSL_AIF2_EVENT_0 = 0, CSL_AIF2_EVENT_1, CSL_AIF2_EVENT_2, CSL_AIF2_EVENT_3, CSL_AIF2_EVENT_4, CSL_AIF2_EVENT_5, CSL_AIF2_EVENT_6, CSL_AIF2_EVENT_7, CSL_AIF2_EVENT_8, CSL_AIF2_EVENT_9, CSL_AIF2_EVENT_10, CSL_AIF2_IN_DIO_EVENT_0, CSL_AIF2_IN_DIO_EVENT_1, CSL_AIF2_IN_DIO_EVENT_2, CSL_AIF2_E_DIO_EVENT_0, CSL_AIF2_E_DIO_EVENT_1, CSL_AIF2_E_DIO_EVENT_2 }
	AT Event selection type. More...
enum	CSL_Aif2AtSyncSource { CSL_AIF2_RP1_SYNC = 0, CSL_AIF2_CHIP_INPUT_SYNC, CSL_AIF2_SW_SYNC, CSL_AIF2_RM_AT_SYNC, CSL_AIF2_PHYT_CMP_SYNC }
	Timer sync sources in AT. More...
enum	CSL_Aif2AtSyncMode { CSL_AIF2_NON_RP1_MODE = 0, CSL_AIF2_RP1_MODE }
	Sync mode for AT. More...
enum	CSL_Aif2AtReSyncMode { CSL_AIF2_NO_AUTO_RESYNC_MODE = 0, CSL_AIF2_AUTO_RESYNC_MODE }
	Re-Sync mode for AT. More...
enum	CSL_Aif2AtCrcUse { CSL_AIF2_AT_CRC_DONT_USE = 0, CSL_AIF2_AT_CRC_USE }
	select CRC mode on / off More...
enum	CSL_Aif2AtCrcFlip { CSL_AIF2_AT_CRC_NORMAL = 0, CSL_AIF2_AT_CRC_REVERSE }
	select CRC flip mode between normal and reverse More...
enum	CSL_Aif2AtCrcInitOnes { CSL_AIF2_AT_CRC_INIT0 = 0, CSL_AIF2_AT_CRC_INIT1 }
	select CRC init value More...
enum	CSL_Aif2AtCrcInvert { CSL_AIF2_AT_CRC_NOINVERT = 0, CSL_AIF2_AT_CRC_INVERT }
	select CRC invert mode More...
enum	CSL_Aif2AtRp1CRCUsage { CSL_AIF2_USE_SYNC_BURST_ON_CRC_FAIL = 0, CSL_AIF2_DISCARD_SYNC_BURST_ON_CRC_FAIL }
	CRC usage in RP1 sync mode for AT. More...
enum	CSL_Aif2AtRp1TypeField { CSL_AIF2_RP1_TYPE_NOT_USED = 0x00, CSL_AIF2_RP1_TYPE_RP3_FRAME_NUM = 0x01, CSL_AIF2_RP1_TYPE_WCDMA_FDD_FRAME_NUM = 0x02, CSL_AIF2_RP1_TYPE_GSM_EDGE_1_FRAME_NUM = 0x03, CSL_AIF2_RP1_TYPE_GSM_EDGE_2_FRAME_NUM = 0x04, CSL_AIF2_RP1_TYPE_GSM_EDGE_3_FRAME_NUM = 0x05, CSL_AIF2_RP1_TYPE_WCDMA_TDD_FRAME_NUM = 0x06, CSL_AIF2_RP1_TYPE_CDMA_2000_FRAME_NUM = 0x07, CSL_AIF2_RP1_TYPE_TOD = 0x08, CSL_AIF2_RP1_TYPE_RESERVED_FIRST = 0x09, CSL_AIF2_RP1_TYPE_RESERVED_LAST = 0x7F, CSL_AIF2_RP1_TYPE_SPARE_FIRST = 0x80, CSL_AIF2_RP1_TYPE_SPARE_LAST = 0xFF }
	Type field definitions for RP1 sync burst. More...
enum	CSL_Aif2EeArgIndex { CSL_AIF2_EE_INT_RAW_STATUS = 0, CSL_AIF2_EE_INT_SET, CSL_AIF2_EE_INT_CLR, CSL_AIF2_EE_INT_EN_STATUS_EV0, CSL_AIF2_EE_INT_EN_STATUS_EV1, CSL_AIF2_EE_INT_EN_EV0, CSL_AIF2_EE_INT_EN_EV1, CSL_AIF2_EE_INT_EN_SET_EV0, CSL_AIF2_EE_INT_EN_SET_EV1, CSL_AIF2_EE_INT_EN_CLR_EV0, CSL_AIF2_EE_INT_EN_CLR_EV1 }
	select EE module working function More...
enum	CSL_Aif2HwControlCmd { CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK = 0, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, CSL_AIF2_CMD_ENABLE_DISABLE_SD_B8_PLL, CSL_AIF2_CMD_ENABLE_DISABLE_SD_B4_PLL, CSL_AIF2_CMD_VC_EMU_CONTROL, CSL_AIF2_CMD_SD_LINK_TX_TEST_PATTERN, CSL_AIF2_CMD_SD_LINK_RX_TEST_PATTERN, CSL_AIF2_CMD_RM_FORCE_STATE, CSL_AIF2_CMD_TM_L1_INBAND_SET, CSL_AIF2_CMD_TM_FLUSH_FIFO, CSL_AIF2_CMD_TM_IDLE, CSL_AIF2_CMD_TM_RESYNC, CSL_AIF2_CMD_PD_CPRI_ID_LUT_SETUP, CSL_AIF2_CMD_PD_CPRI_CW_LUT_SETUP, CSL_AIF2_CMD_PD_LINK_DBMR_SETUP, CSL_AIF2_CMD_PD_CH_CONFIG_SETUP, CSL_AIF2_CMD_PE_CPRI_CW_LUT_SETUP, CSL_AIF2_CMD_PE_OBSAI_HEADER_SETUP, CSL_AIF2_CMD_PE_LINK_DBMR_SETUP, CSL_AIF2_CMD_PE_MODULO_RULE_SETUP, CSL_AIF2_CMD_PE_CH_CONFIG_SETUP, CSL_AIF2_CMD_PE_CH_RULE_LUT_SETUP, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_DATA_CAPTURE, CSL_AIF2_CMD_ENABLE_DISABLE_DATA_TRACE_SYNC, CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_DEBUG_MODE, CSL_AIF2_CMD_DB_IN_DEBUG_DATA_SETUP, CSL_AIF2_CMD_DB_IN_DEBUG_SIDE_DATA_SETUP, CSL_AIF2_CMD_DB_IN_DEBUG_WRITE, CSL_AIF2_CMD_DB_IN_DEBUG_OFFSET_ADDR, CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_CHANNEL, CSL_AIF2_CMD_DB_IN_CHANNEL_SETUP, CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_DEBUG_MODE, CSL_AIF2_CMD_DB_E_DEBUG_READ_CONTROL, CSL_AIF2_CMD_DB_E_DEBUG_WRITE_TOKEN, CSL_AIF2_CMD_DB_E_DEBUG_READ, CSL_AIF2_CMD_DB_E_DEBUG_OFFSET_ADDR, CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_CHANNEL, CSL_AIF2_CMD_DB_E_CHANNEL_SETUP, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_DIO_GLOBAL, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_DIO_GLOBAL, CSL_AIF2_CMD_AD_IN_DIO_TABLE_SELECT, CSL_AIF2_CMD_AD_IN_DIO_NUM_AXC_CHANGE, CSL_AIF2_CMD_AD_IN_DIO_BCN_TABLE_CHANGE, CSL_AIF2_CMD_AD_E_DIO_TABLE_SELECT, CSL_AIF2_CMD_AD_E_DIO_NUM_AXC_CHANGE, CSL_AIF2_CMD_AD_E_DIO_BCN_TABLE_CHANGE, CSL_AIF2_CMD_AD_TRACE_DATA_DMA_CHANNEL_ON_OFF, CSL_AIF2_CMD_AD_TRACE_DATA_BASE_ADDR, CSL_AIF2_CMD_AD_TRACE_FRAMING_DATA_BASE_ADDR, CSL_AIF2_CMD_AD_TRACE_CPPI_DMA_BURST_WRAP, CSL_AIF2_CMD_AT_EVENT_SETUP, CSL_AIF2_CMD_AT_DELTA_SETUP, CSL_AIF2_CMD_AT_HALT_TIMER, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, CSL_AIF2_CMD_AT_ARM_TIMER, CSL_AIF2_CMD_AT_DEBUG_SYNC, CSL_AIF2_CMD_AT_RAD_WCDMA_DIV, CSL_AIF2_CMD_AT_RAD_TC_SETUP, CSL_AIF2_CMD_AT_GSM_TCOUNT_SETUP, CSL_AIF2_CMD_AT_ENABLE_EVENT, CSL_AIF2_CMD_AT_DISABLE_EVENT, CSL_AIF2_CMD_AT_FORCE_EVENT, CSL_AIF2_CMD_EE_EOI_SETUP, CSL_AIF2_CMD_EE_AIF2_ERROR_INT, CSL_AIF2_CMD_EE_DB_INT, CSL_AIF2_CMD_EE_AD_INT, CSL_AIF2_CMD_EE_CD_INT, CSL_AIF2_CMD_EE_SD_INT, CSL_AIF2_CMD_EE_VC_INT, CSL_AIF2_CMD_EE_AIF2_RUN, CSL_AIF2_CMD_EE_LINKA_INT, CSL_AIF2_CMD_EE_LINKB_INT, CSL_AIF2_CMD_EE_AT_INT, CSL_AIF2_CMD_EE_PD_INT, CSL_AIF2_CMD_EE_PE_INT }
enum	CSL_Aif2HwStatusQuery { CSL_AIF2_QUERY_VERSION = 0, CSL_AIF2_QUERY_VC_STAT, CSL_AIF2_QUERY_SD_RX_LINK_STATUS, CSL_AIF2_QUERY_SD_TX_LINK_STATUS, CSL_AIF2_QUERY_SD_B8_PLL_LOCK, CSL_AIF2_QUERY_SD_B4_PLL_LOCK, CSL_AIF2_QUERY_RM_LINK_STATUS_0, CSL_AIF2_QUERY_RM_LINK_STATUS_1, CSL_AIF2_QUERY_RM_LINK_STATUS_2, CSL_AIF2_QUERY_RM_LINK_STATUS_3, CSL_AIF2_QUERY_RM_LINK_STATUS_4, CSL_AIF2_QUERY_TM_LINK_CPRI_HFN, CSL_AIF2_QUERY_TM_LINK_STATUS, CSL_AIF2_QUERY_RT_FIFO_DEPTH_STATUS, CSL_AIF2_QUERY_RT_HEADER_ERROR_STATUS, CSL_AIF2_QUERY_RT_LINK_STATUS, CSL_AIF2_QUERY_PD_CHANNEL_STATUS, CSL_AIF2_QUERY_PD_PACKET_STATUS, CSL_AIF2_QUERY_PE_CHANNEL_STATUS, CSL_AIF2_QUERY_PE_PACKET_STATUS, CSL_AIF2_QUERY_DB_IN_DEBUG_OFFSET_DATA, CSL_AIF2_QUERY_DB_E_DEBUG_DATA, CSL_AIF2_QUERY_DB_E_DEBUG_SIDE_DATA, CSL_AIF2_QUERY_DB_E_DEBUG_OFFSET_DATA, CSL_AIF2_QUERY_DB_E_EOP_COUNT, CSL_AIF2_QUERY_AD_I_EOP_COUNT, CSL_AIF2_QUERY_AT_LINK_PI_CAPTURE, CSL_AIF2_QUERY_AT_RADT_CAPTURE, CSL_AIF2_QUERY_AT_RP1_TYPE_CAPTURE, CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_LSB, CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_MSB, CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_LSB, CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_MSB, CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_LSB, CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_MSB, CSL_AIF2_QUERY_AT_PHY_CLOCK_COUNT, CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_LSB, CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_MSB, CSL_AIF2_QUERY_AT_RAD_CLOCK_COUNT, CSL_AIF2_QUERY_AT_RAD_SYMBOL_COUNT, CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_LSB, CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_MSB, CSL_AIF2_QUERY_AT_ULRAD_CLOCK_COUNT, CSL_AIF2_QUERY_AT_ULRAD_SYMBOL_COUNT, CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_LSB, CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_MSB, CSL_AIF2_QUERY_AT_DLRAD_CLOCK_COUNT, CSL_AIF2_QUERY_AT_DLRAD_SYMBOL_COUNT, CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_LSB, CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_MSB, CSL_AIF2_QUERY_AT_RAD_WCDMA_VALUE, CSL_AIF2_QUERY_AT_ULRAD_WCDMA_VALUE, CSL_AIF2_QUERY_AT_DLRAD_WCDMA_VALUE, CSL_AIF2_QUERY_AT_RAD_TSTAMP_CLOCK_COUNT, CSL_AIF2_QUERY_AT_GSM_TCOUNT_VALUE, CSL_AIF2_QUERY_EE_DB_INT_STATUS, CSL_AIF2_QUERY_EE_AD_INT_STATUS, CSL_AIF2_QUERY_EE_CD_INT_STATUS, CSL_AIF2_QUERY_EE_SD_INT_STATUS, CSL_AIF2_QUERY_EE_VC_INT_STATUS, CSL_AIF2_QUERY_EE_AIF2_RUN_STATUS, CSL_AIF2_QUERY_EE_AIF2_ORIGINATION, CSL_AIF2_QUERY_EE_LINKA_INT_STATUS, CSL_AIF2_QUERY_EE_LINKB_INT_STATUS, CSL_AIF2_QUERY_EE_AT_INT_STATUS }

Enumeration Type Documentation

enum CSL_Aif2AdBcnTable

AD DIO BCN TABLE SEL type.

Use this symbol to specify DIO bcn table selection type for AD

enum CSL_Aif2AdEgrPriority

AD Egress Scheduler aribitration priority.

Enumerator:

CSL_AIF2_AD_AXC_PRI	Set AxC data as high priority
CSL_AIF2_AD_NON_AXC_PRI	Set non AxC data as high priority

enum CSL_Aif2AdFailMode

This field tells how the Ingress Scheduler handles packets marked as failed by the PD.

Enumerator:

CSL_AIF2_AD_DROP	Selects AD error data drop
CSL_AIF2_AD_MARK	Selects AD error data mark

enum CSL_Aif2AdIngrPriority

AD Ingress Scheduler aribitration priority.

Enumerator:

CSL_AIF2_AD_DIO_PRI	Set dio as high priority
CSL_AIF2_AD_PKT_PRI	Set cppi packet as high priority

enum CSL_Aif2AdNumQWord

AD DIO Quad word number for each AxC data.

Enumerator:

CSL_AIF2_AD_1QUAD	Set AD dio quad word number to 1 quad
CSL_AIF2_AD_2QUAD	Set AD dio quad word number to 2 quad
CSL_AIF2_AD_4QUAD	Set AD dio quad word number to 4 quad

enum CSL_Aif2AtCrcFlip

select CRC flip mode between normal and reverse

Enumerator:

CSL_AIF2_AT_CRC_NORMAL	use at crc normal mode
CSL_AIF2_AT_CRC_REVERSE	use at crc reverse mode

enum CSL_Aif2AtCrcInitOnes

select CRC init value

Enumerator:

CSL_AIF2_AT_CRC_INIT0	use at crc init0
CSL_AIF2_AT_CRC_INIT1	use at crc init1

enum CSL_Aif2AtCrcInvert

select CRC invert mode

Enumerator:

CSL_AIF2_AT_CRC_NOINVERT	use at crc non invert mode
CSL_AIF2_AT_CRC_INVERT	use at crc invert mode

enum CSL_Aif2AtCrcUse

select CRC mode on / off

Enumerator:

CSL_AIF2_AT_CRC_DONT_USE	Don't use at crc
CSL_AIF2_AT_CRC_USE	Use at crc

enum CSL_Aif2AtEventIndex

AT Event selection type.

Use this symbol to specify event type for AT dynamic event setup

Enumerator:

CSL_AIF2_EVENT_0	Selects external event 0
CSL_AIF2_EVENT_1	Selects external event 1
CSL_AIF2_EVENT_2	Selects external event 2
CSL_AIF2_EVENT_3	Selects external event 3
CSL_AIF2_EVENT_4	Selects external event 4
CSL_AIF2_EVENT_5	Selects external event 5
CSL_AIF2_EVENT_6	Selects external event 6
CSL_AIF2_EVENT_7	Selects external event 7
CSL_AIF2_EVENT_8	Selects special event 8
CSL_AIF2_EVENT_9	Selects special event 9
CSL_AIF2_EVENT_10	Selects special event 10
CSL_AIF2_IN_DIO_EVENT_0	Selects ingress dio event 0
CSL_AIF2_IN_DIO_EVENT_1	Selects ingress dio event 1
CSL_AIF2_IN_DIO_EVENT_2	Selects ingress dio event 2
CSL_AIF2_E_DIO_EVENT_0	Selects egress dio event 0
CSL_AIF2_E_DIO_EVENT_1	Selects egress dio event 1
CSL_AIF2_E_DIO_EVENT_2	Selects egress dio event 2

enum CSL_Aif2AtEvtStrobe

AT Rad event strobe selection type.

Use this symbol to specify rad event strobe type for AT

Enumerator:

CSL_AIF2_RADT_SYMBOL	Selects rad timer symbol strobe
CSL_AIF2_RADT_FRAME	Selects rad timer frame strobe
CSL_AIF2_ULRADT_SYMBOL	Selects ul rad timer symbol strobe
CSL_AIF2_ULRADT_FRAME	Selects ul rad timer frame strobe
CSL_AIF2_DLRADT_SYMBOL	Selects dl rad timer symbol strobe
CSL_AIF2_DLRADT_FRAME	Selects dl rad timer frame strobe
CSL_AIF2_PHYT_FRAME	Selects phy timer frame strobe

enum CSL_Aif2AtReSyncMode

Re-Sync mode for AT.

Use this symbol to specify re-sync mode for AT

Enumerator:

CSL_AIF2_NO_AUTO_RESYNC_MODE	Selects at no auto resync mode
CSL_AIF2_AUTO_RESYNC_MODE	Selects at auto resync mode

enum CSL_Aif2AtRp1CRCUsage

CRC usage in RP1 sync mode for AT.

Use this symbol to specify CRC usage mode when AT is used in RP1 sync mode

Enumerator:

CSL_AIF2_USE_SYNC_BURST_ON_CRC_FAIL	use at sync burst on crc fail
CSL_AIF2_DISCARD_SYNC_BURST_ON_CRC_FAIL	discard at sync burst on crc fail

enum CSL_Aif2AtRp1TypeField

Type field definitions for RP1 sync burst.

Use this symbol to specify the type field in the RP1 sync burst

Enumerator:

CSL_AIF2_RP1_TYPE_NOT_USED	Selects rp1 type not used
CSL_AIF2_RP1_TYPE_RP3_FRAME_NUM	Selects rp1 type rp3 frame number
CSL_AIF2_RP1_TYPE_WCDMA_FDD_FRAME_NUM	Selects rp1 type wcdma fdd frame number
CSL_AIF2_RP1_TYPE_GSM_EDGE_1_FRAME_NUM	Selects rp1 type gsm edge 1 frame number
CSL_AIF2_RP1_TYPE_GSM_EDGE_2_FRAME_NUM	Selects rp1 type gsm edge 2 frame number
CSL_AIF2_RP1_TYPE_GSM_EDGE_3_FRAME_NUM	Selects rp1 type gsm edge3 frame number
CSL_AIF2_RP1_TYPE_WCDMA_TDD_FRAME_NUM	Selects rp1 type wcdma tdd frame number
CSL_AIF2_RP1_TYPE_CDMA_2000_FRAME_NUM	Selects rp1 type cdma 2000 frame number
CSL_AIF2_RP1_TYPE_TOD	Selects rp1 type tdd
CSL_AIF2_RP1_TYPE_RESERVED_FIRST	Selects rp1 type reserved first
CSL_AIF2_RP1_TYPE_RESERVED_LAST	Selects rp1 type reserved last
CSL_AIF2_RP1_TYPE_SPARE_FIRST	Selects rp1 type spare first
CSL_AIF2_RP1_TYPE_SPARE_LAST	Selects rp1 type spare last

enum CSL_Aif2AtSyncMode

Sync mode for AT.

Use this symbol to specify sync mode for AT

Enumerator:

CSL_AIF2_NON_RP1_MODE	Selects non rp1 mode
CSL_AIF2_RP1_MODE	Selects rp1 mode

enum CSL_Aif2AtSyncSource

Timer sync sources in AT.

Use this symbol to specify timer sync source for AT

Enumerator:

CSL_AIF2_RP1_SYNC	Selects RP1 sync
CSL_AIF2_CHIP_INPUT_SYNC	Selects chip input sync
CSL_AIF2_SW_SYNC	Selects sw debug sync
CSL_AIF2_RM_AT_SYNC	Selects rm at sync
CSL_AIF2_PHYT_CMP_SYNC	Selects phy timer compare sync

enum CSL_Aif2CppiDio

select mode between CPPI and DIO

Enumerator:

CSL_AIF2_CPPI	Use CPPI mode
CSL_AIF2_DIO	Use DIO for AxC data

enum CSL_Aif2CpriAxCPack

select CPRI AxC data pack type

Enumerator:

CSL_AIF2_CPRI_7BIT_SAMPLE	AxC data is 7bit I & 7bit Q (byte packing needed)
CSL_AIF2_CPRI_8BIT_SAMPLE	AxC data is 8bit I & 8bit Q (byte aligned)
CSL_AIF2_CPRI_15BIT_SAMPLE	AxC data is 15bit I & 15bit Q (byte packing needed)
CSL_AIF2_CPRI_16BIT_SAMPLE	AxC data is 16bit I & 16bit Q (byte aligned)

enum CSL_Aif2CpriCwPktDelim

CRPI Control Word 4B/5B encoding enable.

Enumerator:

CSL_AIF2_CW_DELIM_NO_CW	User defined data is not extracted from CPRI Control Words
CSL_AIF2_CW_DELIM_4B5B	CW user data is delimitted using 4B/5B encoding where SOP & EOP are defined
CSL_AIF2_CW_DELIM_NULLDELM	CW user data is delimitted by a user defined Null Delimiter (defined in other MMR field)
CSL_AIF2_CW_DELIM_HYP_FRM	Packet Boundaries are inferred to be on hyper-frame boundaries

enum CSL_Aif2CrcLen

CRC: length of CRC.

Use this symbol to specify crc length for PE,PD

Enumerator:

CSL_AIF2_CRC_32BIT	CRC 32 bits
CSL_AIF2_CRC_16BIT	CRC 16 bits
CSL_AIF2_CRC_8BIT	CRC 8 bits

enum CSL_Aif2DataWidth

data width format supported

Use this symbol to specify DL/UL and Generic data formats for AIF2

Enumerator:

CSL_AIF2_DATA_WIDTH_7_BIT	Selects 7bit data width
CSL_AIF2_DATA_WIDTH_8_BIT	Selects 8bit data width
CSL_AIF2_DATA_WIDTH_15_BIT	Selects 15bit data width
CSL_AIF2_DATA_WIDTH_16_BIT	Selects 16bit data width

enum CSL_Aif2DbDataSwap

DB Big endian swapping control.

Enumerator:

CSL_AIF2_DB_NO_SWAP	Selects DB no swap
CSL_AIF2_DB_BYTE_SWAP	Selects DB byte swap
CSL_AIF2_DB_HALF_WORD_SWAP	Selects DB half word swap
CSL_AIF2_DB_WORD_SWAP	Selects DB word swap

enum CSL_Aif2DbFifoDepth

DB FIFO bufffer depth.

Use this symbol to specify the buffer depth for DB FIFO

Enumerator:

CSL_AIF2_DB_FIFO_DEPTH_QW8	Selects FIFO buffer depth to 8 quad words
CSL_AIF2_DB_FIFO_DEPTH_QW16	Selects FIFO buffer depth to 16 quad words
CSL_AIF2_DB_FIFO_DEPTH_QW32	Selects FIFO buffer depth to 32 quad words
CSL_AIF2_DB_FIFO_DEPTH_QW64	Selects FIFO buffer depth to 64 quad words
CSL_AIF2_DB_FIFO_DEPTH_QW128	Selects FIFO buffer depth to 128 quad words
CSL_AIF2_DB_FIFO_DEPTH_QW256	Selects FIFO buffer depth to 256 quad words

enum CSL_Aif2DbIqOrder

Internally changing IQ data order control.

Enumerator:

CSL_AIF2_DB_IQ_NO_SWAP	Selects DB IQ data no swap
CSL_AIF2_DB_IQ_NO_SWAP1	Selects DB IQ data no swap1
CSL_AIF2_DB_IQ_BYTE_SWAP	Selects DB IQ data byte swap
CSL_AIF2_DB_IQ_16BIT_SWAP	Selects DB IQ data 16 bit swap

enum CSL_Aif2DbPmControl

DB Packet mode control type.

Use this symbol to specify PM control for DB

Enumerator:

CSL_AIF2_DB_PM_TOKEN_FIFO	Put PM tokens from PE in separate PM Token FIFO
CSL_AIF2_DB_AXC_TOKEN_FIFO	Put PM tokens from PE in Axc Token FIFO to improve CPRI packet performance

enum CSL_Aif2DioEngineIndex

aif2 dio engine index supported

Use this symbol to specify the aif2 dio engine index

Enumerator:

CSL_AIF2_DIO_ENGINE_0	Selects dio engine 0
CSL_AIF2_DIO_ENGINE_1	Selects dio engine 1
CSL_AIF2_DIO_ENGINE_2	Selects dio engine 2

enum CSL_Aif2DioLen

DB DIO length type.

Use this symbol to specify DIO length type for DB

Enumerator:

CSL_AIF2_DB_DIO_LEN_128	Selects DB dio buffer length 128 bytes
CSL_AIF2_DB_DIO_LEN_256	Selects DB dio buffer length 256 bytes

enum CSL_Aif2EeArgIndex

select EE module working function

Use this symbol to specify one of the function of EE

Enumerator:

CSL_AIF2_EE_INT_RAW_STATUS	Selects ee interrupt raw status
CSL_AIF2_EE_INT_SET	Selects ee interrupt set
CSL_AIF2_EE_INT_CLR	Selects ee interrupt clear
CSL_AIF2_EE_INT_EN_STATUS_EV0	Selects ee interrupt enabled status ev0
CSL_AIF2_EE_INT_EN_STATUS_EV1	Selects ee interrupt enabled status ev1
CSL_AIF2_EE_INT_EN_EV0	Selects ee interrupt enable ev0
CSL_AIF2_EE_INT_EN_EV1	Selects ee interrupt enable ev1
CSL_AIF2_EE_INT_EN_SET_EV0	Selects ee interrupt enable set ev0
CSL_AIF2_EE_INT_EN_SET_EV1	Selects ee interrupt enable set ev1
CSL_AIF2_EE_INT_EN_CLR_EV0	Selects ee interrupt enable clear ev0
CSL_AIF2_EE_INT_EN_CLR_EV1	Selects ee interrupt enable clear ev1

enum CSL_Aif2FrameMode

Frame model supported.

Use this symbol to specify frame mode for AIF2

Enumerator:

CSL_AIF2_FRAME_MODE_NORMAL	Selects the Normal frame mode
CSL_AIF2_FRAME_MODE_SHORT	Selects the Short frame mode

enum CSL_Aif2GSMDataFormat

GSM data type supported.

Use this symbol to specify the GSM type of data on inbound link

Enumerator:

CSL_AIF2_GSM_DATA_OTHER	Not GSM UL
CSL_AIF2_GSM_DATA_UL	GSM UL, has special OBSAI Time Stamp implications. UL time stamp format msb=1 first four msg

enum CSL_Aif2HwControlCmd

This is the set of control commands that are passed to CSL_aif2HwControl(), with an optional argument type-casted to void*

The arguments, if any, to be passed with each command are specified next to that command.

Enumerator:

CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK	Starts a Rx link. use hAif2->arg_link to select link (argument type: Bool * )
CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK	Starts a Tx link. use hAif2->arg_link to select link (argument type: Bool * )
CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK	Enable loopback mode for specific link. use hAif2->arg_link to select link (argument type: Bool * )
CSL_AIF2_CMD_ENABLE_DISABLE_SD_B8_PLL	Enable SD B8 PLL (argument type: Bool * )
CSL_AIF2_CMD_ENABLE_DISABLE_SD_B4_PLL	Enable SD B4 PLL (argument type: Bool * )
CSL_AIF2_CMD_VC_EMU_CONTROL	Control Aif2 Emulation (argument type: CSL_Aif2VcEmu*)
CSL_AIF2_CMD_SD_LINK_TX_TEST_PATTERN	Select Serdes link Tx test pattern (argument type: CSL_Aif2SdTestPattern *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_SD_LINK_RX_TEST_PATTERN	Select Serdes link Rx test pattern (argument type: CSL_Aif2SdTestPattern *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_RM_FORCE_STATE	Force RM Sync State (argument type: CSL_Aif2RmSyncState *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_TM_L1_INBAND_SET	TM L1 Inband Control Signal Set (argument type: Uint8 *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_TM_FLUSH_FIFO	Force TM Flush FIFO (argument type: Bool *)
CSL_AIF2_CMD_TM_IDLE	Force TM Idle state (argument type: Bool *)
CSL_AIF2_CMD_TM_RESYNC	Force TM Resync state (argument type: Bool *)
CSL_AIF2_CMD_PD_CPRI_ID_LUT_SETUP	Dynamic configuration of PD CPRI id lut register (argument type: CSL_Aif2PdCpriIdLut *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_PD_CPRI_CW_LUT_SETUP	Dynamic configuration of PD CPRI Control Word lut register (argument type: CSL_Aif2PdCpriCwLut *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_PD_LINK_DBMR_SETUP	Dynamic configuration of PD DBMR (argument type: CSL_Aif2DualbitMap *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_PD_CH_CONFIG_SETUP	Dynamic configuration of PD channel config registers (argument type: CSL_Aif2PdChannelConfig *)
CSL_AIF2_CMD_PE_CPRI_CW_LUT_SETUP	Dynamic configuration of PE CPRI Control Word lut register (argument type: CSL_Aif2CpriCwLut *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_PE_OBSAI_HEADER_SETUP	Dynamic configuration of PE OBSAI header register (argument type: CSL_Aif2PeObsaiHeader *, use hAif2->arg_link to select link)
CSL_AIF2_CMD_PE_LINK_DBMR_SETUP	Dynamic configuration of PE DBMR (argument type: CSL_Aif2DualbitMap *)
CSL_AIF2_CMD_PE_MODULO_RULE_SETUP	Dynamic configuration of PE Modulo rule (argument type: CSL_Aif2DualbitMap *)
CSL_AIF2_CMD_PE_CH_CONFIG_SETUP	Dynamic configuration of PE channel config registers (argument type: CSL_Aif2PeChannelConfig *)
CSL_AIF2_CMD_PE_CH_RULE_LUT_SETUP	Dynamic configuration of PE channel rule LUT config registers (argument type: CSL_Aif2PeChRuleLut *)
CSL_AIF2_CMD_ENABLE_DISABLE_LINK_DATA_CAPTURE	Enables Trace data and framing data capture (use hAif2->arg_link to select link, argument type: Bool *)
CSL_AIF2_CMD_ENABLE_DISABLE_DATA_TRACE_SYNC	Data Trace Synchronization with Frame boundary Enable (argument type: Bool *)
CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_DEBUG_MODE	Enables Ingress DB Debug mode (argument type: Bool *)
CSL_AIF2_CMD_DB_IN_DEBUG_DATA_SETUP	Debug data written to bits 128:0 of Ingress DB RAM (argument type: Uint32 *)
CSL_AIF2_CMD_DB_IN_DEBUG_SIDE_DATA_SETUP	Ingress DB debug side band data setup (argument type: CSL_Aif2DbSideDatal *)
CSL_AIF2_CMD_DB_IN_DEBUG_WRITE	Writes the data in the following registers into the Ingress DB and sideband RAMS DB_IDB_DEBUG_D0, DB_IDB_DEBUG_D1, DB_IDB_DEBUG_D2, DB_IDB_DEBUG_D3, DB_IDB_DEBUG_SBDN (argument type: Bool *)
CSL_AIF2_CMD_DB_IN_DEBUG_OFFSET_ADDR	Set Read and Write Address used to access write or read Offset RAM for DB Debug (argument type: Uint8 * arg[0] : write offset addr arg[1] : read offset addr)
CSL_AIF2_CMD_DB_IN_ENABLE_DISABLE_CHANNEL	Enable or Disable Ingress DB channel to add or remove channel dynamically (argument type: Uint32 *)
CSL_AIF2_CMD_DB_IN_CHANNEL_SETUP	Setup Ingress DB channel to add or remove channel dynamically (argument type: CSL_Aif2DbChannel *)
CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_DEBUG_MODE	Enables Egress DB Debug mode (argument type: Bool *)
CSL_AIF2_CMD_DB_E_DEBUG_READ_CONTROL	Setup Side band data control info like dio and fifo write enable and channel id and dio base address.(argument type: CSL_Aif2DbSideData *)
CSL_AIF2_CMD_DB_E_DEBUG_WRITE_TOKEN	the value loaded into DB_EDB_DEBUG_RD_CNTL.CH_ID being issued to the AxC Token FIFO.(argument type: Bool *)
CSL_AIF2_CMD_DB_E_DEBUG_READ	Read the data in the following registers from the Egress DB and sideband RAMS DB_EDB_DEBUG_D0, DB_EDB_DEBUG_D1, DB_EDB_DEBUG_D2, DB_EDB_DEBUG_D3, DB_EDB_DEBUG_SBDN (argument type: Bool *)
CSL_AIF2_CMD_DB_E_DEBUG_OFFSET_ADDR	Set Read and Write Address used to access write or read Offset RAM for DB Debug (argument type: Uint8 * arg[0] : write offset addr arg[1] : read offset addr)
CSL_AIF2_CMD_DB_E_ENABLE_DISABLE_CHANNEL	Enable or Disable Egress DB channel to add or remove channel dynamically (argument type: Uint32 *)
CSL_AIF2_CMD_DB_E_CHANNEL_SETUP	Setup Egress DB channel to add or remove channel dynamically (argument type: CSL_Aif2DbChannel *)
CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL	Enable or Disable IN Global AD module dynamically (argument type: Bool *)
CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL	Enable or Disable E Global AD module dynamically (argument type: Bool *)
CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_DIO_GLOBAL	Enable or Disable Global Ingress DIO mode dynamically (argument type: Bool *)
CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_DIO_GLOBAL	Enable or Disable Global Egress DIO mode dynamically (argument type: Bool *)
CSL_AIF2_CMD_AD_IN_DIO_TABLE_SELECT	Change Ingress DIO table selection dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_IN_DIO_NUM_AXC_CHANGE	Change Ingress DIO num of AxC dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_IN_DIO_BCN_TABLE_CHANGE	Change Ingress DIO BCN table dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_E_DIO_TABLE_SELECT	Change Egress DIO table selection dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_E_DIO_NUM_AXC_CHANGE	Change Egress DIO num of AxC dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_E_DIO_BCN_TABLE_CHANGE	Change Egress DIO BCN table dynamically (use hAif2->arg_dioEngine to select dio engine. argument type: Uint8 *)
CSL_AIF2_CMD_AD_TRACE_DATA_DMA_CHANNEL_ON_OFF	Set Enable or disable Data trace DMA for data and framing data (argument type: Bool *)
CSL_AIF2_CMD_AD_TRACE_DATA_BASE_ADDR	Set Trace data base address (argument type: Uint32 *)
CSL_AIF2_CMD_AD_TRACE_FRAMING_DATA_BASE_ADDR	Set trace framing data base address (argument type: Uint32 *)
CSL_AIF2_CMD_AD_TRACE_CPPI_DMA_BURST_WRAP	Sets the number of burst transfers before the destination address wraps back to the base address (argument type: Uint8 *)
CSL_AIF2_CMD_AT_EVENT_SETUP	Sets AT External Rad timer event dynamically (argument type: CSL_Aif2AtEvent *)
CSL_AIF2_CMD_AT_DELTA_SETUP	Sets AT Delta offset (use hAif2->arg_link to select link argument type: CSL_Aif2AtEvent *)
CSL_AIF2_CMD_AT_HALT_TIMER	Sets AT Halt timer (argument type: Bool *)
CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS	Sets AT diable all events for debug purpose (argument type: Bool *)
CSL_AIF2_CMD_AT_ARM_TIMER	Sets AT Arm timer (argument type: Bool *)
CSL_AIF2_CMD_AT_DEBUG_SYNC	Sets AT SW debug sync (argument type: Bool *)
CSL_AIF2_CMD_AT_RAD_WCDMA_DIV	Sets AT radt wcdma clock divider terminal count (argument type: Uint8 *)
CSL_AIF2_CMD_AT_RAD_TC_SETUP	Sets AT Rad terminal count (argument type: CSL_Aif2AtTcObj *)
CSL_AIF2_CMD_AT_GSM_TCOUNT_SETUP	Sets AT GSM Tcount (argument type: CSL_Aif2AtGsmTCount *)
CSL_AIF2_CMD_AT_ENABLE_EVENT	Enable Eight Rad and Six DIO Events (argument type: CSL_Aif2AtEventIndex *)
CSL_AIF2_CMD_AT_DISABLE_EVENT	Disable Eight Rad and Six DIO Events (argument type: CSL_Aif2AtEventIndex *)
CSL_AIF2_CMD_AT_FORCE_EVENT	Force set Eight Rad and Six DIO Events (argument type: CSL_Aif2AtEventIndex *)
CSL_AIF2_CMD_EE_EOI_SETUP	EE End of interrupt vector value setup (argument type: Uint8 *)
CSL_AIF2_CMD_EE_AIF2_ERROR_INT	EE VB error interrupt set or clear (use hAif2->ee_arg to select between set and clear argument type: CSL_Aif2EeAif2IntSetup *)
CSL_AIF2_CMD_EE_DB_INT	EE DB interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeDbIntSetup *)
CSL_AIF2_CMD_EE_AD_INT	EE AD interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeAdIntSetup *)
CSL_AIF2_CMD_EE_CD_INT	EE CD(CDMA module) interrupt set, clear, enable set or clear for EV0 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeCdIntSetup *)
CSL_AIF2_CMD_EE_SD_INT	EE SD interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeSdIntSetup *)
CSL_AIF2_CMD_EE_VC_INT	EE VC interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeVcIntSetup *)
CSL_AIF2_CMD_EE_AIF2_RUN	EE Aif2 run control register setup (argument type: CSL_Aif2EeAif2RunSetup *)
CSL_AIF2_CMD_EE_LINKA_INT	EE Link A interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeLinkAIntSetup *)
CSL_AIF2_CMD_EE_LINKB_INT	EE Link B interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeLinkBIntSetup *)
CSL_AIF2_CMD_EE_AT_INT	EE AT interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EeAtInt *)
CSL_AIF2_CMD_EE_PD_INT	EE PD common interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EePdInt *)
CSL_AIF2_CMD_EE_PE_INT	EE PE common interrupt set, clear, enable set or clear for EV0 and EV1 (use hAif2->ee_arg to select function argument type: CSL_Aif2EePeInt *)

enum CSL_Aif2HwStatusQuery

This is the set of query commands to get the status of various operations in AIF2

The arguments, if any, to be passed with each command are specified next to that command.

Enumerator:

CSL_AIF2_QUERY_VERSION

Get the version of the module accessed

Parameters:

(CSL_Aif2PidStatus

CSL_AIF2_QUERY_VC_STAT

returns VC Emu status

CSL_AIF2_QUERY_SD_RX_LINK_STATUS

SERDES Rx Status

Parameters:

(CSL_Aif2SdRxStatus

CSL_AIF2_QUERY_SD_TX_LINK_STATUS

SERDES Tx Status

Parameters:

(CSL_Aif2SdTxStatus

CSL_AIF2_QUERY_SD_B8_PLL_LOCK

Return the status of SERDES B8 PLL lock.

Parameters:

(Uint8

CSL_AIF2_QUERY_SD_B4_PLL_LOCK

Return the status of SERDES B4 PLL lock.

Parameters:

(Uint8

CSL_AIF2_QUERY_RM_LINK_STATUS_0

RM link Status 0. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RmStatus0

CSL_AIF2_QUERY_RM_LINK_STATUS_1

RM link Status 1. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RmStatus1

CSL_AIF2_QUERY_RM_LINK_STATUS_2

RM link Status 2. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RmStatus2

CSL_AIF2_QUERY_RM_LINK_STATUS_3

RM link Status 3. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RmStatus3

CSL_AIF2_QUERY_RM_LINK_STATUS_4

RM link Status 4. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RmStatus4

CSL_AIF2_QUERY_TM_LINK_CPRI_HFN

Return TM link CPRI HFN Status. use hAif2->arg_link to choose link.

Parameters:

(Uint8

CSL_AIF2_QUERY_TM_LINK_STATUS

TM link Status. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2TmStatus

CSL_AIF2_QUERY_RT_FIFO_DEPTH_STATUS

RT Internal FIFO depth Status. use hAif2->arg_link to choose link.

Parameters:

(Uint8

CSL_AIF2_QUERY_RT_HEADER_ERROR_STATUS

RT Header Error Status. use hAif2->arg_link to choose link.

Parameters:

(CSL_Aif2RtHeaderStatus

CSL_AIF2_QUERY_RT_LINK_STATUS

Get the status of the Retransmitter

Parameters:

(CSL_Aif2RtStatus

CSL_AIF2_QUERY_PD_CHANNEL_STATUS

PD 128 Channel Status.

Parameters:

(Uint32

CSL_AIF2_QUERY_PD_PACKET_STATUS

PD Packet Status for 128 channels if it is in or out of packet.

Parameters:

(Uint32

CSL_AIF2_QUERY_PE_CHANNEL_STATUS

PE 128 Channel Status.

Parameters:

(Uint32

CSL_AIF2_QUERY_PE_PACKET_STATUS

PE Packet Status for 128 channels if it is in or out of packet.

Parameters:

(Uint32

CSL_AIF2_QUERY_DB_IN_DEBUG_OFFSET_DATA

Get Write and Read Offset Value at address in DB_IDB_DEBUG_OFS

Parameters:

(Uint8

CSL_AIF2_QUERY_DB_E_DEBUG_DATA

Get Debug data written to bits 128:0 of Egress DB RAM

Parameters:

(Uint32

CSL_AIF2_QUERY_DB_E_DEBUG_SIDE_DATA

Get Egress DB debug side band data setup

Parameters:

(CSL_Aif2DbSideData

CSL_AIF2_QUERY_DB_E_DEBUG_OFFSET_DATA

Get Write and Read Offset Value at address in DB_EDB_DEBUG_OFS

Parameters:

(Uint8

CSL_AIF2_QUERY_DB_E_EOP_COUNT

Get Egress EOP count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AD_I_EOP_COUNT

Get Ingress EOP count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_LINK_PI_CAPTURE

Get Aif2 timer link Pi captured value. use hAif2->arg_link to choose link

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RADT_CAPTURE

Get Aif2 timer capture Radt values

Parameters:

(CSL_Aif2AtCaptRadt

CSL_AIF2_QUERY_AT_RP1_TYPE_CAPTURE

Get Aif2 timer RP1 type capture value

Parameters:

(Uint8

CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_LSB

Get Aif2 timer RP1 tod capture lsb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RP1_TOD_CAPTURE_MSB

Get Aif2 timer RP1 tod capture msb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_LSB

Get Aif2 timer RP1 RP3 capture lsb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RP1_RP3_CAPTURE_MSB

Get Aif2 timer RP1 RP3 capture msb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_LSB

Get Aif2 timer RP1 RAD capture lsb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RP1_RAD_CAPTURE_MSB

Get Aif2 timer RP1 RAD capture msb value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_PHY_CLOCK_COUNT

Get Aif2 Phy timer clock count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_LSB

Get Aif2 Phy timer frame count value lsb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_PHY_FRAME_COUNT_MSB

Get Aif2 Phy timer frame count value msb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RAD_CLOCK_COUNT

Get Aif2 Rad timer clock count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RAD_SYMBOL_COUNT

Get Aif2 Rad timer symbol count value

Parameters:

(Uint8

CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_LSB

Get Aif2 Rad timer frame count value lsb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RAD_FRAME_COUNT_MSB

Get Aif2 Rad timer frame count value msb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_ULRAD_CLOCK_COUNT

Get Aif2 Ul Rad timer clock count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_ULRAD_SYMBOL_COUNT

Get Aif2 Ul Rad timer symbol count value

Parameters:

(Uint8

CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_LSB

Get Aif2 Ul Rad timer frame count value lsb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_ULRAD_FRAME_COUNT_MSB

Get Aif2 Ul Rad timer frame count value msb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_DLRAD_CLOCK_COUNT

Get Aif2 Dl Rad timer clock count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_DLRAD_SYMBOL_COUNT

Get Aif2 Dl Rad timer symbol count value

Parameters:

(Uint8

CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_LSB

Get Aif2 Dl Rad timer frame count value lsb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_DLRAD_FRAME_COUNT_MSB

Get Aif2 Dl Rad timer frame count value msb

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_RAD_WCDMA_VALUE

Get Aif2 Rad timer WCDMA chip count value

Parameters:

(CSL_Aif2AtWcdmaCount

CSL_AIF2_QUERY_AT_ULRAD_WCDMA_VALUE

Get Aif2 Ul Rad timer WCDMA chip count value

Parameters:

(CSL_Aif2AtWcdmaCount

CSL_AIF2_QUERY_AT_DLRAD_WCDMA_VALUE

Get Aif2 Dl Rad timer WCDMA chip count value

Parameters:

(CSL_Aif2AtWcdmaCount

CSL_AIF2_QUERY_AT_RAD_TSTAMP_CLOCK_COUNT

Get Aif2 Rad timer time stamp clock count value

Parameters:

(Uint32

CSL_AIF2_QUERY_AT_GSM_TCOUNT_VALUE

Get Aif2 GSM Tcount value

Parameters:

(CSL_Aif2AtGsmTCount

CSL_AIF2_QUERY_EE_DB_INT_STATUS

Get Aif2 EE DB interrupt status value

Parameters:

(CSL_Aif2EeDbInt

CSL_AIF2_QUERY_EE_AD_INT_STATUS

Get Aif2 EE AD interrupt status value

Parameters:

(CSL_Aif2EeAdInt

CSL_AIF2_QUERY_EE_CD_INT_STATUS

Get Aif2 EE CD(CDMA) interrupt status value

Parameters:

(CSL_Aif2EeCdInt

CSL_AIF2_QUERY_EE_SD_INT_STATUS

Get Aif2 EE SD interrupt status value

Parameters:

(CSL_Aif2EeSdInt

CSL_AIF2_QUERY_EE_VC_INT_STATUS

Get Aif2 EE VC interrupt status value

Parameters:

(CSL_Aif2EeVcInt

CSL_AIF2_QUERY_EE_AIF2_RUN_STATUS

Get Aif2 EE AIF2 run status value

Parameters:

(CSL_Aif2EeAif2Run

CSL_AIF2_QUERY_EE_AIF2_ORIGINATION

Get Aif2 EE error or alarm origination

Parameters:

(CSL_Aif2EeAif2Run

CSL_AIF2_QUERY_EE_LINKA_INT_STATUS

Get Aif2 EE Link A interrupt status value

Parameters:

(CSL_Aif2EeLinkAInt

*) use hAif2->ee_arg to select function and hAif2->arg_link to select link

CSL_AIF2_QUERY_EE_LINKB_INT_STATUS

Get Aif2 EE Link B interrupt status value

Parameters:

(CSL_Aif2EeLinkBInt

*) use hAif2->ee_arg to select function and hAif2->arg_link to select link

CSL_AIF2_QUERY_EE_AT_INT_STATUS

Get Aif2 EE AT interrupt status value

Parameters:

(CSL_Aif2EeAtInt

*) use hAif2->ee_arg to select function

enum CSL_Aif2LinkDataType

Link data type supported.

Use this symbol to specify the type of data on inbound/outbound link

Enumerator:

CSL_AIF2_LINK_DATA_TYPE_NORMAL	Selects the link data type as downlink, generic
CSL_AIF2_LINK_DATA_TYPE_RSA	Selects the link data type as uplink

enum CSL_Aif2LinkIndex

aif2 link indices supported

Use this symbol to specify the aif2 link index

Enumerator:

CSL_AIF2_LINK_0	Selects link0
CSL_AIF2_LINK_1	Selects link1
CSL_AIF2_LINK_2	Selects link2
CSL_AIF2_LINK_3	Selects link3
CSL_AIF2_LINK_4	Selects link4
CSL_AIF2_LINK_5	Selects link5
CSL_AIF2_NO_LINK	Selects no link

enum CSL_Aif2LinkProtocol

Link Protocol supported.

Use this symbol to specify link formats for AIF2

Enumerator:

CSL_AIF2_LINK_PROTOCOL_CPRI	Selects the CPRI protocol
CSL_AIF2_LINK_PROTOCOL_OBSAI	Selects the OBSAI protocol

enum CSL_Aif2LinkRate

link rates supported

Use this symbol to specify the link rate

Enumerator:

CSL_AIF2_LINK_RATE_8x	Selects 8X link rate
CSL_AIF2_LINK_RATE_4x	Selects 4X link rate
CSL_AIF2_LINK_RATE_2x	Selects 2X link rate
CSL_AIF2_LINK_RATE_5x	Selects 5X link rate only for CPRI

enum CSL_Aif2ObsaiTsMask

PD or PE Obsai time stamp mask supported.

Enumerator:

CSL_AIF2_TSTAMP_MASK_FULL_GEN	All TS bits are genrated, not inserted
CSL_AIF2_TSTAMP_MASK_4INS_2GEN	4 lsb bits of TS are inserted, 2 msb are generated
CSL_AIF2_TSTAMP_MASK_FULL_INS	All TS(5:0) bits are inserted

enum CSL_Aif2PdDataMode

dicates the payload is to be used as AxC (normal) or Packet traffic

Enumerator:

CSL_AIF2_PD_DATA_AXC	Use AxC data
CSL_AIF2_PD_DATA_PKT	Use Packet data

enum CSL_Aif2PdWatchDogReport

Report every missed WDog fail, or report only fails of missing EOP.

Enumerator:

CSL_AIF2_PD_WD_REPORT_ALL	WD Report all
CSL_AIF2_PD_WD_REPORT_EOP	WD report EOP only

enum CSL_Aif2PeRtContol

Controls RT to perform appropriate insterion/aggregation into PHY.

Use this symbol to specify RT control for PE

Enumerator:

CSL_AIF2_PE_RT_RETRANS	Retransmit mode
CSL_AIF2_PE_RT_INSERT	PE Insert mode
CSL_AIF2_PE_RT_ADD8	aggregate 8 bit mode
CSL_AIF2_PE_RT_ADD16	aggregate 16 bit mode

enum CSL_Aif2PllMpyFactor

Sd module index.

Use this symbol to specify the Sd PLL multiply factor

Enumerator:

CSL_AIF2_PLL_MUL_FACTOR_4X	Select 4x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_5X	Select 5x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_6X	Select 6x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_8X	Select 8x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_8_25X	Select 8.25x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_10X	Select 10x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_12X	Select 12x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_12_5X	Select 12.5x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_15X	Select 15x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_16X	Select 16x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_16_5X	Select 16.5x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_20X	Select 20x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_22X	Select 22x PLL multiply factor
CSL_AIF2_PLL_MUL_FACTOR_25X	Select 25x PLL multiply factor

enum CSL_Aif2RmErrorSuppress

Suppress error reporting when the receiver state machine is not in state ST3.

Enumerator:

CSL_AIF2_RM_ERROR_ALLOW	Allow all RM error reporting when not in ST3
CSL_AIF2_RM_ERROR_SUPPRESS	Suppress all RM error reporting when not in ST3

enum CSL_Aif2RmFifoThold

setup Rm fifo threshold word size for reading received data

Enumerator:

CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY	FIFO starts reading immediately
CSL_AIF2_RM_FIFO_THOLD_4DUAL	FIFO starts reading after 4 dual words received
CSL_AIF2_RM_FIFO_THOLD_8DUAL	FIFO starts reading after 8 dual words received
CSL_AIF2_RM_FIFO_THOLD_16DUAL	FIFO starts reading after 16 dual words received

enum CSL_Aif2RmSyncState

RM sync states.

Use this symbol to specify the state of the RM state machine

Enumerator:

CSL_AIF2_RM_ST_0	Selects the RM state 0
CSL_AIF2_RM_ST_1	Selects the RM state 1
CSL_AIF2_RM_ST_2	Selects the RM state 2
CSL_AIF2_RM_ST_3	Selects the RM state 3
CSL_AIF2_RM_ST_4	Selects the RM state 4
CSL_AIF2_RM_ST_5	Selects the RM state 5

enum CSL_Aif2RouteMask

controls how many OBSAI time stamp bits to use in the reception routing.

Use this symbol to specify the masking value for time stamp

Enumerator:

CSL_AIF2_ROUTE_MASK_NONE	Do not use the TS field for routing
CSL_AIF2_ROUTE_MASK_4LSB	4 lsb bits: Use TS(3:0)
CSL_AIF2_ROUTE_MASK_ALL	all Use TS(5:0)
CSL_AIF2_ROUTE_MASK_RESERVED	Reserved

enum CSL_Aif2RtConfig

Retransmitter Mode used.

Use this symbol to specify the retransmitter mode

Enumerator:

CSL_AIF2_RT_MODE_RETRANSMIT	RT takes RM input only
CSL_AIF2_RT_MODE_AGGREGATE	Aggregate or Merge data from PE and CI
CSL_AIF2_RT_MODE_TRANSMIT	RT takes PE input only

enum CSL_Aif2SdClockBypass

Sd pll clock bypass selection.

Use this symbol to specify the Sd PLL clock bypass

enum CSL_Aif2SdLoopBandwidth

Sd pll loop bandwidth selection.

Use this symbol to specify the Sd PLL loop bandwidth

Enumerator:

CSL_AIF2_PLL_LOOP_BAND_MID	set pll loop bandwidth mid
CSL_AIF2_PLL_LOOP_BAND_UHIGH	set pll loop bandwidth ultra high
CSL_AIF2_PLL_LOOP_BAND_LOW	set pll loop bandwidth low
CSL_AIF2_PLL_LOOP_BAND_HIGH	set pll loop bandwidth high

enum CSL_Aif2SdRxAlign

Sd module rx alignment.

Enumerator:

CSL_AIF2_SD_RX_ALIGNMENT_DISABLE	No symbol alignment will be performed whilst this setting is selected, or when switching to this selection from another
CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE	Symbol alignment will be performed whenever a misaligned comma symbol is received.
CSL_AIF2_SD_RX_ALIGNMENT_JOG	The symbol alignment will be adjusted by one bit position when this mode is selected

enum CSL_Aif2SdRxCdrAlg

Sd clock recovery algorithm.

Use this symbol to specify the Sd Rx clock recovery algorithm

Enumerator:

CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1	Phase offset tracking upto ¡¾488ppm. Suitable for use in asynchronous systems with low frequency offset
CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_17	Phase offset tracking upto ¡¾325ppm. Suitable for use in synchronous systems. Offers superiour rejection of random jitter, but is less responsive to systematic variation such as sinusoidal jitter
CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_1	As per setting 000, but the algorithm is only enabled periodically to reduce power
CSL_AIF2_SD_RX_CDR_FO_PERIODIC_THRESH_17	As per setting 001, but the algorithm is only enabled periodically to reduce power

enum CSL_Aif2SdRxEqConfig

Sd module index.

Use this symbol to specify the Sd Rx adaptive equalizer

Enumerator:

CSL_AIF2_SD_RX_EQ_MAXIMUM	Selects the maximum Receiver equalizer
CSL_AIF2_SD_RX_EQ_ADAPTIVE	Selects the adaptive Receiver equalizer
CSL_AIF2_SD_RX_EQ_PRECURSOR	Selects the Precursor equalization analysis
CSL_AIF2_SD_RX_EQ_POSTCURSOR	Selects the Postcursor equalization analysis

enum CSL_Aif2SdRxInvertPolarity

Sd module index.

Use this symbol to specify the Sd Rx invert polarity

Enumerator:

CSL_AIF2_SD_RX_NORMAL_POLARITY	Selects the Receive pair normal polarity
CSL_AIF2_SD_RX_INVERTED_POLARITY	Selects the Receive pair inverted polarity

enum CSL_Aif2SdRxLos

Sd module rx LOS.

Enumerator:

CSL_AIF2_SD_RX_LOS_DISABLE	Loss of signal detection disabled
CSL_AIF2_SD_RX_LOS_ENABLE	Loss of signal detection enabled.

enum CSL_Aif2SdRxTerm

Sd module index.

Use this symbol to specify the Serdes Rx termination

Enumerator:

CSL_AIF2_SD_RX_TERM_COMMON_POINT_VDDT	This configuration is for DC coupled systems using CML transmitters
CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7	This configuration is for AC coupled systems. The transmitter has no effect on the receiver common mode
CSL_AIF2_SD_RX_TERM_COMMON_POINT_FLOATING	This configuration is for DC coupled systems which require the common mode voltage to be determined by the transmitter only.

enum CSL_Aif2SdSleepPll

Sd pll sleep.

Use this symbol to specify the Sd PLL sleep mode

Enumerator:

CSL_AIF2_PLL_AWAKE	PLL awake
CSL_AIF2_PLL_SLEEP	PLL sleep

enum CSL_Aif2SdTestPattern

Sd link test pattern index.

Enumerator:

CSL_AIF2_SD_TEST_DISABLED	Test mode disabled
CSL_AIF2_SD_ALTERNATING_0_1	Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2UI
CSL_AIF2_SD_PRBS_7BIT_LFSR	Generate or Verify 27 . 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x7 + x6 + 1
CSL_AIF2_SD_PRBS_23BIT_LFSR	Generate or Verify 223.1 PRBS. Uses a 23-bit LFSR with feedback polynomial x23 + x18 + 1
CSL_AIF2_SD_PRBS_31BIT_LFSR	Generate or Verify 223.1 PRBS. Uses a 23-bit LFSR with feedback polynomial x23 + x18 + 1

enum CSL_Aif2SdTxInvertPolarity

Sd module index.

Use this symbol to specify the Sd Tx polarity

Enumerator:

CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY	Selects Tx pair normal polarity
CSL_AIF2_SD_TX_PAIR_INVERTED_POLARITY	Selects Tx pair inverted polarity

enum CSL_Aif2SdTxOutputSwing

Sd module index.

Use this symbol to specify the Sd Tx output swing

Enumerator:

CSL_AIF2_SD_TX_OUTPUT_SWING_0	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_1	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_2	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_3	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_4	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_5	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_6	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_7	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_8	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_9	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_10	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_11	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_12	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_13	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_14	Selects tx output swing amplitude
CSL_AIF2_SD_TX_OUTPUT_SWING_15	Selects tx output swing amplitude

enum CSL_Aif2SdTxPostcursorTabWeight

Sd module index.

Use this symbol to specify the Sd Tx post cursor tab weight

Enumerator:

CSL_AIF2_SD_TX_POST_TAP_WEIGHT_0	Post-cursor Transmit tap weights to 0 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_1	Post-cursor Transmit tap weights to 2.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_2	Post-cursor Transmit tap weights to 5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_3	Post-cursor Transmit tap weights to 7.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_4	Post-cursor Transmit tap weights to 10 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_5	Post-cursor Transmit tap weights to 12.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_6	Post-cursor Transmit tap weights to 15 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_7	Post-cursor Transmit tap weights to 17.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_8	Post-cursor Transmit tap weights to 20 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_9	Post-cursor Transmit tap weights to 22.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_10	Post-cursor Transmit tap weights to 25 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_11	Post-cursor Transmit tap weights to 27.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_12	Post-cursor Transmit tap weights to 30 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_13	Post-cursor Transmit tap weights to 32.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_14	Post-cursor Transmit tap weights to 35 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_15	Post-cursor Transmit tap weights to 37.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_16	Post-cursor Transmit tap weights to 0 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_17	Post-cursor Transmit tap weights to -2.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_18	Post-cursor Transmit tap weights to - 5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_19	Post-cursor Transmit tap weights to -7.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_20	Post-cursor Transmit tap weights to -10 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_21	Post-cursor Transmit tap weights to -12.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_22	Post-cursor Transmit tap weights to -15 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_23	Post-cursor Transmit tap weights to -17.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24	Post-cursor Transmit tap weights to -20 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_25	Post-cursor Transmit tap weights to -22.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_26	Post-cursor Transmit tap weights to - 25 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_27	Post-cursor Transmit tap weights to -27.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_28	Post-cursor Transmit tap weights to -30 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_29	Post-cursor Transmit tap weights to -32.5 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_30	Post-cursor Transmit tap weights to -35 %
CSL_AIF2_SD_TX_POST_TAP_WEIGHT_31	Post-cursor Transmit tap weights to -37.5 %

enum CSL_Aif2SdTxPrecursorTabWeight

Sd module index.

Use this symbol to specify the Sd Tx precursor tab weight

Enumerator:

CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_0	Pre-cursor Transmit tap weights to 0 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_1	Pre-cursor Transmit tap weights to -2.5 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2	Pre-cursor Transmit tap weights to - 5 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_3	Pre-cursor Transmit tap weights to -7.5 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_4	Pre-cursor Transmit tap weights to -10 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_5	Pre-cursor Transmit tap weights to -12.5 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_6	Pre-cursor Transmit tap weights to -15 %
CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_7	Pre-cursor Transmit tap weights to -17.5 %

enum CSL_Aif2SdVoltRange

Sd pll voltage range.

Use this symbol to specify the Sd PLL voltage range

Enumerator:

CSL_AIF2_PLL_VOLTAGE_LOW	Use low voltage for PLL
CSL_AIF2_PLL_VOLTAGE_HIGH	Use high voltage for PLL

enum CSL_Aif2TmSyncState

TM states.

Use this symbol to specify the state of the TM state machine

Enumerator:

CSL_AIF2_TM_ST_OFF	Selects the TM state Off
CSL_AIF2_TM_ST_IDLE	Selects the TM state idle
CSL_AIF2_TM_ST_RE_SYNC	Selects the TM state re-sync
CSL_AIF2_TM_ST_FRAME_SYNC	Selects the TM state frame sync

enum CSL_Aif2TstampFormat

PD or PE time stamp format supported.

Enumerator:

CSL_AIF2_TSTAMP_FORMAT_NO_TS	Selects the link time stamp format as no time stamp check
CSL_AIF2_TSTAMP_FORMAT_NORM_TS	Selects the link time stamp format as normal time stamp
CSL_AIF2_TSTAMP_FORMAT_GSM	Selects the link time stamp format as GSM OBSAI time stamp (UL time stamp for PE)
CSL_AIF2_TSTAMP_FORMAT_GEN_PKT	Selects the link time stamp format for generic packet (SOP = 10, MOP = 00, EOP = 11)
CSL_AIF2_TSTAMP_FORMAT_ETHERNET	Selects the link time stamp format for ethernet
CSL_AIF2_TSTAMP_FORMAT_ROUTE_CHECK	Selects the link time stamp format, which value is checked by PD or PE route
CSL_AIF2_TSTAMP_FORMAT_GSM_DL	Selects the link time stamp format as GSM DL OBSAI time stamp (only used for PE)

AIF2 Enumerated Data Types [AIF2]

Enumerations

Enumeration Type Documentation

AIF2 Enumerated Data Types
[AIF2]