EDMA3 Enumerated Data Types
[EDMA3]


Enumerations

enum  CSL_Edma3QuePri {
  CSL_EDMA3_QUE_PRI_0 = 0, CSL_EDMA3_QUE_PRI_1 = 1, CSL_EDMA3_QUE_PRI_2 = 2, CSL_EDMA3_QUE_PRI_3 = 3,
  CSL_EDMA3_QUE_PRI_4 = 4, CSL_EDMA3_QUE_PRI_5 = 5, CSL_EDMA3_QUE_PRI_6 = 6, CSL_EDMA3_QUE_PRI_7 = 7
}
 Enumeration for System priorities. More...
enum  CSL_Edma3Que {
  CSL_EDMA3_QUE_DEFAULT = 0, CSL_EDMA3_QUE_0 = 0, CSL_EDMA3_QUE_1 = 1, CSL_EDMA3_QUE_2 = 2,
  CSL_EDMA3_QUE_3 = 3, CSL_EDMA3_QUE_4 = 4, CSL_EDMA3_QUE_5 = 5, CSL_EDMA3_QUE_6 = 6,
  CSL_EDMA3_QUE_7 = 7
}
 Enumeration for EDMA Event Queues. More...
enum  CSL_Edma3QueThr {
  CSL_EDMA3_QUE_THR_0 = 0, CSL_EDMA3_QUE_THR_1 = 1, CSL_EDMA3_QUE_THR_2 = 2, CSL_EDMA3_QUE_THR_3 = 3,
  CSL_EDMA3_QUE_THR_4 = 4, CSL_EDMA3_QUE_THR_5 = 5, CSL_EDMA3_QUE_THR_6 = 6, CSL_EDMA3_QUE_THR_7 = 7,
  CSL_EDMA3_QUE_THR_8 = 8, CSL_EDMA3_QUE_THR_9 = 9, CSL_EDMA3_QUE_THR_10 = 10, CSL_EDMA3_QUE_THR_11 = 11,
  CSL_EDMA3_QUE_THR_12 = 12, CSL_EDMA3_QUE_THR_13 = 13, CSL_EDMA3_QUE_THR_14 = 14, CSL_EDMA3_QUE_THR_15 = 15,
  CSL_EDMA3_QUE_THR_16 = 16
}
 Enumeration for EDMA Que Thresholds. More...
enum  CSL_Edma3HwControlCmd {
  CSL_EDMA3_CMD_MEMPROTECT_SET, CSL_EDMA3_CMD_MEMFAULT_CLEAR, CSL_EDMA3_CMD_DMAREGION_ENABLE, CSL_EDMA3_CMD_DMAREGION_DISABLE,
  CSL_EDMA3_CMD_QDMAREGION_ENABLE, CSL_EDMA3_CMD_QDMAREGION_DISABLE, CSL_EDMA3_CMD_QUEPRIORITY_SET, CSL_EDMA3_CMD_QUETHRESHOLD_SET,
  CSL_EDMA3_CMD_ERROR_EVAL, CSL_EDMA3_CMD_INTRPEND_CLEAR, CSL_EDMA3_CMD_INTR_ENABLE, CSL_EDMA3_CMD_INTR_DISABLE,
  CSL_EDMA3_CMD_INTR_EVAL, CSL_EDMA3_CMD_CTRLERROR_CLEAR, CSL_EDMA3_CMD_EVENTMISSED_CLEAR
}
enum  CSL_Edma3HwStatusQuery {
  CSL_EDMA3_QUERY_MEMFAULT, CSL_EDMA3_QUERY_MEMPROTECT, CSL_EDMA3_QUERY_CTRLERROR, CSL_EDMA3_QUERY_INTRPEND,
  CSL_EDMA3_QUERY_EVENTMISSED, CSL_EDMA3_QUERY_QUESTATUS, CSL_EDMA3_QUERY_ACTIVITY, CSL_EDMA3_QUERY_INFO
}
 MODULE Level Queries. More...
enum  CSL_Edma3HwChannelControlCmd {
  CSL_EDMA3_CMD_CHANNEL_ENABLE, CSL_EDMA3_CMD_CHANNEL_DISABLE, CSL_EDMA3_CMD_CHANNEL_SET, CSL_EDMA3_CMD_CHANNEL_CLEAR,
  CSL_EDMA3_CMD_CHANNEL_CLEARERR
}
 CHANNEL Commands. More...
enum  CSL_Edma3HwChannelStatusQuery { CSL_EDMA3_QUERY_CHANNEL_STATUS, CSL_EDMA3_QUERY_CHANNEL_ERR }
 CHANNEL Queries. More...

Enumeration Type Documentation

enum CSL_Edma3HwChannelControlCmd

CHANNEL Commands.

Enumerator:
CSL_EDMA3_CMD_CHANNEL_ENABLE  Enables specified Channel.

Parameters:
(None) 
CSL_EDMA3_CMD_CHANNEL_DISABLE  Disables specified Channel.

Parameters:
(None) 
CSL_EDMA3_CMD_CHANNEL_SET  Manually sets the Channel Event,writes into ESR/ESRH and not ER.NA for QDMA.

Parameters:
(None) 
CSL_EDMA3_CMD_CHANNEL_CLEAR  Manually clears the Channel Event, does not write into ESR/ESRH or ER/ERH but the ECR/ECRH. NA for QDMA.

Parameters:
(None) 
CSL_EDMA3_CMD_CHANNEL_CLEARERR  In case of DMA channels clears SER/SERH(by writing into SECR/SECRH if "secEvt" and "missed" are both TRUE) and EMR/EMRH(by writing into EMCR/EMCRH if "missed" is TRUE). In case of QDMA channels clears QSER(by writing into QSECR if "ser" and "missed" are both TRUE) and QEMR(by writing into QEMCR if "missed" is TRUE).

Parameters:
(CSL_Edma3ChannelErr *)

enum CSL_Edma3HwChannelStatusQuery

CHANNEL Queries.

Enumerator:
CSL_EDMA3_QUERY_CHANNEL_STATUS  In case of DMA channels returns TRUE if ER/ERH is set, In case of QDMA channels returns TRUE if QER is set.

Parameters:
(Bool *)
CSL_EDMA3_QUERY_CHANNEL_ERR  In case of DMA channels,'missed' is set to TRUE if EMR/EMRH is set, 'secEvt' is set to TRUE if SER/SERH is set.In case of QDMA channels,'missed' is set to TRUE if QEMR is set, 'secEvt' is set to TRUE if QSER is set. It should be noted that if secEvt ONLY is set to TRUE it may not be a valid error condition.

Parameters:
(CSL_Edma3ChannelErr *)

enum CSL_Edma3HwControlCmd

MODULE Level Commands

Enumerator:
CSL_EDMA3_CMD_MEMPROTECT_SET  Programmation of MPPAG,MPPA[0-7] attributes.

Parameters:
(CSL_Edma3CmdRegion *)
CSL_EDMA3_CMD_MEMFAULT_CLEAR  Clear Memory Fault.

Parameters:
(None) 
CSL_EDMA3_CMD_DMAREGION_ENABLE  Enables bits as specified in the argument passed in DRAE/DRAEH. Please note:If bits are already set in DRAE/DRAEH this Control command will cause additional bits (as specified by the bitmask) to be set and does.

Parameters:
(CSL_Edma3CmdDrae *)
CSL_EDMA3_CMD_DMAREGION_DISABLE  Disables bits as specified in the argument passed in DRAE/DRAEH.

Parameters:
(CSL_Edma3CmdDrae *)
CSL_EDMA3_CMD_QDMAREGION_ENABLE  Enables bits as specified in the argument passed in QRAE.Pleasenote:If bits are already set in QRAE/QRAEH this Control command will cause additional bits (as specified by the bitmask) to be set and does.

Parameters:
(CSL_Edma3CmdQrae *)
CSL_EDMA3_CMD_QDMAREGION_DISABLE  Disables bits as specified in the argument passed in QRAE DRAE/DRAEH.

Parameters:
(CSL_Edma3CmdQrae *)
CSL_EDMA3_CMD_QUEPRIORITY_SET  Programmation of QUEPRI register with the specified priority DRAE/DRAEH.

Parameters:
(CSL_Edma3CmdQuePri *)
CSL_EDMA3_CMD_QUETHRESHOLD_SET  Programmation of QUE Threshold levels.

Parameters:
(CSL_Edma3CmdQueThr *)
CSL_EDMA3_CMD_ERROR_EVAL  Sets the EVAL bit in the EEVAL register.

Parameters:
(None) 
CSL_EDMA3_CMD_INTRPEND_CLEAR  Clears specified (Bitmask)pending interrupt at Module/Region Level.

Parameters:
(CSL_Edma3CmdIntr *)
CSL_EDMA3_CMD_INTR_ENABLE  Enables specified interrupts(BitMask) at Module/Region Level.

Parameters:
(CSL_Edma3CmdIntr *)
CSL_EDMA3_CMD_INTR_DISABLE  Disables specified interrupts(BitMask) at Module/Region Level.

Parameters:
(CSL_Edma3CmdIntr *)
CSL_EDMA3_CMD_INTR_EVAL  Interrupt Evaluation asserted for the Module/Region.

Parameters:
(Int *)
CSL_EDMA3_CMD_CTRLERROR_CLEAR  Clear the EDMA Controller Erorr.

Parameters:
(CSL_Edma3CtrlErrStat *)
CSL_EDMA3_CMD_EVENTMISSED_CLEAR  Pointer to an array of 3 elements, where element0 refers to the EMR register to be cleared, element1 refers to the EMRH register to be cleared, element2 refers to the QEMR register to be cleared.

Parameters:
(CSL_BitMask32 *)

enum CSL_Edma3HwStatusQuery

MODULE Level Queries.

Enumerator:
CSL_EDMA3_QUERY_MEMFAULT  Return the Memory fault details.

Parameters:
(CSL_Edma3MemFaultStat *)
CSL_EDMA3_QUERY_MEMPROTECT  Return memory attribute of the specified region.

Parameters:
(CSL_Edma3CmdRegion *)
CSL_EDMA3_QUERY_CTRLERROR  Return Controller Error.

Parameters:
(CSL_Edma3CtrlErrStat *)
CSL_EDMA3_QUERY_INTRPEND  Return pend status of specified interrupt.

Parameters:
(CSL_Edma3CmdIntr *)
CSL_EDMA3_QUERY_EVENTMISSED  Returns Miss Status of all Channels Pointer to an array of 3 elements, where element0 refers to the EMR registr, element1 refers to the EMRH register, element2 refers to the QEMR register.

Parameters:
(CSL_BitMask32 *)
CSL_EDMA3_QUERY_QUESTATUS  Returns the Que status.

Parameters:
(CSL_Edma3QueStat *)
CSL_EDMA3_QUERY_ACTIVITY  Returns the Channel Controller Active Status.

Parameters:
(CSL_Edma3ActivityStat *)
CSL_EDMA3_QUERY_INFO  Returns the Channel Controller Information viz. Configuration, Revision Id.

Parameters:
(CSL_Edma3QueryInfo *)

enum CSL_Edma3Que

Enumeration for EDMA Event Queues.

These are a list of all the event queues.

Enumerator:
CSL_EDMA3_QUE_DEFAULT  Default Event Queue
CSL_EDMA3_QUE_0  Event Queue 0
CSL_EDMA3_QUE_1  Event Queue 1
CSL_EDMA3_QUE_2  Event Queue 2
CSL_EDMA3_QUE_3  Event Queue 3
CSL_EDMA3_QUE_4  Event Queue 4
CSL_EDMA3_QUE_5  Event Queue 5
CSL_EDMA3_QUE_6  Event Queue 6
CSL_EDMA3_QUE_7  Event Queue 7

enum CSL_Edma3QuePri

Enumeration for System priorities.

This is used for Setting up the Que Priority level

Enumerator:
CSL_EDMA3_QUE_PRI_0  System priority level 0
CSL_EDMA3_QUE_PRI_1  System priority level 1
CSL_EDMA3_QUE_PRI_2  System priority level 2
CSL_EDMA3_QUE_PRI_3  System priority level 3
CSL_EDMA3_QUE_PRI_4  System priority level 4
CSL_EDMA3_QUE_PRI_5  System priority level 5
CSL_EDMA3_QUE_PRI_6  System priority level 6
CSL_EDMA3_QUE_PRI_7  System priority level 7

enum CSL_Edma3QueThr

Enumeration for EDMA Que Thresholds.

This is used for Setting up the Que thresholds

Enumerator:
CSL_EDMA3_QUE_THR_0  EDMA Que Threshold 0
CSL_EDMA3_QUE_THR_1  EDMA Que Threshold 1
CSL_EDMA3_QUE_THR_2  EDMA Que Threshold 2
CSL_EDMA3_QUE_THR_3  EDMA Que Threshold 3
CSL_EDMA3_QUE_THR_4  EDMA Que Threshold 4
CSL_EDMA3_QUE_THR_5  EDMA Que Threshold 5
CSL_EDMA3_QUE_THR_6  EDMA Que Threshold 6
CSL_EDMA3_QUE_THR_7  EDMA Que Threshold 7
CSL_EDMA3_QUE_THR_8  EDMA Que Threshold 8
CSL_EDMA3_QUE_THR_9  EDMA Que Threshold 9
CSL_EDMA3_QUE_THR_10  EDMA Que Threshold 10
CSL_EDMA3_QUE_THR_11  EDMA Que Threshold 11
CSL_EDMA3_QUE_THR_12  EDMA Que Threshold 12
CSL_EDMA3_QUE_THR_13  EDMA Que Threshold 13
CSL_EDMA3_QUE_THR_14  EDMA Que Threshold 14
CSL_EDMA3_QUE_THR_15  EDMA Que Threshold 15
CSL_EDMA3_QUE_THR_16  EDMA Que Threshold 16

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