INTC
Detailed Description
The CPU has one exception input, one non-maskable interrupt, 12 maskable interrupts, and two dedicated emulation interrupts.The Interrupt Controller supports up to 128 system events. There are 128 system events that act as inputs to the Interrupt Controller. They consist of both internally-generated events (within the megamodule) and chip-level events. In addition to these 128 events, INTC also receives (and routes straight through to the CPU) the non-maskable and reset events.From these event inputs, the Interrupt Controller outputs signals to the CPU:
- One maskable, hardware exception (EXCEP)
- Twelve maskable hardware interrupts (INT4 ... INT15)
- One non-maskable signal which can be used as either an interrupt or exception (NMI)
- One reset signal (RESET)
NOTE: The CSL 3.0 INTC module is delivered as a separate library from the remaining CSL modules. When using an embedded operating system that contains interrupt controller/dispatcher support, do not link in the INTC library. For interrupt controller support, DSP/BIOS users should use the HWI (Hardware Interrupt) and ECM (Event Combiner Manager) modules supported under DSP/BIOS v5.21 or later.
- CSL 3.x Technical Requirements Specifications Version 0.5, dated May 14th, 2003
- TMS320C64x+ DSP Megamodule SPRU871I.pdf (May 2008)
The abbreviations INTC, Intc and intc have been used throughout this document to refer to Interrupt Controller
Copyright 2011, Texas Instruments Incorporated
