_CSL_RAC_BEII_interruptStatus Struct Reference
[RAC Back-End Data Structures]

CSL_RAC_BEII_interruptStatus This descriptor specifies the parameters obtained from the interrupt status register. More...

#include <csl_rac_regsBETypes.h>


Data Fields

Uint8 gccp1WdStat
Uint8 gccp0WdStat
Uint8 feWdStat
Uint8 odbtRdPtrStat
Uint8 obbtRdPtrStat
Uint8 eotStat
Uint8 gccp1SeqStat
Uint8 gccp1FifoOverStat
Uint8 gccp1CycOverStat
Uint8 gccp0SeqStat
Uint8 gccp0FifoOverStat
Uint8 gccp0CycOverStat

Detailed Description

CSL_RAC_BEII_interruptStatus This descriptor specifies the parameters obtained from the interrupt status register.

Field Documentation

Uint8 _CSL_RAC_BEII_interruptStatus::gccp1WdStat

Denotes the GCCP1 Watchdog status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp0WdStat

Denotes the GCCP0 Watchdog status.

Uint8 _CSL_RAC_BEII_interruptStatus::feWdStat

Denotes the Front-end Watchdog status.

Uint8 _CSL_RAC_BEII_interruptStatus::odbtRdPtrStat

Denotes the BETI ODBT read pointer crossing status.

Uint8 _CSL_RAC_BEII_interruptStatus::obbtRdPtrStat

Denotes the BETI OBBT read pointer crossing status.

Uint8 _CSL_RAC_BEII_interruptStatus::eotStat

Denotes the BETI 'end-of-transfer' status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp1SeqStat

Denotes the GCCP1 Sequencer Idle status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp1FifoOverStat

Denotes the GCCP1 FIFO Overflow status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp1CycOverStat

Denotes the GCCP#1 Cycle Overflow status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp0SeqStat

Denotes the GCCP0 Sequencer Idle status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp0FifoOverStat

Denotes the GCCP0 FIFO Overflow status.

Uint8 _CSL_RAC_BEII_interruptStatus::gccp0CycOverStat

Denotes the GCCP0 Cycle Overflow status.

The documentation for this struct was generated from the following file:
Copyright 2011, Texas Instruments Incorporated