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#include <csl_aif2.h>
Gives Phase alignement relative to Channel Radio Frame Boundary for scheduling DMA. OBSAI: only lsb is used CPRI: all three bits give 8th phase alignment. Phase can be used to adjust DMA according to DMA transfer budget.
bit order for Ethernet preamble and SOF
DirectIO buffer length, set same as value in DB
PE globla enable setup
PE frame and symbol terminal counting value to calculate sop and eop of packet
| Bool CSL_Aif2PeCommonSetup::bEnableCh[128] |
Enable PE channels one-by-one
PE channel configuration 0
PE input fifo control
| Uint32 CSL_Aif2PeCommonSetup::PeAxcOffset[128] |
Antanna carrier offset. Programmed in sys-clocks
| Uint16 CSL_Aif2PeCommonSetup::PeFrameMsgTc[128] |
PE Frame message terminal counter for OBSAI and CPRI
Modulo terminal count structure for Pe OBSAI WCDMA or LTE
| Uint8 CSL_Aif2PeCommonSetup::PeChObsaiTS[128] |
PE 128 DMA channel OBSAI time stamp value which is inserted into the frame
| Uint8 CSL_Aif2PeCommonSetup::PeChObsaiType[128] |
PE 128 DMA channel OBSAI type value which is inserted into the frame
| Uint16 CSL_Aif2PeCommonSetup::PeChObsaiAddr[128] |
PE 128 DMA channel OBSAI address value which is inserted into the frame
PE 128 DMA channel OBSAI time stamp mask value which is inserted into the frame
PE 128 DMA channel OBSAI time stamp generation algorithm
Dual bit map structure for Pe OBSAI dual bit map rule FSM
| Uint8 CSL_Aif2PeCommonSetup::ChIndex0[512] |
DMA channel rule LUT 0 for first 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex0[512] |
DMA channel rule LUT 0 enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex1[512] |
DMA channel rule LUT 1 for second 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex1[512] |
DMA channel rule LUT 1 enable for first 512 rules
| Bool CSL_Aif2PeCommonSetup::CpriPktEn1[512] |
DMA channel rule LUT 1 cpri packet enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex2[512] |
DMA channel rule LUT 2 for third 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex2[512] |
DMA channel rule LUT 2 enable for first 512 rules
| Bool CSL_Aif2PeCommonSetup::CpriPktEn2[512] |
DMA channel rule LUT 2 cpri packet enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex3[512] |
DMA channel rule LUT 3 for fourth 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex3[512] |
DMA channel rule LUT 3 enable for first 512 rules
| Bool CSL_Aif2PeCommonSetup::CpriPktEn3[512] |
DMA channel rule LUT 3 cpri packet enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex4[512] |
DMA channel rule LUT 4 for fifth 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex4[512] |
DMA channel rule LUT 4 enable for first 512 rules
| Bool CSL_Aif2PeCommonSetup::CpriPktEn4[512] |
DMA channel rule LUT 4 cpri packet enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex5[512] |
DMA channel rule LUT 5 for sixth 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex5[512] |
DMA channel rule LUT 5 enable for first 512 rules
| Bool CSL_Aif2PeCommonSetup::CpriPktEn5[512] |
DMA channel rule LUT 5 cpri packet enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex6[512] |
DMA channel rule LUT 6 for seventh 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex6[512] |
DMA channel rule LUT 6 enable for first 512 rules
| Uint8 CSL_Aif2PeCommonSetup::ChIndex7[512] |
DMA channel rule LUT 7 for eighth 512 rules
| Bool CSL_Aif2PeCommonSetup::bEnableChIndex7[512] |
DMA channel rule LUT 7 enable for first 512 rules