CSL_Aif2RmLinkSetup Struct Reference
[AIF2 Data Structures]

This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of RM link. More...

#include <csl_aif2.h>


Data Fields

Bool bEnableRmLink
CSL_Aif2RmFifoThold RmFifoThold
CSL_Aif2RmErrorSuppress RmErrorSuppress
Bool bEnableSdAutoAlign
Bool bEnableScrambler
Bool bEnableLcvUnsync
Bool bEnableLcvControl
Bool bEnableWatchDog
Uint8 WatchDogWrap
Bool bEnableClockQuality
Uint16 ClockMonitorWrap
Uint16 losDetThreshold
Uint16 SyncThreshold
Uint16 FrameSyncThreshold
Uint16 UnsyncThreshold
Uint16 FrameUnsyncThreshold

Detailed Description

This is a sub-structure in CSL_Aif2LinkSetup. This structure is used for configuring the parameters of RM link.

Field Documentation

Bool CSL_Aif2RmLinkSetup::bEnableRmLink

Boolean indicating if Rm link is to be enabled

CSL_Aif2RmFifoThold CSL_Aif2RmLinkSetup::RmFifoThold

setup Rm fifo threshold word size for reading received data

CSL_Aif2RmErrorSuppress CSL_Aif2RmLinkSetup::RmErrorSuppress

Suppress error reporting when the receiver state machine is not in state ST3

Bool CSL_Aif2RmLinkSetup::bEnableSdAutoAlign

Enables the RM to automatically disable Serdes symbol alignment when the receiver state machine reaches state ST3

Bool CSL_Aif2RmLinkSetup::bEnableScrambler

Boolean indicating if Rm Scrambler is to be enabled

Bool CSL_Aif2RmLinkSetup::bEnableLcvUnsync

Enables a state transition from teh ST3 to the ST0 state when lcv_det_thold is met

Bool CSL_Aif2RmLinkSetup::bEnableLcvControl

Writing a 1 to the bit will enable the Line Code Violation counter. THis 16 bit counter will saturate when it reaches a value of 0xffff. Writing a 0 to this bit will clear and disable the counter. The current counter value is available as status, lcv_cntr_value

Bool CSL_Aif2RmLinkSetup::bEnableWatchDog

Enables the clock detect watch dog timer.

Uint8 CSL_Aif2RmLinkSetup::WatchDogWrap

Defines the wrap value of the clock detection watchdog circuit. A value of zero disables the clock watchdog timer, Range 0 to 255

Bool CSL_Aif2RmLinkSetup::bEnableClockQuality

Enables the clock quality circuit.

Uint16 CSL_Aif2RmLinkSetup::ClockMonitorWrap

Defines the wrap value of the clock monitor used to define clock quality. A value of zero disables the clock monitor, Range 0 to 65,535

Uint16 CSL_Aif2RmLinkSetup::losDetThreshold

Sets 8b10b los detect threshold values in number of Line Code Violations received during a master frame, OBSAI, or during a Hyperframe, CPRI. Writing to this location will automatically clear the num_los counter and num_los_det status bit. Range 0 to 65,535

Uint16 CSL_Aif2RmLinkSetup::SyncThreshold

Threshold value for consecutive valid blocks of bytes which result in state ST1. Range 0 to 65,535

Uint16 CSL_Aif2RmLinkSetup::FrameSyncThreshold

Threshold value for consecutive valid message groups which result in state ST3. Range 0 to 65,535

Uint16 CSL_Aif2RmLinkSetup::UnsyncThreshold

Threshold value for consecutive invalid blocks of bytes which result in state ST0. Range 0 to 65,535

Uint16 CSL_Aif2RmLinkSetup::FrameUnsyncThreshold

Threshold value for consecutive invalid message groups which result in state ST1. Range 0 to 65,535

The documentation for this struct was generated from the following file:
Copyright 2011, Texas Instruments Incorporated