CSL_Aif2SdCommonSetup Struct Reference
[AIF2 Data Structures]

This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of a SD module, the link index specifies which SD module is used links 0-3 use SD module 0, links 4-5 use SD module 1. More...

#include <csl_aif2.h>


Data Fields

Bool bEnablePllB8
Bool bEnablePllB4
CSL_Aif2PllMpyFactor pllMpyFactorB8
CSL_Aif2PllMpyFactor pllMpyFactorB4
CSL_Aif2SdVoltRange VoltRangeB8
CSL_Aif2SdVoltRange VoltRangeB4
CSL_Aif2SdSleepPll SleepPllB8
CSL_Aif2SdSleepPll SleepPllB4
CSL_Aif2SdLoopBandwidth LB_B8
CSL_Aif2SdLoopBandwidth LB_B4
CSL_Aif2SdClockBypass CLKBYP_B8
CSL_Aif2SdClockBypass CLKBYP_B4
CSL_Aif2SdClockSelect SysClockSelect
Bool DisableLinkClock [6]

Detailed Description

This is a sub-structure in CSL_Aif2CommonSetup. This structure is used for configuring the parameters of a SD module, the link index specifies which SD module is used links 0-3 use SD module 0, links 4-5 use SD module 1.

Field Documentation

Bool CSL_Aif2SdCommonSetup::bEnablePllB8

Boolean indicating if B8 PLL is to be enabled

Bool CSL_Aif2SdCommonSetup::bEnablePllB4

Boolean indicating if B4 PLL is to be enabled

CSL_Aif2PllMpyFactor CSL_Aif2SdCommonSetup::pllMpyFactorB8

PLL mpy setting 4,5,..25

CSL_Aif2PllMpyFactor CSL_Aif2SdCommonSetup::pllMpyFactorB4

PLL mpy setting 4,5,..25

CSL_Aif2SdVoltRange CSL_Aif2SdCommonSetup::VoltRangeB8

PLL volt range setting between low and high

CSL_Aif2SdVoltRange CSL_Aif2SdCommonSetup::VoltRangeB4

PLL volt range setting between low and high

CSL_Aif2SdSleepPll CSL_Aif2SdCommonSetup::SleepPllB8

Puts the B8 PLL into sleep state when high

CSL_Aif2SdSleepPll CSL_Aif2SdCommonSetup::SleepPllB4

Puts the B4 PLL into sleep state when high

CSL_Aif2SdLoopBandwidth CSL_Aif2SdCommonSetup::LB_B8

PLL Loop bandwidth setting

CSL_Aif2SdLoopBandwidth CSL_Aif2SdCommonSetup::LB_B4

PLL Loop bandwidth setting

CSL_Aif2SdClockBypass CSL_Aif2SdCommonSetup::CLKBYP_B8

PLL clock bypass setting

CSL_Aif2SdClockBypass CSL_Aif2SdCommonSetup::CLKBYP_B4

PLL clock bypass setting

CSL_Aif2SdClockSelect CSL_Aif2SdCommonSetup::SysClockSelect

Tx byte clock from either B8 or B4 SEDES link will be selected as sys_clk once the PLL has acquired lock

Bool CSL_Aif2SdCommonSetup::DisableLinkClock[6]

Select if link clock is gated off or on each bool array is matched with each link

The documentation for this struct was generated from the following file:
Copyright 2011, Texas Instruments Incorporated