CSL_Aif2SdRxStatus Struct Reference
[AIF2 Data Structures]

This object contains the aif2 SERDES Rx link status information. More...

#include <csl_aif2.h>


Data Fields

Bool sdRxSync
Bool sdRxLosDetect
Bool sdRxOCIP
Bool sdRxEqUnder
Bool sdRxEqOver
Uint8 sdRxBusWidth
Bool sdRxTestFail

Detailed Description

This object contains the aif2 SERDES Rx link status information.

Field Documentation

Bool CSL_Aif2SdRxStatus::sdRxSync

If the alignment feature of the Ser-des is used by hardware, the receiver frame synchronizer must have knowledge that each Ser-des port had completed a requested byte alignment so that the byte alignment control logic can operate.

Bool CSL_Aif2SdRxStatus::sdRxLosDetect

The receiver frame synchronizer must have knowledge that each Ser-des port had detected a loss of signal condition so that the receiver can suppress events due to a loss of frame synchronization

Bool CSL_Aif2SdRxStatus::sdRxOCIP

Offset compensation in progress. Driven high asynchronously during offset compensation

Bool CSL_Aif2SdRxStatus::sdRxEqUnder

Driven high during equalizer analysis if under equalized

Bool CSL_Aif2SdRxStatus::sdRxEqOver

Driven high during equalizer analysis if over equalized

Uint8 CSL_Aif2SdRxStatus::sdRxBusWidth

The receiver bus bandwidth is fixed in hardware to 20 bits and is not configurable through an MMR. However the value that reflects a 20 bit bus width will be read of the configuration register is read.

Bool CSL_Aif2SdRxStatus::sdRxTestFail

Test Failure. Driven high when an error is encountered during a test sequence executed on an individual channel. Synchronous to RXBCLK

The documentation for this struct was generated from the following file:
Copyright 2011, Texas Instruments Incorporated