CSL_TAC_BEII_interruptStatus Struct Reference
[TAC Back-End Data Structures]

This descriptor specifies the parameters obtained from the interrupt status register. More...

#include <csl_tac_regsBEAux.h>


Data Fields

Uint8 sgcp0CycOverStat
Uint8 sgcp0FifoOverStat
Uint8 sgcp0SeqStat
Uint8 sgcp0BuffMissStat
Uint8 sgcp1CycOverStat
Uint8 sgcp1FifoOverStat
Uint8 sgcp1SeqStat
Uint8 sgcp1BuffMissStat
Uint8 betiWdStat
Uint8 feTransErrStat

Detailed Description

This descriptor specifies the parameters obtained from the interrupt status register.

Field Documentation

Uint8 CSL_TAC_BEII_interruptStatus::sgcp0CycOverStat

Denotes the SGCP0 Cycle Overflow status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp0FifoOverStat

Denotes the SGCP0 FIFO Overflow status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp0SeqStat

Denotes the SGCP0 Sequencer Idle status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp0BuffMissStat

Denotes the SGCP0 Input Buffer Miss status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp1CycOverStat

Denotes the SGCP1 Cycle Overflow status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp1FifoOverStat

Denotes the SGCP1 FIFO Overflow status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp1SeqStat

Denotes the SGCP1 Sequencer Idle status.

Uint8 CSL_TAC_BEII_interruptStatus::sgcp1BuffMissStat

Denotes the SGCP1 Input Buffer Miss status.

Uint8 CSL_TAC_BEII_interruptStatus::betiWdStat

Denotes the BETI Watchdog status.

Uint8 CSL_TAC_BEII_interruptStatus::feTransErrStat

FE transaction error status

The documentation for this struct was generated from the following file:
Copyright 2011, Texas Instruments Incorporated