/* * ======== all.cfg ======== * * For details about the packages and configuration parameters used throughout * this config script, see the Codec Engine Configuration Guide (link * provided in the release notes). */ /* temporary workaround for SDSCM00016135 - this has to be first in this file */ xdc.loadPackage('ti.bios'); xdc.loadCapsule('./heaps.cfg'); xdc.useModule('ti.sysbios.BIOS'); /* Setup xdcruntime proxys */ xdc.useModule('ti.sysbios.xdcruntime.Settings'); var platformName = Program.platformName; /* * Configure CE's OSAL. This codec server only builds for the BIOS-side of * a heterogeneous system, so use the "DSPLINK_BIOS" configuration. */ var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global'); /* SysLink-based slave server */ osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS; /* configure default memory seg id to BIOS-defined "DDR2" */ //osalGlobal.defaultMemSegId = "`defaultMemSegIdStr`"; /* activate BIOS logging module */ /* TODO:L need to add UIA Log collection support */ //var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer'); /* IPC-related config */ var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); var myName; // put into platform capsule if (platformName.match(/DM8168/) || platformName.match(/DM8148/) || platformName.match(/TI816X/) || platformName.match(/TI814X/)) { if (platformName.match(/:VIDEO-M3/)) { var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 0; myName = "VIDEO-M3"; } else if (platformName.match(/:VPSS-M3/)) { var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 1; myName = "VPSS-M3"; } else { myName = "DSP"; } } else { myName = "DSP"; } var settings = xdc.useModule('ti.sdo.ipc.family.Settings'); var procNames = settings.getDeviceProcNames(); MultiProc.setConfig(myName, procNames); var platformBaseName = platformName.replace(/(\w+)\:.*$/, "$1").replace(/\./g, "_"); try { xdc.loadCapsule(platformBaseName + ".cfg"); } catch(e) { throw "Error: cannot load example's platform capsule '" + platformBaseName + ".cfg' (either it doesn't exist or there's an error inside it)"; } if (false) { var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU'); /* L2RAM: 64K mapped using 4 smallPages(16K); cacheable; translated */ /* config small page[2] to map 16K VA 0x20000000 to PA 0x55020000 */ AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES; AMMU.smallPages[2].logicalAddress = 0x20000000; AMMU.smallPages[2].translatedAddress = 0x55020000; AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES; AMMU.smallPages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.smallPages[2].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.smallPages[2].size = AMMU.Small_16K; /* config small page[3] to map 16K VA 0x20004000 to PA 0x55024000 */ AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES; AMMU.smallPages[3].logicalAddress = 0x20004000; AMMU.smallPages[3].translatedAddress = 0x55024000; AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES; AMMU.smallPages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.smallPages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.smallPages[3].size = AMMU.Small_16K; /* config small page[4] to map 16K VA 0x20008000 to PA 0x55028000 */ AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES; AMMU.smallPages[4].logicalAddress = 0x20008000; AMMU.smallPages[4].translatedAddress = 0x55028000; AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES; AMMU.smallPages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.smallPages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.smallPages[4].size = AMMU.Small_16K; /* config small page[5] to map 16K VA 0x2000C000 to PA 0x5502C000 */ AMMU.smallPages[5].pageEnabled = AMMU.Enable_YES; AMMU.smallPages[5].logicalAddress = 0x2000C000; AMMU.smallPages[5].translatedAddress = 0x5502C000; AMMU.smallPages[5].translationEnabled = AMMU.Enable_YES; AMMU.smallPages[5].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.smallPages[5].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.smallPages[5].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.smallPages[5].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.smallPages[5].size = AMMU.Small_16K; }; /* TODO:L need to add UIA Log collection support */ //xdc.useModule('ti.sdo.ce.bioslog.LogServer'); /* to link in release libs, remove the following lines */ xdc.useModule('ti.sdo.ce.global.Settings').profile = "debug"; xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug"; /* * "Use" the various codec modules; i.e., implementation of codecs. * All these "xdc.useModule" commands provide a handle to the codecs, * which we'll use below to add them to the Server.algs array. */ var SOME_CODEC = xdc.useModule('root_example.spec.codec.SOME_CODEC'); //var ittiam_g729_decoder = xdc.useModule('codecs.g729_decoder.ittiam_g729_decoder'); var ONE_DSP_LIBRARY = xdc.loadPackage('library_place.one_dsp_library'); var ANOTHER_DSP_LIBRARY = xdc.loadPackage('library_place.another_dsp_library'); /* * ======== Server Configuration ======== */ var Server = xdc.useModule('ti.sdo.ce.Server'); /* The server's stackSize */ Server.threadAttrs.stackSize = 16*1024; /* The servers execution priority */ Server.threadAttrs.priority = Server.MINPRI; /* * The optional stack pad to add to non-configured stacks. This is well * beyond most codec needs, but follows the approach of "start big and * safe, then optimize when things are working." */ Server.stackSizePad = 9000; /* * The array of algorithms this server can serve up. This array also * configures details about the threads which will be created to run the * algorithms (e.g. stack sizes, priorities, etc.). * * Note that we don't set any per-codec instance stack sizes below, as * we leverage the Server.stackSizePad config param to pad all stacks in * this simple example. * * However, in a 'real' server, stack sizes should be measured and * tested - there are some techniques for doing so here: * http://wiki.davincidsp.com/index.php?title=Stack_issues */ Server.algs = [ {name: "some_codec", mod: SOME_CODEC, threadAttrs: { stackSize: 48*1024, stackMemId: 0, priority: Server.MINPRI + 1} }, ]; /* we can use DMA in the VIDENC_COPY codecs */ //VIDENC_COPY.useDMA = true; //VIDENC1_COPY.alg.useDMA = false; /* * Note that we presume this server runs on a system with DSKT2 and DMAN3, * so we configure those modules here. */ /* * ======== DSKT2 (XDAIS Alg. memory allocation) configuration ======== * * DSKT2 is the memory manager for all algorithms running in the system, * granting them persistent and temporary ("scratch") internal and external * memory. We configure it here to define its memory allocation policy. * * DSKT2 settings are critical for algorithm performance. * * First we assign various types of algorithm internal memory (DARAM0..2, * SARAM0..2,IPROG, which are all the same on a C64+ DSP) to "L1DHEAP" * defined in the BIOS cfg as an internal memory heap. (For instance, if * an algorithm asks for 5K of DARAM1 memory, DSKT2 will allocate 5K from * L1DHEAP, if available, and give it to the algorithm; if the 5K is not * available in the L1DHEAP, that algorithm's creation will fail.) * * The remaining segments we point to the "DDRALGHEAP" external memory segment * (also defined in BIOS cfg) except for DSKT2_HEAP which stores DSKT2's * internal dynamically allocated objects, which must be preserved even if * no codec instances are running, so we place them in "DDR2" memory segment * with the rest of system code and static data. */ var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2'); /* CE 3.21.02.25 configuration * //DSKT2.DARAM0 = "INT_HEAP"; //DSKT2.DARAM1 = "INT_HEAP"; //DSKT2.DARAM2 = "INT_HEAP"; //DSKT2.SARAM0 = "INT_HEAP"; //DSKT2.SARAM1 = "INT_HEAP"; //DSKT2.SARAM2 = "INT_HEAP"; //DSKT2.ESDATA = "EXTALG_HEAP"; //DSKT2.EPROG = "EXTALG_HEAP"; //DSKT2.IPROG = "INT_HEAP"; //DSKT2.DSKT2_HEAP = "EXT_HEAP"; */ /* Custom CE 3.21.02.25 configuration */ DSKT2.DARAM0 = "DDRALGHEAP"; DSKT2.DARAM1 = "DDRALGHEAP"; DSKT2.DARAM2 = "DDRALGHEAP"; DSKT2.SARAM0 = "DDRALGHEAP"; DSKT2.SARAM1 = "DDRALGHEAP"; DSKT2.SARAM2 = "DDRALGHEAP"; DSKT2.ESDATA = "DDRALGHEAP"; DSKT2.EPROG = "DDRALGHEAP"; DSKT2.IPROG = "DDRALGHEAP"; DSKT2.DSKT2_HEAP = "DDRALGHEAP"; /* * Next we define how to fulfill algorithms' requests for fast ("scratch") * internal memory allocation; "scratch" is an area an algorithm writes to * while it processes a frame of data and * * First we turn off the switch that allows the DSKT2 algorithm memory manager * to give to an algorithm external memory for scratch if the system has run * out of internal memory. In that case, if an algorithm fails to get its * requested scratch memory, it will fail at creation rather than proceed to * run at poor performance. (If your algorithms fail to create, you may try * changing this value to "true" just to get it running and optimize other * scratch settings later.) * * Next we set "algorithm scratch sizes", a scheme we use to minimize internal * memory resources for algorithms' scratch memory allocation. Algorithms that * belong to the same "scratch group ID" -- field "groupId" in the algorithm's * Server.algs entry above, reflecting the priority of the task running the * algorithm -- don't run at the same time and thus can share the same * scratch area. When creating the first algorithm in a given "scratch group" * (between 0 and 19), a shared scratch area for that groupId is created with * a size equal to SARAM_SCRATCH_SIZES[] below -- unless the * algorithm requests more than that number, in which case the size will be * what the algorithm asks for. So SARAM_SCRATCH_SIZES[] size is * more of a groupId size guideline -- if the algorithm needs more it will get * it, but getting these size guidelines right is important for optimal use of * internal memory. The reason for this is that if an algorithm comes along * that needs more scratch memory than its groupId scratch area's size, it * will get that memory allocated separately, without sharing. * * This DSKT2.SARAM_SCRATCH_SIZES[] does not mean it is a scratch size * that will be automatically allocated for the group at system * startup, but only that is a preferred minimum scratch size to use for the * first algorithm that gets created in the group, if any. * * (An example: if algorithms A and B with the same groupId = 0 require 10K and * 20K of scratch, and if SARAM_SCRATCH_SIZES[0] is 0, if A gets created first * DSKT2 allocates a shared scratch area for group 0 of size 10K, as A needs. * If then B gets to be created, the 20K scratch area it gets will not be * shared with A's -- or anyone else's; the total internal memory use will be * 30K. By contrast, if B gets created first, a 20K shared scratch will be * allocated, and when A comes along, it will get its 10K from the existing * group 0's 20K area. To eliminate such surprises, we set * SARAM_SCRATCH_SIZES[0] to 20K and always spend exactly 20K on A and B's * shared needs -- independent of their creation order. Not only do we save 10K * of precious internal memory, but we avoid the possibility that B can't be * created because less than 20K was available in the DSKT2 internal heaps.) * * In our example below, we set the size of groupId 0 to 32K -- as an example, * even though our codecs don't use it. * * Finally, note that if the codecs correctly implement the * ti.sdo.ce.ICodec.getDaramScratchSize() and .getSaramScratchSize() methods, * this scratch size configuration can be autogenerated by * configuring Server.autoGenScratchSizeArrays = true. */ DSKT2.ALLOW_EXTERNAL_SCRATCH = false; DSKT2.SARAM_SCRATCH_SIZES[0] = 32 * 1024; /* * ======== DMAN3 (DMA manager) configuration ======== */ //var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3'); /* First we configure how DMAN3 handles memory allocations: * * Essentially the configuration below should work for most codec combinations. * If it doesn't work for yours -- meaning an algorithm fails to create due * to insufficient internal memory -- try the alternative (commented out * line that assigns "DDRALGHEAP" to DMAN3.heapInternal). * * What follows is an FYI -- an explanation for what the alternative would do: * * When we use an external memory segment (DDRALGHEAP) for DMAN3 internal * segment, we force algorithms to use external memory for what they think is * internal memory -- we do this in a memory-constrained environment * where all internal memory is used by cache and/or algorithm scratch * memory, pessimistically assuming that if DMAN3 uses any internal memory, * other components (algorithms) will not get the internal memory they need. * * This setting would affect performance very lightly. * * By setting DMAN3.heapInternal = DMAN3 *may not* supply * ACPY3_PROTOCOL IDMA3 channels the protocol required internal memory for * IDMA3 channel 'env' memory. To deal with this catch-22 situation we * configure DMAN3 with hook-functions to obtain internal-scratch memory * from the shared scratch pool for the associated algorithm's * scratch-group (i.e. it first tries to get the internal scratch memory * from DSKT2 shared allocation pool, hoping there is enough extra memory * in the shared pool, if that doesn't work it will try persistent * allocation from DMAN3.internalHeap). */ //DMAN3.heapInternal = "L1DHEAP"; /* L1DHEAP is an internal segment */ // DMAN3.heapInternal = "DDRALGHEAP"; /* DDRALGHEAP is an external segment */ //DMAN3.heapExternal = "DDRALGHEAP"; //DMAN3.idma3Internal = false; //DMAN3.scratchAllocFxn = "DSKT2_allocScratch"; //DMAN3.scratchFreeFxn = "DSKT2_freeScratch"; // // CE 3.21.02.25 config //DMAN3.heapInternal = "INT_HEAP"; //DMAN3.heapExternal = "EXTALG_HEAP"; //DMAN3.idma3Internal = false; //DMAN3.scratchAllocFxn = "DSKT2_allocScratch"; //DMAN3.scratchFreeFxn = "DSKT2_freeScratch"; /* Next, we configure all the physical resources that DMAN3 is granted * exclusively. These settings are optimized for the DSP on DM6446 (DaVinci). * * We assume PaRams 0..79 are taken by the Arm drivers, so we reserve * all the rest, up to 127 (there are 128 PaRam sets on DM6446). * DMAN3 takes TCC's 32 through 63 (hence the High TCC mask is 0xFFFFFFFF * and the Low TCC mask is 0). Of the 48 PaRams we reserved, we assign * all of them to scratch group 0; similarly, of the 32 TCCs we reserved, * we assign all of them to scratch group 0. * * If we had more scratch groups with algorithms that require EDMA, we would * split those 48 PaRams and 32 TCCs appropriately. For example, if we had * a video encoder alg. in group 0 and video decoder alg. in group 1, and they * both needed a number of EDMA channels, we could assing 24 PaRams and 16 * TCCs to Groups [0] and [1] each. (Assuming both algorithms needed no more * than 24 channels to run properly.) */ //DMAN3.paRamBaseIndex = 80; // 1st EDMA3 PaRAM set available for DMAN3 //DMAN3.numQdmaChannels = 8; // number of device's QDMA channels to use //DMAN3.qdmaChannels = [0,1,2,3,4,5,6,7]; // choice of QDMA channels to use //DMAN3.numPaRamEntries = 48; // number of PaRAM sets exclusively used by DMAN //DMAN3.numPaRamGroup[0] = 48; // number of PaRAM sets for scratch group 0 //DMAN3.numTccGroup[0] = 32; // number of TCCs assigned to scratch group 0 //DMAN3.tccAllocationMaskL = 0; // bit mask indicating which TCCs 0..31 to use //DMAN3.tccAllocationMaskH = 0xffffffff; // assign all TCCs 32..63 for DMAN // // CE 3.21.02.25 config below //var lld = Program.build.cfgArgs.lld; // //if (lld == true) { // // print("Setting DMAN3's useExternalRM mode to TRUE"); // DMAN3.useExternalRM = true; // DMAN3.numQdmaChannels = 1; // // var EDMA3 = xdc.useModule("ti.sdo.fc.edma3.Settings"); // // EDMA3.persistentAllocFxn = "DSKT2_allocPersistent"; // EDMA3.persistentFreeFxn = "DSKT2_freePersistent"; // // // EDMA3.maxTccs[0] = 32; // EDMA3.maxPaRams[0] = 48; //} //else { // if (platformName.match(/DM8168/) || platformName.match(/DM8148/) || // platformName.match(/TI816X/) || platformName.match(/TI814X/)) { // DMAN3.qdmaPaRamBase = 0x09004000; // } // // DMAN3.paRamBaseIndex = 80; // 1st EDMA3 PaRAM set available for DMAN3 // DMAN3.numQdmaChannels = 8; // number of device's QDMA channels to use // DMAN3.qdmaChannels = [0,1,2,3,4,5,6,7]; // choice of QDMA channels // //to use // DMAN3.numPaRamEntries = 48; // number of PaRAM sets exclusively used // //by DMAN // DMAN3.numPaRamGroup[0] = 48; //number of PaRAM sets for scratch group 0 // DMAN3.numTccGroup[0] = 32; //number of TCCs assigned to scratch group 0 // DMAN3.tccAllocationMaskL = 0; // bit mask indicating which TCCs 0..31 // //to use // DMAN3.tccAllocationMaskH = 0xffffffff; // assign all TCCs 32..63 for DMAN //} /* The remaining DMAN3 configuration settings are as defined in ti.sdo.fc.DMAN3 * defaults. You may need to override them to add more QDMA channels and * configure per-scratch-group resource sub-allocations. */ /* * ======== RMAN (IRES Resource manager) configuration ======== */ /* TODO: What all do I set up here from RMANs perspective ? Should this be here or in OSAL? */ var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN'); RMAN.useDSKT2 = true; RMAN.tableSize = 10; var GT = xdc.useModule('ti.sdo.utils.trace.GT'); var GTINFRA = xdc.useModule('ti.sdo.fc.utils.gtinfra.GTINFRA'); GTINFRA.runtimeEnv = GTINFRA.NONE; GT.MALLOCFXN = "myMalloc"; GT.PRINTFXN = "printfCaller"; // Set up logging xdc.loadCapsule('example_root/buildutils/server_log.cfg'); /* * @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,261; 12-2-2011 14:52:49; /db/atree/library/trees/ce/ce-s25x/src/ xlibrary */