| 1 | ////////////////////////////////////////////////////////////////////////////// | = | 1 | ////////////////////////////////////////////////////////////////////////////// |
| 2 | // * File name: aic3204_loop_stereo_in1.c | <> | 2 | // * File name: aic3204_tone_stereo_out.c |
| 3 | // * | = | 3 | // * |
| 4 | // * Description: AIC3204 Loop IN1. | <> | 4 | // * Description: AIC3204 Tone. |
| 5 | // * | = | 5 | // * |
| 6 | // * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | 6 | // * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
| 7 | // * Copyright (C) 2012 Spectrum Digital, Incorporated | 7 | // * Copyright (C) 2012 Spectrum Digital, Incorporated | |
| 8 | // * | 8 | // * | |
| 9 | // * | 9 | // * | |
| 10 | // * Redistribution and use in source and binary forms, with or without | 10 | // * Redistribution and use in source and binary forms, with or without | |
| 11 | // * modification, are permitted provided that the following conditions | 11 | // * modification, are permitted provided that the following conditions | |
| 12 | // * are met: | 12 | // * are met: | |
| 13 | // * | 13 | // * | |
| 14 | // * Redistributions of source code must retain the above copyright | 14 | // * Redistributions of source code must retain the above copyright | |
| 15 | // * notice, this list of conditions and the following disclaimer. | 15 | // * notice, this list of conditions and the following disclaimer. | |
| 16 | // * | 16 | // * | |
| 17 | // * Redistributions in binary form must reproduce the above copyright | 17 | // * Redistributions in binary form must reproduce the above copyright | |
| 18 | // * notice, this list of conditions and the following disclaimer in the | 18 | // * notice, this list of conditions and the following disclaimer in the | |
| 19 | // * documentation and/or other materials provided with the | 19 | // * documentation and/or other materials provided with the | |
| 20 | // * distribution. | 20 | // * distribution. | |
| 21 | // * | 21 | // * | |
| 22 | // * Neither the name of Texas Instruments Incorporated nor the names of | 22 | // * Neither the name of Texas Instruments Incorporated nor the names of | |
| 23 | // * its contributors may be used to endorse or promote products derived | 23 | // * its contributors may be used to endorse or promote products derived | |
| 24 | // * from this software without specific prior written permission. | 24 | // * from this software without specific prior written permission. | |
| 25 | // * | 25 | // * | |
| 26 | // * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | 26 | // * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 27 | // * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | 27 | // * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 28 | // * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | 28 | // * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 29 | // * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | 29 | // * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 30 | // * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | 30 | // * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 31 | // * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | 31 | // * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 32 | // * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | 32 | // * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 33 | // * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | 33 | // * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 34 | // * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | 34 | // * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 35 | // * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | 35 | // * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 36 | // * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 36 | // * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 37 | // * | 37 | // * | |
| 38 | ////////////////////////////////////////////////////////////////////////////// | 38 | ////////////////////////////////////////////////////////////////////////////// | |
| 39 | 39 | |||
| 40 | #include "stdio.h" | 40 | #include "stdio.h" | |
| 41 | #include "evm5517.h" | 41 | #include "evm5517.h" | |
| 42 | 42 | |||
| 43 | extern Int16 AIC3204_rset( Uint16 regnum, Uint16 regval); | 43 | extern Int16 AIC3204_rset( Uint16 regnum, Uint16 regval); | |
| 44 | 44 | |||
| 45 | #define Rcv 0x08 | +- | ||
| 46 | #define Xmit 0x20 | = | 45 | #define Xmit 0x20 |
| 47 | <> | |||
| 48 | /* | = | 46 | /* |
| 49 | * | 47 | * | |
| 50 | * aic3204_loop_stereo_in1( ) | <> | 48 | * AIC3204 Tone |
| 51 | * Input from STEREO IN 1 is looped out through HEADPHONE jack | 49 | * Output a 1 kHz tone through the STEREO OUT jack | |
| 52 | * | = | 50 | * |
| 53 | */ | 51 | */ | |
| 54 | Int16 aic3204_loop_stereo_in1( ) | <> | 52 | Int16 aic3204_tone_stereo_out( ) |
| 55 | { | = | 53 | { |
| 56 | /* Pre-generated sine wave data, 16-bit signed samples */ | 54 | /* Pre-generated sine wave data, 16-bit signed samples */ | |
| -+ | 55 | Int16 sinetable[48] = { | ||
| 56 | 0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b, | |||
| 57 | 0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef, | |||
| 58 | 0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4, | |||
| 59 | 0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75, | |||
| 60 | 0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1, | |||
| 61 | 0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c | |||
| 62 | }; | |||
| 57 | Int16 j, i = 0; | = | 63 | Int16 j, i = 0; |
| 58 | Int16 sample, data1, data2; | <> | 64 | Int16 sample; |
| 59 | = | 65 | ||
| 60 | /* Configure AIC3204 */ | 66 | /* Configure AIC3204 */ | |
| 61 | AIC3204_rset( 0, 0x00 ); // Select page 0 | 67 | AIC3204_rset( 0, 0x00 ); // Select page 0 | |
| 62 | AIC3204_rset( 1, 0x01 ); // Reset codec | 68 | AIC3204_rset( 1, 0x01 ); // Reset codec | |
| 63 | AIC3204_rset( 0, 0x01 ); // Point to page 1 | 69 | AIC3204_rset( 0, 0x01 ); // Point to page 1 | |
| 64 | AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD | 70 | AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD | |
| 65 | AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks | 71 | AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks | |
| 66 | /* PLL and Clocks config and Power Up */ | 72 | /* PLL and Clocks config and Power Up */ | |
| 67 | AIC3204_rset( 0, 0x00 ); // Select page 0 | 73 | AIC3204_rset( 0, 0x00 ); // Select page 0 | |
| 68 | // AIC3204_rset( 27, 0x00 ); // BCLK and WCLK is set as i/p to AIC3204(Slave) | <> | ||
| 69 | AIC3204_rset( 27, 0x0d ); // BCLK and WCLK is set as o/p from AIC3204(Master) //MM | 74 | AIC3204_rset( 27, 0x00 ); // BCLK and WCLK is set as i/p to AIC3204(Slave) | |
| 70 | ||||
| 71 | // // AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK | |||
| 72 | // AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK //MM | |||
| 73 | // AIC3204_rset( 6, 0x08 ); // PLL setting: J | |||
| 74 | // AIC3204_rset( 7, 0 ); // PLL setting: HI_BYTE(D) | |||
| 75 | // AIC3204_rset( 8, 0 ); // PLL setting: LO_BYTE(D) | |||
| 76 | // /* For 48 KHz sampling */ | |||
| 77 | // AIC3204_rset( 5, 0x92 ); // PLL setting: Power up PLL, P=1 and R=2 | |||
| 78 | // AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling | |||
| 79 | // AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080 | |||
| 80 | // AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 | |||
| 81 | // AIC3204_rset( 11, 0x88 ); // Power up NDAC and set NDAC value to 8 | |||
| 82 | // AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2 | |||
| 83 | // AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8 | |||
| 84 | // AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2 | |||
| 85 | ||||
| 86 | // MM - Added below | |||
| 87 | AIC3204_rset( 28, 0x00 ); // Data ofset = 0 | |||
| 88 | AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK | 75 | AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK | |
| 89 | AIC3204_rset( 6, 0x07 ); // PLL setting: J=7 | 76 | AIC3204_rset( 6, 0x08 ); // PLL setting: J | |
| 90 | AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680) | 77 | AIC3204_rset( 7, 0 ); // PLL setting: HI_BYTE(D = 0) | |
| 91 | AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680) | 78 | AIC3204_rset( 8, 0 ); // PLL setting: LO_BYTE(D) = 0 | |
| 92 | AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY | 79 | AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK | |
| 93 | // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs | 80 | /* For 48 KHz sampling */ | |
| 94 | AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1 | 81 | AIC3204_rset( 5, 0x92 ); // PLL setting: Power up PLL, P=1 and R=2 | |
| 95 | //EZDSP5535_waitusec(10000); // Wait for PLL to come up | |||
| 96 | EVM5517_waitusec( 10000 ); // Wait for PLL to come up | |||
| 97 | AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling | 82 | AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling | |
| 98 | AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080 | 83 | AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080 | |
| 99 | AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 | 84 | AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6 | |
| 100 | AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2 | 85 | AIC3204_rset( 11, 0x88 ); // Power up NDAC and set NDAC value to 8 | |
| 101 | AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7 | 86 | AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2 | |
| 102 | AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7 | 87 | AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8 | |
| 103 | AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2 | 88 | AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2 | |
| 104 | // MM - Added above | |||
| 105 | ||||
| 106 | /* DAC ROUTING and Power Up */ | 89 | /* DAC ROUTING and Power Up */ | |
| 107 | AIC3204_rset( 0, 0x01 ); // Select page 1 | = | 90 | AIC3204_rset( 0, 0x01 ); // Select page 1 |
| 108 | AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL | <> | 91 | AIC3204_rset( 14, 0x08 ); // LDAC AFIR routed to LOL |
| 109 | AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR | 92 | AIC3204_rset( 15, 0x08 ); // RDAC AFIR routed to LOR | |
| 110 | AIC3204_rset( 0, 0x00 ); // Select page 0 | = | 93 | AIC3204_rset( 0, 0x00 ); // Select page 0 |
| 111 | AIC3204_rset( 64, 0x02 ); // Left vol=right vol | 94 | AIC3204_rset( 64, 0x02 ); // Left vol=right vol | |
| 112 | AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left | 95 | AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left | |
| 113 | AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel | 96 | AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel | |
| 114 | AIC3204_rset( 0, 0x01 ); // Select page 1 | 97 | AIC3204_rset( 0, 0x01 ); // Select page 1 | |
| 115 | AIC3204_rset( 16, 0x06 ); // Unmute HPL , 6dB gain | <> | 98 | AIC3204_rset( 18, 0x3a ); // Unmute LOL , -6dB gain |
| 116 | AIC3204_rset( 17, 0x06 ); // Unmute HPR , 6dB gain | 99 | AIC3204_rset( 19, 0x3a ); // Unmute LOR , -6dB gain | |
| 117 | AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR | 100 | AIC3204_rset( 9, 0x0C ); // Power up LOL,LOR | |
| 118 | AIC3204_rset( 0, 0x00 ); // Select page 0 | = | 101 | AIC3204_rset( 0, 0x00 ); // Select page 0 |
| 119 | EVM5517_wait( 500 ); // Wait | 102 | EVM5517_wait( 500 ); // Wait | |
| 120 | /* ADC ROUTING and Power Up */ | 103 | /* ADC ROUTING and Power Up */ | |
| 121 | AIC3204_rset( 0, 0x01 ); // Select page 1 | 104 | AIC3204_rset( 0, 0x01 ); // Select page 1 | |
| 122 | AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack | <> | 105 | AIC3204_rset( 52, 0x0C ); // STEREO 1 Jack |
| 123 | // IN2_L to LADC_P through 40 kohm | = | 106 | // IN2_L to LADC_P through 40 kohm |
| 124 | AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm | <> | 107 | AIC3204_rset( 55, 0x0C ); // IN2_R to RADC_P through 40 kohmm |
| 125 | AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm | = | 108 | AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm |
| 126 | AIC3204_rset( 57, 0xC0 ); // CM_1 (common mode) to RADC_M through 40 kohm | 109 | AIC3204_rset( 57, 0xC0 ); // CM_1 (common mode) to RADC_M through 40 kohm | |
| 127 | AIC3204_rset( 59, 0x0f ); // MIC_PGA_L unmute | <> | 110 | AIC3204_rset( 59, 0x00 ); // MIC_PGA_L unmute |
| 128 | AIC3204_rset( 60, 0x0f ); // MIC_PGA_R unmute | 111 | AIC3204_rset( 60, 0x00 ); // MIC_PGA_R unmute | |
| 129 | AIC3204_rset( 0, 0x00 ); // Select page 0 | = | 112 | AIC3204_rset( 0, 0x00 ); // Select page 0 |
| 130 | AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC | 113 | AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC | |
| 131 | AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC | 114 | AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC | |
| 132 | 115 | |||
| 133 | AIC3204_rset( 0, 0x00 ); | 116 | AIC3204_rset( 0, 0x00 ); | |
| 134 | EVM5517_wait( 200 ); // Wait | 117 | EVM5517_wait( 200 ); // Wait | |
| 135 | 118 | |||
| 136 | /* I2S settings */ | 119 | /* I2S settings */ | |
| 137 | // I2S0_SRGR = 0x0015; // FSDIV = 2 (/32), CLKDIV = 5 (/64), Fs = 48.8k (SYSCLK = 100MHz) / Fs = 48k (SYSCLK = 98.304MHz) | <> | 120 | I2S0_SRGR = 0x0015; // FSDIV = 2 (/32), CLKDIV = 5 (/64), Fs = 48.8k (SYSCLK = 100MHz) / Fs = 48k (SYSCLK = 98.304MHz) |
| 138 | I2S0_ICMR = 0x0028; // Enable interrupts | = | 121 | I2S0_ICMR = 0x0028; // Enable interrupts |
| 139 | // I2S0_CR = 0x8012; // 16-bit word, Master, enable I2S | <> | ||
| 140 | I2S0_CR = 0x8010; // 16-bit word, Slave, enable I2S | 122 | I2S0_CR = 0x8012; // 16-bit word, Master, enable I2S | |
| 141 | 123 | |||
| 142 | /* Play Tone */ | = | 124 | /* Play Tone */ |
| 143 | for ( i = 0 ; i < 5 ; i++ ) | 125 | for ( i = 0 ; i < 5 ; i++ ) | |
| 144 | { | 126 | { | |
| 145 | for ( j = 0 ; j < 1000 ; j++ ) | 127 | for ( j = 0 ; j < 1000 ; j++ ) | |
| 146 | { | 128 | { | |
| 147 | for ( sample = 0 ; sample < 48 ; sample++ ) | 129 | for ( sample = 0 ; sample < 48 ; sample++ ) | |
| 148 | { | 130 | { | |
| 149 | /* Read Digital audio input */ | <> | 131 | I2S0_W0_MSW_W = (sinetable[sample]) ; // Send left sample |
| 150 | while((Rcv & I2S0_IR) == 0); // Wait for receive interrupt to be pending | |||
| 151 | data1 = I2S0_W0_MSW_R; // 16 bit left channel received audio data | 132 | I2S0_W0_LSW_W = 0; | |
| 152 | data2 = I2S0_W1_MSW_R; // 16 bit right channel received audio data | 133 | I2S0_W1_MSW_W = (sinetable[sample]) ; // Send right sample | |
| 153 | 134 | I2S0_W1_LSW_W = 0; | ||
| 154 | /* Write Digital audio input */ | |||
| 155 | while((Xmit & I2S0_IR) == 0); // Wait for receive interrupt to be pending | 135 | while((Xmit & I2S0_IR) == 0); // Wait for interrupt | |
| 156 | I2S0_W0_MSW_W = data1; // 16 bit left channel transmit audio data | |||
| 157 | I2S0_W1_MSW_W = data2; // 16 bit right channel transmit audio data | |||
| 158 | } | = | 136 | } |
| <> | 137 | |||
| 159 | } | = | 138 | } |
| 160 | } | 139 | } | |
| 161 | /* Disble I2S */ | 140 | /* Disble I2S */ | |
| 162 | I2S0_CR = 0x00; | 141 | I2S0_CR = 0x00; | |
| 163 | 142 | |||
| 164 | return 0; | 143 | return 0; | |
| 165 | } | 144 | } |