codec settings diff
Produced: 11/14/2014 8:57:43 AM
   
Mode:  All Lines  
   
Left file: 2014-11-14 - aic3204 config code compare.txt  
Right file: aic3204\aic3204_loop_stereo_in1.c  

1	* Configuring the Clock*/	<>
2			1	/*
3	/*void Set_PLL(void) {		2	*  Copyright 2010 by Spectrum Digital Incorporated.
			3	*  All rights reserved. Property of Spectrum Digital Incorporated.
4			4	*/
5		=	5
6		<>	6	/*
7			7	*  AIC3204 Tone
8	CONFIG_SW = 0x0; // Bypass the PLL
9			8	*
10			9	*/
11	PLL_CNTL2 = 0x8000;		10	#include "stdio.h"
12	PLL_CNTL4 = 0x0000;		11	#include "usbstk5515.h"
13	PLL_CNTL3 = 0x0806;		12	extern Int16 AIC3204_rset( Uint16 regnum, Uint16 regval);
14	PLL_CNTL1 = 0x8BB4;		13	#define Rcv 0x08
15	while ( (PLL_CNTL3 & 0x0008) == 0) CONFIG_SW = 0x1; //Switch to the PLL after configuration of PLL
16			14	#define Xmit 0x20
17		=	15
18	}	<>	16	/* ------------------------------------------------------------------------ *
19	*/		17	*                                                                          *
20			18	*  AIC3204 Loop                                                            *
21	Int16 AIC3204_rset( Uint16 regnum, Uint16 regval )		19	*      Output input from STEREO IN 1 through the HEADPHONE jack            *
			20	*                                                                          *
			21	* ------------------------------------------------------------------------ */
			22	Int16 aic3204_loop_stereo_in1( )
22	{	=	23	{
23	Uint8 cmd[2];	<>	24	/* Pre-generated sine wave data, 16-bit signed samples */
24	cmd[0] = regnum & 0x007F; // 7-bit Register Address
25	cmd[1] = regval; // 8-bit Register Data
26			25	Int16 j, i = 0;
27	return USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 2 ); }
28
29	void Codec_setting(void) {
30	Int16 data1, data2, data3, data4;		26	Int16 sample, data1, data2, data3, data4;
31	USBSTK5515_init( );
32	SYS_EXBUSSEL = 0x6100; // Enable I2C bus
33	USBSTK5515_I2C_init( );
34			27
			28	/* Configure AIC3204 */
35		=	29
36	// Setting up the Codec for Capturing the data	<>
37	AIC3204_rset( 0, 0 ); // initialize to page 0 of the Memory Map.		30	AIC3204_rset( 0, 0 );        // Select page 0
38	AIC3204_rset( 1, 1 ); // Software Reset to initialize all the register.		31	AIC3204_rset( 1, 1 );         // Reset codec
39	AIC3204_rset( 0, 1 ); // Selecting the page 1 of the Memory Map.		32	AIC3204_rset( 0, 1 );         // Select page 1
40	AIC3204_rset( 1, 0x088 ); // Disable crude AVDD generation from DVDD.		33	AIC3204_rset( 1, 8 );         // Disable crude AVDD generation from DVDD
41	AIC3204_rset( 71, 0x31 ); // Analogue input charge-time (3.1ms)
42	AIC3204_rset(123, 0x01 ); // REF charging time 40ms		34	AIC3204_rset( 2, 1 );        // Enable Analog Blocks, use LDO power
43	AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks, use LDO power, voltage set =1.67
44	AIC3204_rset( 0, 0 ); // re-selecting page 0 of the Memory Map.		35	AIC3204_rset( 0, 0 );        // Select page 0
			36	/* PLL and Clocks config and Power Up  */
45	AIC3204_rset(27,0x00); // 0x0d Setting the WCLK and BCLK as o/p to AIC3204(Master) Using Audio Interfacing Register1		37	AIC3204_rset( 27, 0x0d );     // BCLK and WCLK is set as o/p to AIC3204(Master)
46	AIC3204_rset(28,0x00); // The data offset set to Zero.		38	AIC3204_rset( 28, 0x00 );     // Data ofset = 0
47	AIC3204_rset( 4, 0x07 ); //....Setting the CODEC_CLKIN to be PLL Output(0x47) going to ADC/DAC		39	AIC3204_rset( 4, 3 );        // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
48	AIC3204_rset( 6, 0x08 ); // Clock setting register,PLL CODEC setting: J=8		40	AIC3204_rset( 6, 7 );          // PLL setting: J=7
49	AIC3204_rset( 7, 0x00 ); //.... PLL setting: HI_BYTE(D=1680)		41	AIC3204_rset( 7, 0x06 );      // PLL setting: HI_BYTE(D=1680)
50	AIC3204_rset( 8, 0x00); // ....PLL setting: LO_BYTE(D=1680)		42	AIC3204_rset( 8, 0x90 );      // PLL setting: LO_BYTE(D=1680)
51	//AIC3204_rset( 30, 0x00 ); // 0x088For 32 bit clocks per frame in Master mode ONLY		43	AIC3204_rset( 30, 0x88 );     // For 32 bit clocks per frame in Master mode ONLY
52	// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs		44	// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
53	AIC3204_rset( 5, 0xA1 ); // PLL setting: Power up PLL, P=2 and R=1		45	AIC3204_rset( 5, 0x91 );      // PLL setting: Power up PLL, P=1 and R=1
54	AIC3204_rset( 13, 0x00 ); // .........Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling		46	AIC3204_rset( 13, 0 );        // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
55	AIC3204_rset( 14, 0x40 ); // .........Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080		47	AIC3204_rset( 14, 0x80 );     // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
56	AIC3204_rset( 20, 0x40 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6		48	AIC3204_rset( 20, 0x80 );     // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
57	AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4		49	AIC3204_rset( 11, 0x82 );     // Power up NDAC and set NDAC value to 2
58	AIC3204_rset( 12, 0x84 ); // Power up MDAC and set MDAC value to 4		50	AIC3204_rset( 12, 0x87 );     // Power up MDAC and set MDAC value to 7
59	AIC3204_rset( 18, 0x84 ); // Power up NADC and set NADC value to 4		51	AIC3204_rset( 18, 0x87 );     // Power up NADC and set NADC value to 7
60	AIC3204_rset( 19, 0x84 ); // Power up MADC and set MADC value to 4		52	AIC3204_rset( 19, 0x82 );     // Power up MADC and set MADC value to 2
61
62	// DAC ROUTING AND POWER UP		53	/* DAC ROUTING and Power Up */
63	AIC3204_rset( 0,0x01 ); // Select page 1		54	AIC3204_rset( 0, 0x01 );     // Select page 1
64	AIC3204_rset(12 ,0x08); //Route left DAC to HPL		55	AIC3204_rset( 12, 0x08 );     // LDAC AFIR routed to HPL
65	AIC3204_rset(13 ,0x08); //Route RIGHT DAC to HPR		56	AIC3204_rset( 13, 0x08 );     // RDAC AFIR routed to HPR
66	AIC3204_rset( 0, 0x00 ); // Select page 0		57	AIC3204_rset( 0, 0x00 );     // Select page 0
67	AIC3204_rset( 64, 0x02 ); // Left vol=right vol		58	AIC3204_rset( 64, 0x02 );     // Left vol=right vol
68	AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL		59	AIC3204_rset( 65, 0x00 );     // Left DAC gain to 0dB VOL; Right tracks Left
69	// AIC3204_rset( 66, 0x00 ); // ....Right DAC gain to 0dB VOL
70	AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel DAC Channel set up		60	AIC3204_rset( 63, 0xd4 );     // Power up left,right data paths and set channel
71	AIC3204_rset( 0, 0x01 ); // Select page 1		61	AIC3204_rset( 0, 0x01 );     // Select page 1
72	AIC3204_rset( 16, 0x10 ); // Unmute HPL , 0dB gain		62	AIC3204_rset( 16, 0x00 );     // Unmute HPL , 0dB gain
73	AIC3204_rset( 17, 0x10 ); // Unmute HPR , 0dB gain		63	AIC3204_rset( 17, 0x00 );     // Unmute HPR , 0dB gain
74	AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR		64	AIC3204_rset( 9, 0x30 );     // Power up HPL,HPR
75	AIC3204_rset( 0, 0x00 ); // Select page 0		65	AIC3204_rset( 0, 0x00 );     // Select page 0
76	USBSTK5515_wait( 500 ); // Wait		66	USBSTK5515_wait( 500 );       // Wait
77			67
78	// ADC ROUTING AND POWER UP		68	/* ADC ROUTING and Power Up */
79	AIC3204_rset( 0, 1 ); // Select page 1		69	AIC3204_rset( 0, 1 );         // Select page 1
80	AIC3204_rset( 51, 0x00 ); // Disable BIAS		70	AIC3204_rset( 0x34, 0x30 );    // STEREO 1 Jack
81	AIC3204_rset( 52, 0x0C ); // STEREO 1 Jack		71	// IN2_L to LADC_P through 40 kohm
82	// IN2_L to LADC_P through 40 kohm
83	AIC3204_rset( 55, 0x0C ); // IN2_R to RADC_P through 40 kohmm		72	AIC3204_rset( 0x37, 0x30 );   // IN2_R to RADC_P through 40 kohmm
84	AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm		73	AIC3204_rset( 0x36, 3 );      // CM_1 (common mode) to LADC_M through 40 kohm
85	AIC3204_rset( 57, 0xc0 ); // common mode to RADC_M through 40 kohm		74	AIC3204_rset( 0x39, 0xc0 );   // CM_1 (common mode) to RADC_M through 40 kohm
86	AIC3204_rset( 59, 0x00 ); // Unmute left MIC PGA Gain selection of 6dB to make channel gain 0dB		75	AIC3204_rset( 0x3b, 0 );       // MIC_PGA_L unmute
87	AIC3204_rset( 60, 0x00 ); // Unmute right MIC PGA Gain selection of 6dB to make channel gain 0dB		76	AIC3204_rset( 0x3c, 0 );       // MIC_PGA_R unmute
88	AIC3204_rset( 0, 0x00 ); // Select page 0		77	AIC3204_rset( 0, 0 );         // Select page 0
89	AIC3204_rset( 81, 0x0C ); // Powerup Left and Right ADC Channels		78	AIC3204_rset( 0x51, 0xc0 );   // Powerup Left and Right ADC
90	AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC		79	AIC3204_rset( 0x52, 0 );      // Unmute Left and Right ADC
91			80
92
93	AIC3204_rset( 0, 0 );		81	AIC3204_rset( 0, 0 );
94	USBSTK5515_wait( 200 ); // Wait		82	USBSTK5515_wait( 200 );       // Wait
95	/* I2S settings */		83	/* I2S settings */
96	I2S0_CR = 0x8012; // I2SSCTRR 16-bit word, slave, enable I2C		84	I2S0_SRGR = 0x0;
97	I2S0_SRGR = 0x2a; //I2SSRATE Register should be configured if I2S0 is the master		85	I2S0_CR = 0x8010;    // 16-bit word, slave, enable I2C
98	I2S0_ICMR = 0x0028; // Enable interrupts		86	I2S0_ICMR = 0x3f;   // Enable interrupts
			87
			88	/* Play Tone */
			89	for ( i = 0 ; i < 5 ; i++ )
99			90	{
			91	for ( j = 0 ; j < 1000 ; j++ )
100	//Polling the Data		92	{
			93	for ( sample = 0 ; sample < 48 ; sample++ )
101	while (1){		94	{
			95	/* Read Digital audio */
102	while((Rcv & I2S0_IR) == 0) { // Wait for interrupt pending flag		96	while((Rcv & I2S0_IR) == 0); // Wait for interrupt pending flag
103	data3 = I2S0_W0_MSW_R; // 16 bit left channel received audio data		97	data3 = I2S0_W0_MSW_R; // 16 bit left channel received audio data
104	data1 = I2S0_W0_LSW_R;		98	data1 = I2S0_W0_LSW_R;
105	data4 = I2S0_W1_MSW_R; // 16 bit right channel received audio data		99	data4 = I2S0_W1_MSW_R; // 16 bit right channel received audio data
106	data2 = I2S0_W1_LSW_R;}		100	data2 = I2S0_W1_LSW_R;
107	/* Write Digital audio */		101	/* Write Digital audio */
108	while((Xmit & I2S0_IR) == 0){ // Wait for interrupt pending flag		102	while((Xmit & I2S0_IR) == 0); // Wait for interrupt pending flag
109	I2S0_W0_MSW_W = data3; // 16 bit left channel transmit audio data		103	I2S0_W0_MSW_W = data3; // 16 bit left channel transmit audio data
110	I2S0_W0_LSW_W = 0;		104	I2S0_W0_LSW_W = 0;
111	I2S0_W1_MSW_W = data4; // 16 bit right channel transmit audio data		105	I2S0_W1_MSW_W = data4; // 16 bit right channel transmit audio data
112	I2S0_W1_LSW_W = 0;}		106	I2S0_W1_LSW_W = 0;
113			107	}
114	}		108	}
			109	}
			110	/* Disble I2S */
			111	I2S0_CR = 0x00;
			112
			113	return 0;
115	}	=	114	}