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IBL Configuration
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Emif controller 4.0 configuration. More...
#include <ibl.h>
Data Fields | |
| uint32 | registerMask |
| uint32 | sdRamConfig |
| uint32 | sdRamConfig2 |
| uint32 | sdRamRefreshCtl |
| uint32 | sdRamTiming1 |
| uint32 | sdRamTiming2 |
| uint32 | sdRamTiming3 |
| uint32 | lpDdrNvmTiming |
| uint32 | powerManageCtl |
| uint32 | iODFTTestLogic |
| uint32 | performCountCfg |
| uint32 | performCountMstRegSel |
| uint32 | readIdleCtl |
| uint32 | sysVbusmIntEnSet |
| uint32 | sdRamOutImpdedCalCfg |
| uint32 | tempAlterCfg |
| uint32 | ddrPhyCtl1 |
| uint32 | ddrPhyCtl2 |
| uint32 | priClassSvceMap |
| uint32 | mstId2ClsSvce1Map |
| uint32 | mstId2ClsSvce2Map |
| uint32 | eccCtl |
| uint32 | eccRange1 |
| uint32 | eccRange2 |
| uint32 | rdWrtExcThresh |
Emif controller 4.0 configuration.
The parameters are placed directly into the emif controller
| uint32 ddrPhyCtl1 |
DDR PHY Control 1 Register
| uint32 ddrPhyCtl2 |
DDR PHY Control 2 Register
| uint32 eccCtl |
ECC Control Register
| uint32 eccRange1 |
ECC Address Range 1 Register
| uint32 eccRange2 |
ECC Address Range 2 Register
| uint32 iODFTTestLogic |
IODFT Test Logic Global Control Register
| uint32 lpDdrNvmTiming |
LPDDR2-NVM Timing Register
| uint32 mstId2ClsSvce1Map |
Master ID to Class of Service 1 Mapping Register
| uint32 mstId2ClsSvce2Map |
Master ID to Class of Service 2 Mapping Register
| uint32 performCountCfg |
Performance Counter Config Register
| uint32 performCountMstRegSel |
Performance Counter Master Region Select Register
| uint32 powerManageCtl |
Power Management Control Register
| uint32 priClassSvceMap |
DDR Priority to Class of Service Mapping Register
| uint32 rdWrtExcThresh |
Read Write Execution Threshold Register
| uint32 readIdleCtl |
Read Idle Control Register
| uint32 registerMask |
Identifies which registers will be configured
| uint32 sdRamConfig |
SDRAM Config Register
| uint32 sdRamConfig2 |
SDRAM Config2 Register
| uint32 sdRamOutImpdedCalCfg |
SDRAM Output Impedance Calibratin Config Register
| uint32 sdRamRefreshCtl |
SDRAM Refresh Control Register
| uint32 sdRamTiming1 |
SDRAM Timing 1 Register
| uint32 sdRamTiming2 |
SDRAM Timing 2 Register
| uint32 sdRamTiming3 |
SDRAM Timing 3 Register
| uint32 sysVbusmIntEnSet |
VBUSM Interrupt Enable Set Register
| uint32 tempAlterCfg |
Temperature Alert Config Register
1.7.4