
#include <csl_bootcfgaux.h>
#include <cslr_emif4f.h>
#include <cslr_cgem.h>
#include "KeyStone_DDR_Init.h"

CSL_BootcfgRegs * boot_cfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
CSL_Emif4fRegs * DDR_Regs= (CSL_Emif4fRegs *)CSL_DDR3_EMIF_CONFIG_REGS;
CSL_CgemRegs * CGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;

void c_int00()
{    
         int i;
		 float clock_MHz = 500;
         CSL_BootCfgUnlockKicker();
		 boot_cfg_regs->DDR3_CONFIG_REG[0] |= 0xF;	// set dll_lock_diff to 15

		//initial vale for leveling  //
		/*WRLVL_INIT_RATIO*/													  
		boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x63;								  
		boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x5D;								  
		boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x46;								  
		boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x3E;								  
		boot_cfg_regs->DDR3_CONFIG_REG[6] = 0xA ;								  
		boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x0 ;								  
		boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x0 ;								  
		boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x0 ;								  
		boot_cfg_regs->DDR3_CONFIG_REG[10]= 0x17;								 
																					  
		/*GTLVL_INIT_RATIO*/													  
		boot_cfg_regs->DDR3_CONFIG_REG[14] = 0x1A7; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x18B; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[16] = 0x180; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[17] = 0x166; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[18] = 0x150; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[19] = 0x145; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[20] = 0x124; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[21] = 0x127; 							   
		boot_cfg_regs->DDR3_CONFIG_REG[22] = 0x165; 							   
	
		///ECO#1 Implementation for Appleton
		//clear bits 9:0
		boot_cfg_regs->DDR3_CONFIG_REG[52] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[53] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[54] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[55] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[56] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[57] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[58] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[59] &= 0xFFFFFC00;
		boot_cfg_regs->DDR3_CONFIG_REG[60] &= 0xFFFFFC00;
	
		//set bit 9, set bits 8:0 to 0[50]
		boot_cfg_regs->DDR3_CONFIG_REG[52] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[53] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[54] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[55] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[56] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[57] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[58] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[59] |= 0x00000250;
		boot_cfg_regs->DDR3_CONFIG_REG[60] |= 0x00000250;
		
		//boot_cfg_regs->DDR3_CONFIG_REG[23] |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
		//boot_cfg_regs->DDR3_CONFIG_REG[23] &= ~(0x00000200); //Clear bit 9 = 1 to use full auto leveling + incremental leveling
	
		/*the PHY_RESET is pulsed (0 -> 1 -> 0) to latch these 
		leveling configuration values into the PHY logic.*/
		DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);
		DDR_Regs->DDR_PHY_CTRL_1 |= (0x00008000);
		DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);
	
	
		/*Drives CKE low.
		This is a JEDEC requirement that we have 500us delay between reset de-assert 
		and cke assert and then program the correct refresh rate
		The DDR internal clock is divide by 16 before SDCFG write*/
		DDR_Regs->SDRAM_REF_CTRL = 0x80000000|(unsigned int)(500.f*clock_MHz/16.f);
	
		DDR_Regs->SDRAM_TIM_1 =    //
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RP_SHIFT)|
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RCD_SHIFT)|
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WR_SHIFT)|
			((unsigned int)(36*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RAS_SHIFT)|
			((unsigned int)(49.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RC_SHIFT)|
			((unsigned int)(30*clock_MHz/4000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RRD_SHIFT)|	/*T_RRD = (tFAW/(4*tCK)) C 1*/
			(_max2(4-1, (unsigned int)(7.5*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WTR_SHIFT);
		DDR_Regs->SDRAM_TIM_2	= 
			(_max2(3-1, (unsigned int)(6*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XP_SHIFT)|
			(_max2(5-1, (unsigned int)((110+10)*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSNR_SHIFT)|	/*T_XSNR = (tXS /tCK)C 1*/
			((512-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSRD_SHIFT)| 	/*T_XSRD =tXSDLLC 1*/
			(_max2(4-1, (unsigned int)(7.5*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_RTP_SHIFT)|
			(_max2(3-1, (unsigned int)(5.625*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_CKE_SHIFT);
		DDR_Regs->SDRAM_TIM_3	= 
			(5<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_PDLL_UL_SHIFT)|	/*This field must always be programmed to 0x5.*/
			((5)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_CSTA_SHIFT)| 	/*This field should be set according to PHY requirements as 0x5.*/
			((unsigned int)(5.625*clock_MHz/1000.f+0.9999f)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_CKESR_SHIFT)|
			((64-1)<<CSL_EMIF4F_SDRAM_TIM_3_REG_ZQ_ZQCS_SHIFT)|
			((unsigned int)(110*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RFC_SHIFT)|
			(15<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RAS_MAX_SHIFT);	/*This field must always be programmed to 0xF.*/
	
		DDR_Regs->DDR_PHY_CTRL_1  = 0x00100100|
			(16<<CSL_EMIF4F_DDR_PHY_CTRL_1_REG_READ_LATENCY_SHIFT); 	/*between CAS Latency + 1 and CAS Latency + 7*/
	
		DDR_Regs->ZQ_CONFIG = 
			((0)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS1EN_SHIFT)|
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS0EN_SHIFT)|
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_DUALCALEN_SHIFT)| 	/*This bit should always be set to 1.*/
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_SFEXITEN_SHIFT)|
			((512/256-1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQINIT_MULT_SHIFT)|	/*T_ZQ_ZQINIT_MULT = (tZQinit/tZQoper C 1)*/
			((256/64-1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_SHIFT)|	/*T_ZQ_ZQCL_MULT = (tZQoper/tZQCS C 1)*/
			/*interval between ZQCS commands = 0.5%/((TSens x Tdriftrate) + (VSens x Vdriftrate))
			=0.5%/((max (dRTTdT, dRONdTM) x Tdriftrate in C/second) + (max(dRTTdV, dRONdVM) x Vdriftrate in mV/second))
			this time need be converted to refresh period number*/
			((151515151/(64000000/8192))<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_REFINTERVAL_SHIFT);
	
		/*map priority 0,1,2,3 to COS0,
		map priority 3,5,6,7 to COS1*/
		DDR_Regs->PRI_COS_MAP = 
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_COS_MAP_EN_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_7_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_6_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_5_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_4_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_3_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_2_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_1_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_0_COS_SHIFT);
	
		/*master based COS map is disabled*/
		DDR_Regs->MSTID_COS_1_MAP= 0;
		DDR_Regs->MSTID_COS_2_MAP= 0;
	
		/*LAT_CONFIG*/
		DDR_Regs->VBUSM_CONFIG= 
			(8<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_1_SHIFT)|
			(16<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_2_SHIFT)|
			(32<<CSL_EMIF4F_VBUSM_CONFIG_REG_PR_OLD_COUNT_SHIFT);
	
		DDR_Regs->ECC_CTRL = 
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_EN_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_SHIFT);
	
		DDR_Regs->ECC_ADDR_RNG_1= 
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_SHIFT);
	
		DDR_Regs->ECC_ADDR_RNG_2= 
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_SHIFT);
	
		/* enables DRAM configuration.	It still has the refresh interval 
		programmed to the longer number needed during DRAM initialization.*/
		DDR_Regs->SDRAM_REF_CTRL = (unsigned int)(500.f*clock_MHz/16.f); 
	
		DDR_Regs->SDRAM_CONFIG = 
			(3<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_TYPE_SHIFT)|	/*Set to 3 for DDR3. All other values reserved.*/
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_POS_SHIFT)|
			(DDR_TERM_RZQ_OVER_6<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_TERM_SHIFT)|
			(DDR_DYN_ODT_OVER_4<<CSL_EMIF4F_SDRAM_CONFIG_REG_DYN_ODT_SHIFT)|
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_DISABLE_DLL_SHIFT)|
			(SDRAM_DRIVE_RZQ_OVER_6<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_DRIVE_SHIFT)|
			(DDR_CWL_7<<CSL_EMIF4F_SDRAM_CONFIG_REG_CWL_SHIFT)|
			(DDR_BUS_WIDTH_64<<CSL_EMIF4F_SDRAM_CONFIG_REG_NARROW_MODE_SHIFT)|
			(DDR_CL_10<<CSL_EMIF4F_SDRAM_CONFIG_REG_CL_SHIFT)|
			(DDR_ROW_SIZE_14_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)|
			(DDR_BANK_NUM_8<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_SHIFT)|
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_EBANK_SHIFT)|
			(DDR_PAGE_SIZE_10_BIT_1024_WORD<<CSL_EMIF4F_SDRAM_CONFIG_REG_PAGESIZE_SHIFT);
	
		for(i=0;i<100000;i++)
			asm(" nop");	//Wait 600us for HW init to complete
	
	//	DDR_Regs->SDRAM_REF_CTRL	= 64000000/8192/(1000/clock_MHz);
		DDR_Regs->SDRAM_REF_CTRL	= (unsigned int)64000.f*clock_MHz/8192.f;
	
		//enable full leveling, no incremental leveling
		/*Typically program a higher rate of incremental leveling in the ramp window*/
		DDR_Regs->RDWR_LVL_RMP_WIN = 10000/7.8; 	/*10000us*/
		DDR_Regs->RDWR_LVL_RMP_CTRL = 
			(1<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDWRLVL_EN_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDWRLVLINC_RMP_PRE_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDLVLINC_RMP_INT_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_RDLVLGATEINC_RMP_INT_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_RMP_CTRL_REG_WRLVLINC_RMP_INT_SHIFT);
		DDR_Regs->RDWR_LVL_CTRL = 
			(1<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDWRLVLFULL_START_SHIFT)|
			(0x7F<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDWRLVLINC_PRE_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDLVLINC_INT_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_RDLVLGATEINC_INT_SHIFT)|
			(0<<CSL_EMIF4F_RDWR_LVL_CTRL_REG_WRLVLINC_INT_SHIFT);
	
		for(i=0;i<1000000;i++)
			asm(" nop 5");	//Wait 3ms for leveling to complete
	
		//Read MMR to ensure full leveling is complete
		i= DDR_Regs->RDWR_LVL_RMP_CTRL;
		
		if(DDR_Regs->STATUS&(CSL_EMIF4F_STATUS_REG_RDLVLGATETO_MASK
			|CSL_EMIF4F_STATUS_REG_RDLVLTO_MASK
			|CSL_EMIF4F_STATUS_REG_WRLVLTO_MASK))
		{
			
			return;
		}

}

