/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Project		: DM814X
File		: DM814X_1.0.gel
Owner		: raj@ti.com
Purpose		: DM814X System initilization function
Desciption	: Contains intilization routines for DDR2, IVAHD0, UART, TIMER, DUCATI
Version	Hystory	
---------------
Version		Date			Who		 		Description 		
-------		-----------		------		 	-----------
Ver1.0   	11-March-2010	Rajesh		 	Consolidated init sequence for DDR,IVA,DSP,DSS,ISS etc

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/

#define PRCM_BASE_ADDR			0x48180000
#define DMM_BASE_ADDR			0x4E000000
#define EMIF4_0_CFG_BASE_ADDR	0x4C000000
#define EMIF4_1_CFG_BASE_ADDR	0x4D000000 
#define GPMC_MEM_BASE_ADDR		0x02000000
#define DDR_MEM_BASE_ADDR		0x80000000
#define DUCATI_BASE_ADDR	    0x55020000
#define DUCATI_MMU_CFG			0x55080000
#define CTRL_MODULE_BASE_ADDR	0x48140000
#define GEM_L2RAM_BASE_ADDR		0x40800000

/* Control Module*/
#define	CM_CTRL_CLKCTRL			0x481815c4
#define DSPBOOTADDR				(CTRL_MODULE_BASE_ADDR + 0x0048) 
#define DSPMEM_SLEEP			(CTRL_MODULE_BASE_ADDR + 0x0650) 
#define GMII_SELECT			    (CTRL_MODULE_BASE_ADDR + 0x0650) 
#define CM_ALWON_L3_SLOW_CLKSTCTRL	(PRCM_BASE_ADDR + 0x1400)

/*UART*/
#define CM_ALWON_UART_0_CLKCTRL 	(PRCM_BASE_ADDR + 0x1550)
#define CM_ALWON_UART_1_CLKCTRL 	(PRCM_BASE_ADDR + 0x1554)
#define CM_ALWON_UART_2_CLKCTRL 	(PRCM_BASE_ADDR + 0x1558)
#define CM_ALWON_UART_3_CLKCTRL		(PRCM_BASE_ADDR + 0x1580)
#define CM_DEFAULT_DUCATI_CLKSTCTRL	(PRCM_BASE_ADDR + 0x0518)
#define CM_DEFAULT_DUCATI_CLKCTRL	(PRCM_BASE_ADDR + 0x0574)
#define RM_DEFAULT_RSTCTRL		(PRCM_BASE_ADDR + 0x0B10)
#define RM_DEFAULT_RSTST		(PRCM_BASE_ADDR + 0x0B14)
#define CM_ALWON_OCMC_0_CLKSTCTRL	(PRCM_BASE_ADDR + 0x1414) 
#define CM_ALWON_OCMC_0_CLKCTRL		(PRCM_BASE_ADDR + 0x15B4) 
#define CM_ALWON_GPMC_CLKCTRL		(PRCM_BASE_ADDR + 0x15D0) 

/*IVAHD0 PRCM Definition*/
#define CM_IVAHD0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x0600) 
#define CM_IVAHD0_IVAHD_CLKCTRL		(PRCM_BASE_ADDR + 0x0620) 
#define CM_IVAHD0_SL2_CLKCTRL		(PRCM_BASE_ADDR + 0x0624)  
#define PM_IVAHD0_PWRSTST		(PRCM_BASE_ADDR + 0x0C04)  
#define RM_IVAHD0_RSTCTRL		(PRCM_BASE_ADDR + 0x0C10)  
#define RM_IVAHD0_RSTST		        (PRCM_BASE_ADDR + 0x0C14)  
/*END OF IVAHD0 PRCM Definition*/ 

/*ISS PRCM Definition*/
#define CM_ISS_CLKSTCTRL	    	(PRCM_BASE_ADDR + 0x0700) 
#define CM_ISS_IVAHD_CLKCTRL     	(PRCM_BASE_ADDR + 0x0720) 
#define CM_ISS_SL2_CLKCTRL       	(PRCM_BASE_ADDR + 0x0724)  
#define PM_ISS_PWRSTST           	(PRCM_BASE_ADDR + 0x0D04)  
#define RM_ISS_RSTCTRL			(PRCM_BASE_ADDR + 0x0D10)  
#define RM_ISS_RSTST		        (PRCM_BASE_ADDR + 0x0D14)  
/*END OF ISS PRCM Definition*/ 

/*GEMSS PRCEM definition*/
#define CM_GEM_CLKSTCTRL		(PRCM_BASE_ADDR + 0x0400) 
#define CM_ACTIVE_GEM_CLKCTRL		(PRCM_BASE_ADDR + 0x0420)
#define PM_ACTIVE_PWRSTST		(PRCM_BASE_ADDR + 0x0A04)
#define RM_ACTIVE_RSTCTRL		(PRCM_BASE_ADDR + 0x0A10) 
#define RM_ACTIVE_RSTST			(PRCM_BASE_ADDR + 0x0A14) 

#define CM_MMU_CLKSTCTRL		(PRCM_BASE_ADDR + 0x140C) 
#define CM_ALWON_MMUDATA_CLKCTRL	(PRCM_BASE_ADDR + 0x159C) 

#define CM_MMUCFG_CLKSTCTRL 		(PRCM_BASE_ADDR + 0x1410) 
#define CM_ALWON_MMUCFG_CLKCTRL  	(PRCM_BASE_ADDR + 0x15A8) 
/*END OF GEMSS PRCM Definition*/ 


//TPPSS
#define CM_DEFAULT_TPPSS_CLKCTRL	(PRCM_BASE_ADDR + 0x554)
#define TPPIRAM_BASE_ADDR		(0x57180000)

/*EMIF4 PRCM Defintion*/
#define CM_DEFAULT_L3_FAST_CLKSTCTRL	(PRCM_BASE_ADDR + 0x0508)    
#define CM_DEFAULT_EMIF_0_CLKCTRL		(PRCM_BASE_ADDR + 0x0520)
#define CM_DEFAULT_EMIF_1_CLKCTRL    	(PRCM_BASE_ADDR + 0x0524)
#define CM_DEFAULT_DMM_CLKCTRL 			(PRCM_BASE_ADDR + 0x0528)
#define CM_DEFAULT_FW_CLKCTRL 			(PRCM_BASE_ADDR + 0x052C)
/*end of EMIF4 PRCM definition*/

/* McASP2 PRCM definitions */
#define CM_ALWON_MCA_0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1540)
#define CM_ALWON_MCA_1_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1544)
#define CM_ALWON_MCA_2_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1548)
#define CM_ALWON_I2C_0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1564)
#define CM_ALWON_I2C_1_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1568)
#define CM_ALWON_MCA_345_CLKSTCTL       (PRCM_BASE_ADDR + 0x156C)
#define CM_ALWON_SPI_0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1590)
#define CM_ALWON_MMC_HS_0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x161C)
#define CM_ALWON_MMC_HS_1_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1620)
#define MC_ALWON_ETHNET_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1404)
#define MC_ALWON_ETH_0_CLKSTCTRL		(PRCM_BASE_ADDR + 0x15D4)
#define MC_ALWON_ETH_1_CLKSTCTRL		(PRCM_BASE_ADDR + 0x15D8)
#define CM_ALWON_DCAN_0_CLKCTRL         (PRCM_BASE_ADDR + 0x1618)

/* Keypad GPIO PRCM definitions */
#define CM_ALWON_GPIO_0_CLKCTRL			(PRCM_BASE_ADDR + 0x155C)
#define CM_ALWON_GPIO_1_CLKCTRL			(PRCM_BASE_ADDR + 0x1560)

/*DMM & EMIF4 MMR Declaration*/
#define DMM_LISA_MAP__0					(DMM_BASE_ADDR + 0x40)
#define DMM_LISA_MAP__1					(DMM_BASE_ADDR + 0x44)
#define DMM_LISA_MAP__2					(DMM_BASE_ADDR + 0x48)
#define DMM_LISA_MAP__3					(DMM_BASE_ADDR + 0x4C)
#define DMM_PAT_BASE_ADDR 				(DMM_BASE_ADDR + 0x460)

#define EMIF4_0_SDRAM_CONFIG			(EMIF4_0_CFG_BASE_ADDR + 0x08)	
#define EMIF4_0_SDRAM_CONFIG2			(EMIF4_0_CFG_BASE_ADDR + 0x0C)	
#define EMIF4_0_SDRAM_REF_CTRL			(EMIF4_0_CFG_BASE_ADDR + 0x10)	
#define EMIF4_0_SDRAM_REF_CTRL_SHADOW	(EMIF4_0_CFG_BASE_ADDR + 0x14)	
#define EMIF4_0_SDRAM_TIM_1				(EMIF4_0_CFG_BASE_ADDR + 0x18)	
#define EMIF4_0_SDRAM_TIM_1_SHADOW		(EMIF4_0_CFG_BASE_ADDR + 0x1C)	
#define EMIF4_0_SDRAM_TIM_2				(EMIF4_0_CFG_BASE_ADDR + 0x20)	
#define EMIF4_0_SDRAM_TIM_2_SHADOW		(EMIF4_0_CFG_BASE_ADDR + 0x24)	
#define EMIF4_0_SDRAM_TIM_3				(EMIF4_0_CFG_BASE_ADDR + 0x28)	
#define EMIF4_0_SDRAM_TIM_3_SHADOW		(EMIF4_0_CFG_BASE_ADDR + 0x2C)	
#define EMIF4_0_DDR_PHY_CTRL_1			(EMIF4_0_CFG_BASE_ADDR + 0xE4)	
#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW	(EMIF4_0_CFG_BASE_ADDR + 0xE8)	
#define EMIF4_0_IODFT_TLGC			    (EMIF4_0_CFG_BASE_ADDR + 0x60)	

#define EMIF4_1_SDRAM_CONFIG			(EMIF4_1_CFG_BASE_ADDR + 0x08)	
#define EMIF4_1_SDRAM_CONFIG2			(EMIF4_1_CFG_BASE_ADDR + 0x0C)	
#define EMIF4_1_SDRAM_REF_CTRL			(EMIF4_1_CFG_BASE_ADDR + 0x10)	
#define EMIF4_1_SDRAM_REF_CTRL_SHADOW	(EMIF4_1_CFG_BASE_ADDR + 0x14)	
#define EMIF4_1_SDRAM_TIM_1				(EMIF4_1_CFG_BASE_ADDR + 0x18)	
#define EMIF4_1_SDRAM_TIM_1_SHADOW		(EMIF4_1_CFG_BASE_ADDR + 0x1C)	
#define EMIF4_1_SDRAM_TIM_2				(EMIF4_1_CFG_BASE_ADDR + 0x20)	
#define EMIF4_1_SDRAM_TIM_2_SHADOW		(EMIF4_1_CFG_BASE_ADDR + 0x24)	
#define EMIF4_1_SDRAM_TIM_3				(EMIF4_1_CFG_BASE_ADDR + 0x28)	
#define EMIF4_1_SDRAM_TIM_3_SHADOW		(EMIF4_1_CFG_BASE_ADDR + 0x2C)	
#define EMIF4_1_DDR_PHY_CTRL_1			(EMIF4_1_CFG_BASE_ADDR + 0xE4)	 
#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW	(EMIF4_1_CFG_BASE_ADDR + 0xE8)	 
#define EMIF4_1_IODFT_TLGC			    (EMIF4_1_CFG_BASE_ADDR + 0x60)	


#define	   DDR0_PHY_BASE_ADDR	0x47C0C400
#define	   DDR1_PHY_BASE_ADDR	0x47C0C800
#define	   DDR0_IO_CTRL	       0x48140E04
#define	   DDR1_IO_CTRL	       0x48140E08
#define	   VTP0_CTRL_REG       0x48140E0C
#define	   VTP1_CTRL_REG       0x48140E10
#define	   EMIF4_0_CFG_BASE_ADDR		0x4C000000
#define    EMIF4_1_CFG_BASE_ADDR		0x4D000000 
#define	   DMM_BASE_ADDR			0x4E000000

#define EMIF4_0_RDWR_LVL_RMP_CTRL		(EMIF4_0_CFG_BASE_ADDR + 0xD8)	
#define EMIF4_0_RDWR_LVL_CTRL			(EMIF4_0_CFG_BASE_ADDR + 0xDC)	
#define EMIF4_1_RDWR_LVL_RMP_CTRL		(EMIF4_1_CFG_BASE_ADDR + 0xD8)	
#define EMIF4_1_RDWR_LVL_CTRL			(EMIF4_1_CFG_BASE_ADDR + 0xDC)	

#define	   CMD0_REG_PHY0_CTRL_SLAVE_RATIO_0	(0x01C + DDR0_PHY_BASE_ADDR)
#define	   CMD0_REG_PHY0_DLL_LOCK_DIFF_0 	(0x028 + DDR0_PHY_BASE_ADDR)
#define	   CMD0_REG_PHY0_INVERT_CLKOUT_0 	(0x02C + DDR0_PHY_BASE_ADDR)
#define	   CMD1_REG_PHY0_CTRL_SLAVE_RATIO_0 	(0x050 + DDR0_PHY_BASE_ADDR)
#define	   CMD1_REG_PHY0_DLL_LOCK_DIFF_0	(0x05C + DDR0_PHY_BASE_ADDR)
#define	   CMD1_REG_PHY0_INVERT_CLKOUT_0	(0x060 + DDR0_PHY_BASE_ADDR)
#define	   CMD2_REG_PHY0_CTRL_SLAVE_RATIO_0	(0x084 + DDR0_PHY_BASE_ADDR)
#define	   CMD2_REG_PHY0_DLL_LOCK_DIFF_0	(0x090 + DDR0_PHY_BASE_ADDR)
#define	   CMD2_REG_PHY0_INVERT_CLKOUT_0	(0x094 + DDR0_PHY_BASE_ADDR)

//- Common DDR PHY parameters
#define	   PHY_INVERT_CLKOUT_DEFINE		 0
#define	   DDR3_PHY_INVERT_CLKOUT_DEFINE	 0
#define	   PHY_REG_USE_RANK0_DELAY_DEFINE	 0
#define	   mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE	 1
#define	   PHY_DLL_LOCK_DIFF_DEFINE 	        0x4
#define	   PHY_CMD0_DLL_LOCK_DIFF_DEFINE	0x4

#define	   PHY_GATELVL_INIT_CS0_DEFINE           0x0
#define	   PHY_WRLVL_INIT_CS0_DEFINE		 0x0

#define	   PHY_GATELVL_INIT_CS1_DEFINE           0x0
#define	   PHY_WRLVL_INIT_CS1_DEFINE		 0x0
#define	   PHY_CTRL_SLAVE_RATIO_CS1_DEFINE       0x80 

//- DDR2 parameters
#define    DDR2_EMIF_READ_LATENCY_DEFINE	0x09	
#define    DDR2_EMIF_TIM1_DEFINE		0x0EF197EC
#define    DDR2_EMIF_TIM2_DEFINE		0x144931E2
#define    DDR2_EMIF_TIM3_DEFINE		0x00000447
#define    DDR2_EMIF_REF_CTRL_DEFINE		0x1000103D
#define    DDR2_EMIF_SDRAM_CONFIG_DEFINE	0x43801E32

#define	   DDR2_PHY_RD_DQS_CS0_DEFINE	0x35
#define	   DDR2_PHY_WR_DQS_CS0_DEFINE	0x20
#define	   DDR2_PHY_FIFO_WE_CS0_DEFINE	0x90
#define	   DDR2_PHY_WR_DATA_CS0_DEFINE	0x50
#define	   DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE       0x80

//- DDR3 parameters

#define    DDR3_EMIF_READ_LATENCY_DEFINE	0xC
#define    DDR3_EMIF_TIM1_DEFINE		0x1557B9A5
#define    DDR3_EMIF_TIM2_DEFINE		0x4C5F7FEB
#define    DDR3_EMIF_TIM3_DEFINE		0x00000578
#define    DDR3_EMIF_REF_CTRL_DEFINE		0x10001860
#define    DDR3_EMIF_SDRAM_CONFIG_DEFINE	0x62833AB2 //0x61833AB2

#define	   DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE       0x80

#define	   DDR3_PHY_RD_DQS_CS0_DEFINE   0x34 
#define	   DDR3_PHY_WR_DQS_CS0_DEFINE	0xA
#define	   DDR3_PHY_FIFO_WE_CS0_DEFINE	0xB4
#define	   DDR3_PHY_WR_DATA_CS0_DEFINE	0x4A



#define	   DDR0_DATA0_CS0_CTRL0    0x48141440
#define	   DDR0_DATA0_CS0_CTRL1    0x48141444
#define	   DDR0_DATA0_CS1_CTRL0    0x48141448
#define	   DDR0_DATA0_CS1_CTRL1    0x4814144C

#define	   DDR0_DATA1_CS0_CTRL0    0x48141450
#define	   DDR0_DATA1_CS0_CTRL1    0x48141454
#define	   DDR0_DATA1_CS1_CTRL0    0x48141458
#define	   DDR0_DATA1_CS1_CTRL1    0x4814145C

#define	   DDR0_DATA2_CS0_CTRL0    0x48141460
#define	   DDR0_DATA2_CS0_CTRL1    0x48141464
#define	   DDR0_DATA2_CS1_CTRL0    0x48141468
#define	   DDR0_DATA2_CS1_CTRL1    0x4814146C

#define	   DDR0_DATA3_CS0_CTRL0    0x48141470
#define	   DDR0_DATA3_CS0_CTRL1    0x48141474
#define	   DDR0_DATA3_CS1_CTRL0    0x48141478
#define	   DDR0_DATA3_CS1_CTRL1    0x4814147C
#define	   DDR0_DATA0_CTRL         0x48141420
#define	   DDR0_DATA1_CTRL         0x48141424
#define	   DDR0_DATA2_CTRL         0x48141428
#define	   DDR0_DATA3_CTRL         0x4814142C

#define	   DDR1_DATA0_CS0_CTRL0    0x48141540
#define	   DDR1_DATA0_CS0_CTRL1    0x48141544
#define	   DDR1_DATA0_CS1_CTRL0    0x48141548
#define	   DDR1_DATA0_CS1_CTRL1    0x4814154C

#define	   DDR1_DATA1_CS0_CTRL0    0x48141550
#define	   DDR1_DATA1_CS0_CTRL1    0x48141554
#define	   DDR1_DATA1_CS1_CTRL0    0x48141558
#define	   DDR1_DATA1_CS1_CTRL1    0x4814155C

#define	   DDR1_DATA2_CS0_CTRL0    0x48141560
#define	   DDR1_DATA2_CS0_CTRL1    0x48141564
#define	   DDR1_DATA2_CS1_CTRL0    0x48141568
#define	   DDR1_DATA2_CS1_CTRL1    0x4814156C

#define	   DDR1_DATA3_CS0_CTRL0    0x48141570
#define	   DDR1_DATA3_CS0_CTRL1    0x48141574
#define	   DDR1_DATA3_CS1_CTRL0    0x48141578
#define	   DDR1_DATA3_CS1_CTRL1    0x4814157C
#define	   DDR1_DATA0_CTRL         0x48141520
#define	   DDR1_DATA1_CTRL         0x48141524
#define	   DDR1_DATA2_CTRL         0x48141528
#define	   DDR1_DATA3_CTRL         0x4814152C

#define	   VTP0_CTRL_REG	   0x48140E0C
#define	   VTP1_CTRL_REG	   0x48140E10

#define	   PHY_WR_DQS       0x1E
#define	   PHY_WR_DATA      0x8E
#define	   PHY_FIFO_WE      0x8E
#define	   PHY_RD_DQS       0x8E // I kept same as PHY_WR_DQS --- Ankit

#define	   PHY_INVERT_CLKOUT      0
#define	   CMD_SLAVE_RATIO        0x80
#define	   DLL_LOCK_DIFF	  0x4
#define	   PHY_REG_DQ_OFFSET      0x40

#define CM_ALWON_L3_SLOW_CLKSTCTRL		(PRCM_BASE_ADDR + 0x1400)

#define CM_ALWON_TIMER_0_CLKCTRL     	(PRCM_BASE_ADDR + 0x156C)
#define CM_ALWON_TIMER_1_CLKCTRL     	(PRCM_BASE_ADDR + 0x1570) 
#define CM_ALWON_TIMER_2_CLKCTRL     	(PRCM_BASE_ADDR + 0x1574) 
#define CM_ALWON_TIMER_3_CLKCTRL     	(PRCM_BASE_ADDR + 0x1578) 
#define CM_ALWON_TIMER_4_CLKCTRL     	(PRCM_BASE_ADDR + 0x157C) 
#define CM_ALWON_TIMER_5_CLKCTRL     	(PRCM_BASE_ADDR + 0x1580) 
#define CM_ALWON_TIMER_6_CLKCTRL     	(PRCM_BASE_ADDR + 0x1584)  
#define CM_ALWON_TIMER_7_CLKCTRL     	(PRCM_BASE_ADDR + 0x1588) 
#define CM_ALWON_SYSCLK5_CLKSTCTRL	(PRCM_BASE_ADDR + 0x1424)
#define CM_ALWON_DCAN_0_1_CLKCTRL	(PRCM_BASE_ADDR + 0x1618) 

#define CM_TIMER0_CLKSEL				(PRCM_BASE_ADDR + 0x038C)
#define CM_TIMER1_CLKSEL				(PRCM_BASE_ADDR + 0x0390)
#define CM_TIMER2_CLKSEL				(PRCM_BASE_ADDR + 0x0394)
#define CM_TIMER3_CLKSEL				(PRCM_BASE_ADDR + 0x0398)
#define CM_TIMER4_CLKSEL				(PRCM_BASE_ADDR + 0x039C)
#define CM_TIMER5_CLKSEL				(PRCM_BASE_ADDR + 0x03A0)
#define CM_TIMER6_CLKSEL				(PRCM_BASE_ADDR + 0x03A4)
#define CM_TIMER7_CLKSEL				(PRCM_BASE_ADDR + 0x03A8)

#define CM_HDVPSS_CLKSTCTRL				(PRCM_BASE_ADDR + 0x0800)
#define CM_HDVPSS_HDVPSS_CLKCTRL		(PRCM_BASE_ADDR + 0x0820)
#define CM_HDVPSS_HDMI_CLKCTRL			(PRCM_BASE_ADDR + 0x0824)

#define WR_MEM_32(addr, data)    *(unsigned int*)(addr) =(unsigned int)(data)
#define RD_MEM_32(addr) 		 *(unsigned int*)(addr)

#define SIZE 1
#define DATA_SIZE 10
#define OCMC0RAM_BASE_ADDR 				0x40300000
#define OCMC1RAM_BASE_ADDR 				0x40400000

#define DELAY_TIME  5
#define DMTIMER0_BASE_ADDR 				0x4802C000
#define DMTIMER1_BASE_ADDR 				0x4802E000
#define DMTIMER2_BASE_ADDR 				0x48040000
#define DMTIMER3_BASE_ADDR 				0x48042000
#define DMTIMER4_BASE_ADDR 				0x48044000
#define DMTIMER5_BASE_ADDR 				0x48046000
#define DMTIMER6_BASE_ADDR 				0x48048000
#define DMTIMER7_BASE_ADDR 				0x4804A000

#define OB_SIZE                     	0x1
#define PCIE_REGISTER_BASE          	0x51000000
#define PCIE_TARGET                 	0x20000000

#define EP_APPL_OB_SIZE             	0x30
#define EP_APPL_OB_OFFSET_INDEX(n)  	0x200 + 8 * n
#define EP_APPL_OB_OFFSET_HI(n)     	0x204 + 8 * n
#define EP_TYP0_STAT_CMD            	0x1004
#define EP_TYP0_BAR0                	0x1010
#define EP_TYP0_BAR1                	0x1014
#define EP_APPL_CMD_STATUS          	0x4
#define EP_PL_DEBUG0                	0x1728

#define RC_APPL_OB_SIZE             0x30
#define RC_APPL_OB_OFFSET_INDEX(n)  0x200 + 8 * n
#define RC_APPL_OB_OFFSET_HI(n)     0x204 + 8 * n
#define RC_TYP1_STAT_CMD            0x1004 
#define RC_APPL_CMD_STATUS          0x4
#define RC_PL_DEBUG0                0x1728
#define RM_RC_TYP0_BAR0             0x10 + 0x2000        
#define RM_RC_TYP0_BAR1             0x14 + 0x2000


/* PIN Control defines */
					
#define	PINCNTL1	(	CTRL_MODULE_BASE_ADDR +	0x0800	)
#define	PINCNTL2	(	CTRL_MODULE_BASE_ADDR +	0x0804	)
#define	PINCNTL3	(	CTRL_MODULE_BASE_ADDR +	0x0808	)
#define	PINCNTL4	(	CTRL_MODULE_BASE_ADDR +	0x080C	)
#define	PINCNTL5	(	CTRL_MODULE_BASE_ADDR +	0x0810	)
#define	PINCNTL6	(	CTRL_MODULE_BASE_ADDR +	0x0814	)
#define	PINCNTL7	(	CTRL_MODULE_BASE_ADDR +	0x0818	)
#define	PINCNTL8	(	CTRL_MODULE_BASE_ADDR +	0x081C	)
#define	PINCNTL9	(	CTRL_MODULE_BASE_ADDR +	0x0820	)
#define	PINCNTL10	(	CTRL_MODULE_BASE_ADDR +	0x0824	)
#define	PINCNTL11	(	CTRL_MODULE_BASE_ADDR +	0x0828	)
#define	PINCNTL12	(	CTRL_MODULE_BASE_ADDR +	0x082C	)
#define	PINCNTL13	(	CTRL_MODULE_BASE_ADDR +	0x0830	)
#define	PINCNTL14	(	CTRL_MODULE_BASE_ADDR +	0x0834	)
#define	PINCNTL15	(	CTRL_MODULE_BASE_ADDR +	0x0838	)
#define	PINCNTL16	(	CTRL_MODULE_BASE_ADDR +	0x083C	)
#define	PINCNTL17	(	CTRL_MODULE_BASE_ADDR +	0x0840	)
#define	PINCNTL18	(	CTRL_MODULE_BASE_ADDR +	0x0844	)
#define	PINCNTL19	(	CTRL_MODULE_BASE_ADDR +	0x0848	)
#define	PINCNTL20	(	CTRL_MODULE_BASE_ADDR +	0x084C	)
#define	PINCNTL21	(	CTRL_MODULE_BASE_ADDR +	0x0850	)
#define	PINCNTL22	(	CTRL_MODULE_BASE_ADDR +	0x0854	)
#define	PINCNTL23	(	CTRL_MODULE_BASE_ADDR +	0x0858	)
#define	PINCNTL24	(	CTRL_MODULE_BASE_ADDR +	0x085C	)
#define	PINCNTL25	(	CTRL_MODULE_BASE_ADDR +	0x0860	)
#define	PINCNTL26	(	CTRL_MODULE_BASE_ADDR +	0x0864	)
#define	PINCNTL27	(	CTRL_MODULE_BASE_ADDR +	0x0868	)
#define	PINCNTL28	(	CTRL_MODULE_BASE_ADDR +	0x086C	)
#define	PINCNTL29	(	CTRL_MODULE_BASE_ADDR +	0x0870	)
#define	PINCNTL30	(	CTRL_MODULE_BASE_ADDR +	0x0874	)
#define	PINCNTL31	(	CTRL_MODULE_BASE_ADDR +	0x0878	)
#define	PINCNTL32	(	CTRL_MODULE_BASE_ADDR +	0x087C	)
#define	PINCNTL33	(	CTRL_MODULE_BASE_ADDR +	0x0880	)
#define	PINCNTL34	(	CTRL_MODULE_BASE_ADDR +	0x0884	)
#define	PINCNTL35	(	CTRL_MODULE_BASE_ADDR +	0x0888	)
#define	PINCNTL36	(	CTRL_MODULE_BASE_ADDR +	0x088C	)
#define	PINCNTL37	(	CTRL_MODULE_BASE_ADDR +	0x0890	)
#define	PINCNTL38	(	CTRL_MODULE_BASE_ADDR +	0x0894	)
#define	PINCNTL39	(	CTRL_MODULE_BASE_ADDR +	0x0898	)
#define	PINCNTL40	(	CTRL_MODULE_BASE_ADDR +	0x089C	)
#define	PINCNTL41	(	CTRL_MODULE_BASE_ADDR +	0x08A0	)
#define	PINCNTL42	(	CTRL_MODULE_BASE_ADDR +	0x08A4	)
#define	PINCNTL43	(	CTRL_MODULE_BASE_ADDR +	0x08A8	)
#define	PINCNTL44	(	CTRL_MODULE_BASE_ADDR +	0x08AC	)
#define	PINCNTL45	(	CTRL_MODULE_BASE_ADDR +	0x08B0	)
#define	PINCNTL46	(	CTRL_MODULE_BASE_ADDR +	0x08B4	)
#define	PINCNTL47	(	CTRL_MODULE_BASE_ADDR +	0x08B8	)
#define	PINCNTL48	(	CTRL_MODULE_BASE_ADDR +	0x08BC	)
#define	PINCNTL49	(	CTRL_MODULE_BASE_ADDR +	0x08C0	)
#define	PINCNTL50	(	CTRL_MODULE_BASE_ADDR +	0x08C4	)
#define	PINCNTL51	(	CTRL_MODULE_BASE_ADDR +	0x08C8	)
#define	PINCNTL52	(	CTRL_MODULE_BASE_ADDR +	0x08CC	)
#define	PINCNTL53	(	CTRL_MODULE_BASE_ADDR +	0x08D0	)
#define	PINCNTL54	(	CTRL_MODULE_BASE_ADDR +	0x08D4	)
#define	PINCNTL55	(	CTRL_MODULE_BASE_ADDR +	0x08D8	)
#define	PINCNTL56	(	CTRL_MODULE_BASE_ADDR +	0x08DC	)
#define	PINCNTL57	(	CTRL_MODULE_BASE_ADDR +	0x08E0	)
#define	PINCNTL58	(	CTRL_MODULE_BASE_ADDR +	0x08E4	)
#define	PINCNTL59	(	CTRL_MODULE_BASE_ADDR +	0x08E8	)
#define	PINCNTL60	(	CTRL_MODULE_BASE_ADDR +	0x08EC	)
#define	PINCNTL61	(	CTRL_MODULE_BASE_ADDR +	0x08F0	)
#define	PINCNTL62	(	CTRL_MODULE_BASE_ADDR +	0x08F4	)
#define	PINCNTL63	(	CTRL_MODULE_BASE_ADDR +	0x08F8	)
#define	PINCNTL64	(	CTRL_MODULE_BASE_ADDR +	0x08FC	)
#define	PINCNTL65	(	CTRL_MODULE_BASE_ADDR +	0x0900	)
#define	PINCNTL66	(	CTRL_MODULE_BASE_ADDR +	0x0904	)
#define	PINCNTL67	(	CTRL_MODULE_BASE_ADDR +	0x0908	)
#define	PINCNTL68	(	CTRL_MODULE_BASE_ADDR +	0x090C	)
#define	PINCNTL69	(	CTRL_MODULE_BASE_ADDR +	0x0910	)
#define	PINCNTL70	(	CTRL_MODULE_BASE_ADDR +	0x0914	)
#define	PINCNTL71	(	CTRL_MODULE_BASE_ADDR +	0x0918	)
#define	PINCNTL72	(	CTRL_MODULE_BASE_ADDR +	0x091C	)
#define	PINCNTL73	(	CTRL_MODULE_BASE_ADDR +	0x0920	)
#define	PINCNTL74	(	CTRL_MODULE_BASE_ADDR +	0x0924	)
#define	PINCNTL75	(	CTRL_MODULE_BASE_ADDR +	0x0928	)
#define	PINCNTL76	(	CTRL_MODULE_BASE_ADDR +	0x092C	)
#define	PINCNTL77	(	CTRL_MODULE_BASE_ADDR +	0x0930	)
#define	PINCNTL78	(	CTRL_MODULE_BASE_ADDR +	0x0934	)
#define	PINCNTL79	(	CTRL_MODULE_BASE_ADDR +	0x0938	)
#define	PINCNTL80	(	CTRL_MODULE_BASE_ADDR +	0x093C	)
#define	PINCNTL81	(	CTRL_MODULE_BASE_ADDR +	0x0940	)
#define	PINCNTL82	(	CTRL_MODULE_BASE_ADDR +	0x0944	)
#define	PINCNTL83	(	CTRL_MODULE_BASE_ADDR +	0x0948	)
#define	PINCNTL84	(	CTRL_MODULE_BASE_ADDR +	0x094C	)
#define	PINCNTL85	(	CTRL_MODULE_BASE_ADDR +	0x0950	)
#define	PINCNTL86	(	CTRL_MODULE_BASE_ADDR +	0x0954	)
#define	PINCNTL87	(	CTRL_MODULE_BASE_ADDR +	0x0958	)
#define	PINCNTL88	(	CTRL_MODULE_BASE_ADDR +	0x095C	)
#define	PINCNTL89	(	CTRL_MODULE_BASE_ADDR +	0x0960	)
#define	PINCNTL90	(	CTRL_MODULE_BASE_ADDR +	0x0964	)
#define	PINCNTL91	(	CTRL_MODULE_BASE_ADDR +	0x0968	)
#define	PINCNTL92	(	CTRL_MODULE_BASE_ADDR +	0x096C	)
#define	PINCNTL93	(	CTRL_MODULE_BASE_ADDR +	0x0970	)
#define	PINCNTL94	(	CTRL_MODULE_BASE_ADDR +	0x0974	)
#define	PINCNTL95	(	CTRL_MODULE_BASE_ADDR +	0x0978	)
#define	PINCNTL96	(	CTRL_MODULE_BASE_ADDR +	0x097C	)
#define	PINCNTL97	(	CTRL_MODULE_BASE_ADDR +	0x0980	)
#define	PINCNTL98	(	CTRL_MODULE_BASE_ADDR +	0x0984	)
#define	PINCNTL99	(	CTRL_MODULE_BASE_ADDR +	0x0988	)
#define	PINCNTL100	(	CTRL_MODULE_BASE_ADDR +	0x098C	)
#define	PINCNTL101	(	CTRL_MODULE_BASE_ADDR +	0x0990	)
#define	PINCNTL102	(	CTRL_MODULE_BASE_ADDR +	0x0994	)
#define	PINCNTL103	(	CTRL_MODULE_BASE_ADDR +	0x0998	)
#define	PINCNTL104	(	CTRL_MODULE_BASE_ADDR +	0x099C	)
#define	PINCNTL105	(	CTRL_MODULE_BASE_ADDR +	0x09A0	)
#define	PINCNTL106	(	CTRL_MODULE_BASE_ADDR +	0x09A4	)
#define	PINCNTL107	(	CTRL_MODULE_BASE_ADDR +	0x09A8	)
#define	PINCNTL108	(	CTRL_MODULE_BASE_ADDR +	0x09AC	)
#define	PINCNTL109	(	CTRL_MODULE_BASE_ADDR +	0x09B0	)
#define	PINCNTL110	(	CTRL_MODULE_BASE_ADDR +	0x09B4	)
#define	PINCNTL111	(	CTRL_MODULE_BASE_ADDR +	0x09B8	)
#define	PINCNTL112	(	CTRL_MODULE_BASE_ADDR +	0x09BC	)
#define	PINCNTL113	(	CTRL_MODULE_BASE_ADDR +	0x09C0	)
#define	PINCNTL114	(	CTRL_MODULE_BASE_ADDR +	0x09C4	)
#define	PINCNTL115	(	CTRL_MODULE_BASE_ADDR +	0x09C8	)
#define	PINCNTL116	(	CTRL_MODULE_BASE_ADDR +	0x09CC	)
#define	PINCNTL117	(	CTRL_MODULE_BASE_ADDR +	0x09D0	)
#define	PINCNTL118	(	CTRL_MODULE_BASE_ADDR +	0x09D4	)
#define	PINCNTL119	(	CTRL_MODULE_BASE_ADDR +	0x09D8	)
#define	PINCNTL120	(	CTRL_MODULE_BASE_ADDR +	0x09DC	)
#define	PINCNTL121	(	CTRL_MODULE_BASE_ADDR +	0x09E0	)
#define	PINCNTL122	(	CTRL_MODULE_BASE_ADDR +	0x09E4	)
#define	PINCNTL123	(	CTRL_MODULE_BASE_ADDR +	0x09E8	)
#define	PINCNTL124	(	CTRL_MODULE_BASE_ADDR +	0x09EC	)
#define	PINCNTL125	(	CTRL_MODULE_BASE_ADDR +	0x09F0	)
#define	PINCNTL126	(	CTRL_MODULE_BASE_ADDR +	0x09F4	)
#define	PINCNTL127	(	CTRL_MODULE_BASE_ADDR +	0x09F8	)
#define	PINCNTL128	(	CTRL_MODULE_BASE_ADDR +	0x09FC	)
#define	PINCNTL129	(	CTRL_MODULE_BASE_ADDR +	0x0A00	)
#define	PINCNTL130	(	CTRL_MODULE_BASE_ADDR +	0x0A04	)
#define	PINCNTL131	(	CTRL_MODULE_BASE_ADDR +	0x0A08	)
#define	PINCNTL132	(	CTRL_MODULE_BASE_ADDR +	0x0A0C	)
#define	PINCNTL133	(	CTRL_MODULE_BASE_ADDR +	0x0A10	)
#define	PINCNTL134	(	CTRL_MODULE_BASE_ADDR +	0x0A14	)
#define	PINCNTL135	(	CTRL_MODULE_BASE_ADDR +	0x0A18	)
#define	PINCNTL136	(	CTRL_MODULE_BASE_ADDR +	0x0A1C	)
#define	PINCNTL137	(	CTRL_MODULE_BASE_ADDR +	0x0A20	)
#define	PINCNTL138	(	CTRL_MODULE_BASE_ADDR +	0x0A24	)
#define	PINCNTL139	(	CTRL_MODULE_BASE_ADDR +	0x0A28	)
#define	PINCNTL140	(	CTRL_MODULE_BASE_ADDR +	0x0A2C	)
#define	PINCNTL141	(	CTRL_MODULE_BASE_ADDR +	0x0A30	)
#define	PINCNTL142	(	CTRL_MODULE_BASE_ADDR +	0x0A34	)
#define	PINCNTL143	(	CTRL_MODULE_BASE_ADDR +	0x0A38	)
#define	PINCNTL144	(	CTRL_MODULE_BASE_ADDR +	0x0A3C	)
#define	PINCNTL145	(	CTRL_MODULE_BASE_ADDR +	0x0A40	)
#define	PINCNTL146	(	CTRL_MODULE_BASE_ADDR +	0x0A44	)
#define	PINCNTL147	(	CTRL_MODULE_BASE_ADDR +	0x0A48	)
#define	PINCNTL148	(	CTRL_MODULE_BASE_ADDR +	0x0A4C	)
#define	PINCNTL149	(	CTRL_MODULE_BASE_ADDR +	0x0A50	)
#define	PINCNTL150	(	CTRL_MODULE_BASE_ADDR +	0x0A54	)
#define	PINCNTL151	(	CTRL_MODULE_BASE_ADDR +	0x0A58	)
#define	PINCNTL152	(	CTRL_MODULE_BASE_ADDR +	0x0A5C	)
#define	PINCNTL153	(	CTRL_MODULE_BASE_ADDR +	0x0A60	)
#define	PINCNTL154	(	CTRL_MODULE_BASE_ADDR +	0x0A64	)
#define	PINCNTL155	(	CTRL_MODULE_BASE_ADDR +	0x0A68	)
#define	PINCNTL156	(	CTRL_MODULE_BASE_ADDR +	0x0A6C	)
#define	PINCNTL157	(	CTRL_MODULE_BASE_ADDR +	0x0A70	)
#define	PINCNTL158	(	CTRL_MODULE_BASE_ADDR +	0x0A74	)
#define	PINCNTL159	(	CTRL_MODULE_BASE_ADDR +	0x0A78	)
#define	PINCNTL160	(	CTRL_MODULE_BASE_ADDR +	0x0A7C	)
#define	PINCNTL161	(	CTRL_MODULE_BASE_ADDR +	0x0A80	)
#define	PINCNTL162	(	CTRL_MODULE_BASE_ADDR +	0x0A84	)
#define	PINCNTL163	(	CTRL_MODULE_BASE_ADDR +	0x0A88	)
#define	PINCNTL164	(	CTRL_MODULE_BASE_ADDR +	0x0A8C	)
#define	PINCNTL165	(	CTRL_MODULE_BASE_ADDR +	0x0A90	)
#define	PINCNTL166	(	CTRL_MODULE_BASE_ADDR +	0x0A94	)
#define	PINCNTL167	(	CTRL_MODULE_BASE_ADDR +	0x0A98	)
#define	PINCNTL168	(	CTRL_MODULE_BASE_ADDR +	0x0A9C	)
#define	PINCNTL169	(	CTRL_MODULE_BASE_ADDR +	0x0AA0	)
#define	PINCNTL170	(	CTRL_MODULE_BASE_ADDR +	0x0AA4	)
#define	PINCNTL171	(	CTRL_MODULE_BASE_ADDR +	0x0AA8	)
#define	PINCNTL172	(	CTRL_MODULE_BASE_ADDR +	0x0AAC	)
#define	PINCNTL173	(	CTRL_MODULE_BASE_ADDR +	0x0AB0	)
#define	PINCNTL174	(	CTRL_MODULE_BASE_ADDR +	0x0AB4	)
#define	PINCNTL175	(	CTRL_MODULE_BASE_ADDR +	0x0AB8	)
#define	PINCNTL176	(	CTRL_MODULE_BASE_ADDR +	0x0ABC	)
#define	PINCNTL177	(	CTRL_MODULE_BASE_ADDR +	0x0AC0	)
#define	PINCNTL178	(	CTRL_MODULE_BASE_ADDR +	0x0AC4	)
#define	PINCNTL179	(	CTRL_MODULE_BASE_ADDR +	0x0AC8	)
#define	PINCNTL180	(	CTRL_MODULE_BASE_ADDR +	0x0ACC	)
#define	PINCNTL181	(	CTRL_MODULE_BASE_ADDR +	0x0AD0	)
#define	PINCNTL182	(	CTRL_MODULE_BASE_ADDR +	0x0AD4	)
#define	PINCNTL183	(	CTRL_MODULE_BASE_ADDR +	0x0AD8	)
#define	PINCNTL184	(	CTRL_MODULE_BASE_ADDR +	0x0ADC	)
#define	PINCNTL185	(	CTRL_MODULE_BASE_ADDR +	0x0AE0	)
#define	PINCNTL186	(	CTRL_MODULE_BASE_ADDR +	0x0AE4	)
#define	PINCNTL187	(	CTRL_MODULE_BASE_ADDR +	0x0AE8	)
#define	PINCNTL188	(	CTRL_MODULE_BASE_ADDR +	0x0AEC	)
#define	PINCNTL189	(	CTRL_MODULE_BASE_ADDR +	0x0AF0	)
#define	PINCNTL190	(	CTRL_MODULE_BASE_ADDR +	0x0AF4	)
#define	PINCNTL191	(	CTRL_MODULE_BASE_ADDR +	0x0AF8	)
#define	PINCNTL192	(	CTRL_MODULE_BASE_ADDR +	0x0AFC	)
#define	PINCNTL193	(	CTRL_MODULE_BASE_ADDR +	0x0B00	)
#define	PINCNTL194	(	CTRL_MODULE_BASE_ADDR +	0x0B04	)
#define	PINCNTL195	(	CTRL_MODULE_BASE_ADDR +	0x0B08	)
#define	PINCNTL196	(	CTRL_MODULE_BASE_ADDR +	0x0B0C	)
#define	PINCNTL197	(	CTRL_MODULE_BASE_ADDR +	0x0B10	)
#define	PINCNTL198	(	CTRL_MODULE_BASE_ADDR +	0x0B14	)
#define	PINCNTL199	(	CTRL_MODULE_BASE_ADDR +	0x0B18	)
#define	PINCNTL200	(	CTRL_MODULE_BASE_ADDR +	0x0B1C	)
#define	PINCNTL201	(	CTRL_MODULE_BASE_ADDR +	0x0B20	)
#define	PINCNTL202	(	CTRL_MODULE_BASE_ADDR +	0x0B24	)
#define	PINCNTL203	(	CTRL_MODULE_BASE_ADDR +	0x0B28	)
#define	PINCNTL204	(	CTRL_MODULE_BASE_ADDR +	0x0B2C	)
#define	PINCNTL205	(	CTRL_MODULE_BASE_ADDR +	0x0B30	)
#define	PINCNTL206	(	CTRL_MODULE_BASE_ADDR +	0x0B34	)
#define	PINCNTL207	(	CTRL_MODULE_BASE_ADDR +	0x0B38	)
#define	PINCNTL208	(	CTRL_MODULE_BASE_ADDR +	0x0B3C	)
#define	PINCNTL209	(	CTRL_MODULE_BASE_ADDR +	0x0B40	)
#define	PINCNTL210	(	CTRL_MODULE_BASE_ADDR +	0x0B44	)
#define	PINCNTL211	(	CTRL_MODULE_BASE_ADDR +	0x0B48	)
#define	PINCNTL212	(	CTRL_MODULE_BASE_ADDR +	0x0B4C	)
#define	PINCNTL213	(	CTRL_MODULE_BASE_ADDR +	0x0B50	)
#define	PINCNTL214	(	CTRL_MODULE_BASE_ADDR +	0x0B54	)
#define	PINCNTL215	(	CTRL_MODULE_BASE_ADDR +	0x0B58	)
#define	PINCNTL216	(	CTRL_MODULE_BASE_ADDR +	0x0B5C	)
#define	PINCNTL217	(	CTRL_MODULE_BASE_ADDR +	0x0B60	)
#define	PINCNTL218	(	CTRL_MODULE_BASE_ADDR +	0x0B64	)
#define	PINCNTL219	(	CTRL_MODULE_BASE_ADDR +	0x0B68	)
#define	PINCNTL220	(	CTRL_MODULE_BASE_ADDR +	0x0B6C	)
#define	PINCNTL221	(	CTRL_MODULE_BASE_ADDR +	0x0B70	)
#define	PINCNTL222	(	CTRL_MODULE_BASE_ADDR +	0x0B74	)
#define	PINCNTL223	(	CTRL_MODULE_BASE_ADDR +	0x0B78	)
#define	PINCNTL224	(	CTRL_MODULE_BASE_ADDR +	0x0B7C	)
#define	PINCNTL225	(	CTRL_MODULE_BASE_ADDR +	0x0B80	)
#define	PINCNTL226	(	CTRL_MODULE_BASE_ADDR +	0x0B84	)
#define	PINCNTL227	(	CTRL_MODULE_BASE_ADDR +	0x0B88	)
#define	PINCNTL228	(	CTRL_MODULE_BASE_ADDR +	0x0B8C	)
#define	PINCNTL229	(	CTRL_MODULE_BASE_ADDR +	0x0B90	)
#define	PINCNTL230	(	CTRL_MODULE_BASE_ADDR +	0x0B94	)
#define	PINCNTL231	(	CTRL_MODULE_BASE_ADDR +	0x0B98	)
#define	PINCNTL232	(	CTRL_MODULE_BASE_ADDR +	0x0B9C	)
#define	PINCNTL233	(	CTRL_MODULE_BASE_ADDR +	0x0BA0	)
#define	PINCNTL234	(	CTRL_MODULE_BASE_ADDR +	0x0BA4	)
#define	PINCNTL235	(	CTRL_MODULE_BASE_ADDR +	0x0BA8	)
#define	PINCNTL236	(	CTRL_MODULE_BASE_ADDR +	0x0BAC	)
#define	PINCNTL237	(	CTRL_MODULE_BASE_ADDR +	0x0BB0	)
#define	PINCNTL238	(	CTRL_MODULE_BASE_ADDR +	0x0BB4	)
#define	PINCNTL239	(	CTRL_MODULE_BASE_ADDR +	0x0BB8	)
#define	PINCNTL240	(	CTRL_MODULE_BASE_ADDR +	0x0BBC	)
#define	PINCNTL241	(	CTRL_MODULE_BASE_ADDR +	0x0BC0	)
#define	PINCNTL242	(	CTRL_MODULE_BASE_ADDR +	0x0BC4	)
#define	PINCNTL243	(	CTRL_MODULE_BASE_ADDR +	0x0BC8	)
#define	PINCNTL244	(	CTRL_MODULE_BASE_ADDR +	0x0BCC	)
#define	PINCNTL245	(	CTRL_MODULE_BASE_ADDR +	0x0BD0	)
#define	PINCNTL246	(	CTRL_MODULE_BASE_ADDR +	0x0BD4	)
#define	PINCNTL247	(	CTRL_MODULE_BASE_ADDR +	0x0BD8	)
#define	PINCNTL248	(	CTRL_MODULE_BASE_ADDR +	0x0BDC	)
#define	PINCNTL249	(	CTRL_MODULE_BASE_ADDR +	0x0BE0	)
#define	PINCNTL250	(	CTRL_MODULE_BASE_ADDR +	0x0BE4	)
#define	PINCNTL251	(	CTRL_MODULE_BASE_ADDR +	0x0BE8	)
#define	PINCNTL252	(	CTRL_MODULE_BASE_ADDR +	0x0BEC	)
#define	PINCNTL253	(	CTRL_MODULE_BASE_ADDR +	0x0BF0	)
#define	PINCNTL254	(	CTRL_MODULE_BASE_ADDR +	0x0BF4	)
#define	PINCNTL255	(	CTRL_MODULE_BASE_ADDR +	0x0BF8	)
#define	PINCNTL256	(	CTRL_MODULE_BASE_ADDR +	0x0BFC	)
#define	PINCNTL257	(	CTRL_MODULE_BASE_ADDR +	0x0C00	)
#define	PINCNTL258	(	CTRL_MODULE_BASE_ADDR +	0x0C04	)
#define	PINCNTL259	(	CTRL_MODULE_BASE_ADDR +	0x0C08	)
#define	PINCNTL260	(	CTRL_MODULE_BASE_ADDR +	0x0C0C	)
#define	PINCNTL261	(	CTRL_MODULE_BASE_ADDR +	0x0C10	)
#define	PINCNTL262	(	CTRL_MODULE_BASE_ADDR +	0x0C14	)
#define	PINCNTL263	(	CTRL_MODULE_BASE_ADDR +	0x0C18	)
#define	PINCNTL264	(	CTRL_MODULE_BASE_ADDR +	0x0C1C	)
#define	PINCNTL265	(	CTRL_MODULE_BASE_ADDR +	0x0C20	)
#define	PINCNTL266	(	CTRL_MODULE_BASE_ADDR +	0x0C24	)
#define	PINCNTL267	(	CTRL_MODULE_BASE_ADDR +	0x0C28	)
#define	PINCNTL268	(	CTRL_MODULE_BASE_ADDR +	0x0C2C	)
#define	PINCNTL269	(	CTRL_MODULE_BASE_ADDR +	0x0C30	)
#define	PINCNTL270	(	CTRL_MODULE_BASE_ADDR +	0x0C34	)
#define	PINCNTL271	(	CTRL_MODULE_BASE_ADDR +	0x0C38	)


#define PLL_BASE_ADDRESS         0x481C5000 
#define CONTROL_BASE_ADDRESS     0x48140000
    
#define OSC_0			   		 20  
#define OSC_1		   			 20  
#define OSC_SRC_CTRL            (PLL_BASE_ADDRESS+0x02c0)
#define ARM_SRC_CLK             (PLL_BASE_ADDRESS+0x02c4)
   
// Top Level ADPLLJ 
#define L3_PLL_BASE             (PLL_BASE_ADDRESS+0x110)
#define IVA_PLL_BASE            (PLL_BASE_ADDRESS+0x0E0)
#define DSS_PLL_BASE            (PLL_BASE_ADDRESS+0x170)
#define SGX_PLL_BASE            (PLL_BASE_ADDRESS+0x0B0)
#define DSP_PLL_BASE            (PLL_BASE_ADDRESS+0x080)
#define ISS_PLL_BASE            (PLL_BASE_ADDRESS+0x140)
#define USB_PLL_BASE            (PLL_BASE_ADDRESS+0x260)
#define AUDIO_PLL_BASE          (PLL_BASE_ADDRESS+0x230)
#define VIDEO_0_PLL_BASE        (PLL_BASE_ADDRESS+0x1A0)
#define VIDEO_1_PLL_BASE        (PLL_BASE_ADDRESS+0x1D0)
#define HDMI_PLL_BASE           (PLL_BASE_ADDRESS+0x200)
#define DDR_PLL_BASE            (PLL_BASE_ADDRESS+0x290)
	
//ADPLL intrnal Offset Registers
#define CLKCTRL 				0x4
#define TENABLE 				0x8
#define TENABLEDIV 				0xC
#define M2NDIV  				0x10
#define MN2DIV 				    0x14
#define STATUS 				    0x24

// ADPLLJ_CLKCRTL_Register Value Configurations
// ADPLLJ_CLKCRTL_Register SPEC bug  bit 19,bit29 -- CLKLDOEN,CLKDCOEN
#define ADPLLJ_CLKCRTL_HS2       0x00000801 //HS2 Mode,TINTZ =1  --used by all PLL's except HDMI 
#define ADPLLJ_CLKCRTL_HS1       0x00001001 //HS1 Mode,TINTZ =1  --used only for HDMI 
#define ADPLLJ_CLKCRTL_CLKDCO    0x200a0000 // Enable CLKDCOEN,CLKLDOEN,CLKDCOPWDNZ -- used for HDMI,USB

/*********** MODENA ADPLLS REGISTERS  *********/
#define MODENAPLL_CLKCTRL		(PLL_BASE_ADDRESS+0x04c) 
#define MODENAPLL_TENABLE		(PLL_BASE_ADDRESS+0x050) 
#define MODENAPLL_TENABLEDIV    (PLL_BASE_ADDRESS+0x054)	
#define MODENAPLL_M2NDIV    	(PLL_BASE_ADDRESS+0x058) 
#define MODENAPLL_MN2DIV    	(PLL_BASE_ADDRESS+0x05c) 
#define MODENAPLL_STATUS		(PLL_BASE_ADDRESS+0x06c) 

/********   SATA PLL REGISTERS   **************/
#define SATA_PLLCFG0            (CONTROL_BASE_ADDRESS+0x720) 
#define SATA_PLLCFG1            (CONTROL_BASE_ADDRESS+0x724) 
#define SATA_PLLCFG2            (CONTROL_BASE_ADDRESS+0x728) 
#define SATA_PLLCFG3            (CONTROL_BASE_ADDRESS+0x72c) 
#define SATA_PLLCFG4            (CONTROL_BASE_ADDRESS+0x730) 
#define SATA_PLLSTATUS          (CONTROL_BASE_ADDRESS+0x734)
#define SATA_RXSTATUS           (CONTROL_BASE_ADDRESS+0x738)
#define SATA_TXSTATUS           (CONTROL_BASE_ADDRESS+0x73c)

#define TI81XX_SATA_BASE    0x4A140000
#define TI814X_SATA_PHY_CFGRX0_OFFSET       (0x1104)
#define TI814X_SATA_PHY_CFGRX1_OFFSET       (0x1108)
#define TI814X_SATA_PHY_CFGRX2_OFFSET       (0x110C)
#define TI814X_SATA_PHY_CFGRX3_OFFSET       (0x1110)
#define TI814X_SATA_PHY_CFGTX0_OFFSET       (0x111C)
#define TI814X_SATA_PHY_CFGTX1_OFFSET       (0x1120)
#define TI814X_SATA_PHY_CFGTX2_OFFSET       (0x1128)

#define CM_ALWON2_SATA_CLKCTRL				(PRCM_BASE_ADDR + 0x0560)
#define CM_ALWON2_L3_MED_CLKSTCTRL				(PRCM_BASE_ADDR + 0x504)

#define PHY_CFGRX0_VAL      0x00C7CC22
#define PHY_CFGRX1_VAL      0x008E0500
#define PHY_CFGRX2_VAL      0x7BDEF000
#define PHY_CFGRX3_VAL      0x1F180B0F
#define PHY_CFGTX0_VAL      0x01001622
#define PHY_CFGTX1_VAL      0x40000002
#define PHY_CFGTX2_VAL      0x073CE39E

/********   PCIE PLL REGISTERS   **************/
#define PCIE_PLLCFG0            (CONTROL_BASE_ADDRESS+0x6D8) 
#define PCIE_PLLCFG1            (CONTROL_BASE_ADDRESS+0x6DC) 
#define PCIE_PLLCFG2            (CONTROL_BASE_ADDRESS+0x6E0) 
#define PCIE_PLLCFG3            (CONTROL_BASE_ADDRESS+0x6E4) 
#define PCIE_PLLCFG4            (CONTROL_BASE_ADDRESS+0x6E8) 
#define PCIE_PLLSTATUS          (CONTROL_BASE_ADDRESS+0x6EC)
#define PCIE_RXSTATUS           (CONTROL_BASE_ADDRESS+0x6F0)
#define PCIE_TXSTATUS           (CONTROL_BASE_ADDRESS+0x6F4)
#define SERDES_REFCLK_CTL 	    (CONTROL_BASE_ADDRESS+0xE24)



#define WR_MEM_32(addr, data)    *(unsigned int*)(addr) =(unsigned int)(data)
#define RD_MEM_32(addr) 	  	 *(unsigned int*)(addr)
#define UWORD32 			     unsigned int
   
/*******************************************************************************************************                               
****                               
****                                   ********* RANGE ************             
****   REF_CLK       = (OSC_FREQ)/N+1  [  REF_CLK < 2.5MHz      ] 
****   DCOCLK_HS2    = (REF_CLK)*M     [500  < DCOCLK < 1000MHz ] 
****   DCOCLK_HS1    = (REF_CLK)*M     [1000 < DCOCLK < 2000MHz ]--used for HDMI CLKDCO    
****   CLKOUT        =  DCOCLK/M2      [10   < CLKOUT < 2000MHz ]
****   N+1 			           		   [1..256]
****   M    		           		   [2..4095]
****   M2    		           		   [1..127]
****
****
******************************************************************************************************
****  Function used for configuring all ADPLLJ except Modena
****  PLL_Clocks_Config(UWORD32 Base_Address,UWORD32 OSC_FREQ,UWORD32 N,UWORD32 M,UWORD32 M2,UWORD32 CLKCTRL_VAL)
	  1. Pass the Base Address of the ADPLL to be configured.
	  2. Pass the Clock i/p to the ADPLL as per the "defines" for ADPLL L3,video-0,video-1,audio,hdmi.
			OSC_0       -- Onchip  20MHz
			OSC_1       -- Offchip 20MHz
			For all other pll's sgx,dsp,iva,dss,gem,usb,ddr clock i/p is fixed to OSC_0	
	  3. Configure N,M,M2 to get the desired clock o/p from ADPLLJ.
	  4. Use the value CLKCTRL_VAL configured in the GEL file as per the defines mentioned above.
***********************************************************************************************
**** CONFIGURED  ALL THE CLOCKS FOR ADPLL CLKi/p to 20MHz.
***** ADPLL     CLKOUT    CLKDC0OUT    CLKLDO
**** MODENA 	600
**** L3 		220/200                         -Need to be confirmed 
***  DSS    	200  
***  DSP   	 	500  
***  SGX    	200  
***  IVA    	266  
***  ISS    	400  
***  USB    	960       960            960
***  VIDEO_0    54  
***  VIDEO_1   	148.5 
***  AUDIO    	200   
***  DDR   		400/333                        -Need to be confirmed
***  HDMI       148.5     1485         148.5  
******************************************************************************************************/

/******* CONFIGURE THE BELOW CLK I/P SOURCES  to OSC_0/OSC_1 FOR THE ADPLLJS ******/
#define L3_OSC_SRC   		OSC_0            
#define VIDE0_0_OSC_SRC   	OSC_0            
#define VIDE0_1_OSC_SRC   	OSC_0            
#define HDMI_OSC_SRC   		OSC_0            
#define AUDIO_OSC_SRC   		OSC_0       

//pass the below defines to L3_PLL_Config for configuring M value as per the L3 Clock Requirements
#define MVAL_L3_220     880  
#define MVAL_L3_200     800  //audi_hd requirement

//pass the below defines to DDR_PLL_Config  for configuring M value as per the DDR Clock Requirements
#define MVAL_DDR_400     800  
#define MVAL_DDR_333     666  //audi_hd requirement

   
#define CLKOUT2EN    1
#define CLKOUT2DIV  0
#define CLKOUT2SRC  0 

// CLKOUT2DIV THis  field controls the external clock divison factor
//          0x0:      SYS_CLKOLUT2/1 
//          0x1:      SYS_CLKOUT2/2 
//          0x2:      SYS_CLKOUT2/4 
//          0x3:      SYS_CLKOUT2/8 
//          0x4:      SYS_CLKOUT2/16 

// CLKOUT2SOURCE     This field selects the external output clock source
//          0x0:      Source clock is MAIN_PLL_CLK5 
//          0x1:      Source clock is DDR_PLL_CLK1 
//          0x2:      Source clock is VIDEO_PLL_CLK1 
//          0x3:      Source clock is AUDIO_PLL_CLK1 

#define CONTROL_STATUS              (CTRL_MODULE_BASE_ADDR + 0x040)
#define BANDGAP0_TRIM       (CTRL_MODULE_BASE_ADDR + 0x44C)
#define BANDGAP1_TRIM       (CTRL_MODULE_BASE_ADDR + 0x454)
#define PLL_SUBSYSTEM_BASE_ADDR       PLL_BASE_ADDRESS
#define DSPPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x084)
#define SGXPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x0B4)
#define IVAPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x0E4)
#define L3PLL_CLOCK_CONTROL        (PLL_SUBSYSTEM_BASE_ADDR + 0x114)
#define ISSPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x144)
#define DSSPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x174)
#define VID0PLL_CLOCK_CONTROL      (PLL_SUBSYSTEM_BASE_ADDR + 0x1A4)
#define VID1PLL_CLOCK_CONTROL      (PLL_SUBSYSTEM_BASE_ADDR + 0x1D4)
#define HDMIPLL_CLOCK_CONTROL      (PLL_SUBSYSTEM_BASE_ADDR + 0x204)
#define AUDIOPLL_CLOCK_CONTROL     (PLL_SUBSYSTEM_BASE_ADDR + 0x234)
#define USBPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x264)
#define DDRPLL_CLOCK_CONTROL       (PLL_SUBSYSTEM_BASE_ADDR + 0x294)
#define MODENAPLL_CLOCK_CONTROL     (PLL_SUBSYSTEM_BASE_ADDR + 0x04C)


#define control_pllss_mmr_lock                     0x481C5040
#define control_mmr_lock0                          0x48140060
#define control_mmr_lock1                          0x48140064
#define control_mmr_lock2                          0x48140068
#define control_mmr_lock3                          0x4814006c
#define control_mmr_lock4                          0x48140070

#define control_pllss_mmr_lock_unlock_val          0x1EDA4C3D
#define control_mmr_lock0_unlock_val               0x2FF1AC2B
#define control_mmr_lock1_unlock_val               0xF757FDC0
#define control_mmr_lock2_unlock_val               0xE2BC3A6D
#define control_mmr_lock3_unlock_val               0x1EBF131D
#define control_mmr_lock4_unlock_val               0x6F361E05

#define NETRA_TEST_DEVICE_FW_VAL 0xFFFFFFFF
/*Netra Fire Wall Registers*/
#define VLYNQ_FW			0x47C06088  
#define EMIF_FW 			0x47C0C088  
#define GPMC_FW 			0x47C0E088  
#define OCMC_RAM0_FW 		0x47C10088  
#define OCMC_RAM1_FW 		0x47C12088  
#define SGX530_FW			0x47C14088  
#define GEM_SDMA_FW 		0x47C16088  
#define DUCATI_FW 			0x47C18088	
#define PCIE_FW				0x47C1A088	
#define TPPSS_FW			0x47C1C088	
#define IVAHD_SL2_FW 		0x47C1E088	
#define IVAHD_CFG_FW 		0x47C20088	
#define MCASP_FW 			0x47C28088	
/* #define SecuritySS_FW 		0x47C2A088	 */
#define HDMI_FW 			0x47C2C088	
#define MCBSP_FW			0x47C2E088	
#define TPTC_FW 			0x47C30088	
#define TPCC_FW 			0x47C38088	
#define USB_FW 				0x47C3A088  


WRITE_MEM()
{
	WR_MEM_32(DUCATI_BASE_ADDR,   	  0x10000);
}



menuitem "DM814X System Initialization"
hotmenu DM814X_System_Initialisation_TEST_device()
{
	ControlModule_ClkEnable();
	Unlock_PLL_Control_MMR();
	OpenFireWall();
	PLL_CLOCKS_Config();
	PrcmAlwayOnClkEnable();
	DucatiClkEnable();
	IVAHD0ClkEnable();
	DDR2_Initialization();
}
hotmenu DM814X_System_Initialisation_GP_device()
{
	//ControlModule_ClkEnable();
	Unlock_PLL_Control_MMR();
	//OpenFireWall();
	PLL_CLOCKS_Config();
	PrcmAlwayOnClkEnable();
	DucatiClkEnable();
	IVAHD0ClkEnable();
	DDR2_Initialization();
}

hotmenu PLL_CLOCKS_Config()
{
    GEL_TextOut("\tDM814X ALL ADPLL INIT IS IN PROGRESS,Please wait ..... \n","Output",1,1,1);	 
	MODENA_PLL_Config();
	DSS_PLL_Config();
	DSP_PLL_Config();
	SGX_PLL_Config();
	IVA_PLL_Config();
	ISS_PLL_Config();
    USB_PLL_Config();
	DDR_PLL_Config();
	AUDIO_PLL_Config();
	HDMI_PLL_Config();
	VIDEO_0_PLL_Config();
	VIDEO_1_PLL_Config();
	//PCIE_PLL_Config();
    SATA_PLL_Config();
	GEL_TextOut("\t ****  DM814X ALL ADPLL INIT IS COMPLETE  ******* \n","Output",1,1,1);	 
    WR_MEM_32(0x48100100, 0x01031FFF);
    WR_MEM_32(0x48100114, 0xC010E);
    WR_MEM_32(0x48100118, 0xF);    
}

//modena 600Mhz
hotmenu MODENA_PLL_Config()
{
    UWORD32 rval_ctrl,M,N,clk_out;
    GEL_TextOut("\tDM814X MODENA_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
	N = 0x1;
	M = 0x3c;
	clk_out     = (OSC_0/(N+1))*M;
	GEL_TextOut("\t ADPLLS CLKOUT value is  = %d \n",,,,,clk_out);
    WR_MEM_32(MODENAPLL_M2NDIV      ,N);         
    WR_MEM_32(MODENAPLL_MN2DIV      ,M);        
	WR_MEM_32(MODENAPLL_TENABLEDIV  ,0x1);  
    WR_MEM_32(MODENAPLL_TENABLEDIV  ,0x0);
    WR_MEM_32(MODENAPLL_TENABLE     ,0x1);
    WR_MEM_32(MODENAPLL_TENABLE     ,0x0);
    rval_ctrl = RD_MEM_32(MODENAPLL_CLKCTRL);
    WR_MEM_32(MODENAPLL_CLKCTRL,(rval_ctrl & 0xff7fffff) | 0x1);
    while (( (RD_MEM_32(MODENAPLL_STATUS)) & 0x00000600) != 0x00000600);
    GEL_TextOut("\tDM814X MODENA_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X MODENA_PLL is initialized to 600Mhz \n","Output",1,1,1);
	
}

//l3 clock 200MHz
hotmenu L3_PLL_Config()
{
	UWORD32 OSC_SOURCE = L3_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0)
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffffffe)|0x0);
	}
	else
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffffffe)|0x1);
	}
	
    GEL_TextOut("\tDM814X L3_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	
	PLL_Clocks_Config(L3_PLL_BASE,OSC_SOURCE,19,MVAL_L3_200,4,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X L3_PLL Init is Done \n","Output",1,1,1);
	GEL_TextOut("\tDM814X L3_PLL is initialized to 200MHz \n","Output",1,1,1);
}


//dss clock 200MHz
hotmenu DSS_PLL_Config()
{
    GEL_TextOut("\tDM814X DSS_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(DSS_PLL_BASE,OSC_0,19,800,4,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X DSS_PLL Init is Done \n","Output",1,1,1);
	GEL_TextOut("\tDM814X DSS_PLL is initialized to 200MHz \n","Output",1,1,1);
}

//dsp clock 500MHz 
hotmenu DSP_PLL_Config()
{
    GEL_TextOut("\tDM814X DSP_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(DSP_PLL_BASE,OSC_0,19,500,1,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X DSP_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X DSP_PLL is initialized to 500MHz \n","Output",1,1,1);
}

//SGX's PLL (200 MHz)
hotmenu SGX_PLL_Config()
{
    GEL_TextOut("\tDM814X SGX_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(SGX_PLL_BASE,OSC_0,19,800,4,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X SGX_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X SGX_PLL is initialized to 200MHz \n","Output",1,1,1);
}


//IVA's PLL (266 MHz)
hotmenu IVA_PLL_Config()
{
    GEL_TextOut("\tDM814X IVA_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(IVA_PLL_BASE,OSC_0,19,532,2,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X IVA_PLL Init is Done \n","Output",1,1,1);
	GEL_TextOut("\tDM814X IVA_PLL is initialized to 266MHz \n","Output",1,1,1);	
}


//ISS's PLL (400 MHz)
hotmenu ISS_PLL_Config()
{
    GEL_TextOut("\tDM814X ISS_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(ISS_PLL_BASE,OSC_0,19,800,2,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X ISS_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X ISS_PLL is initialized to 400MHz \n","Output",1,1,1);
}

#define CM_ALWON2_USB_CLKCTRL			(PRCM_BASE_ADDR + 0x0558)
#define RM_ALWON2_RSTCTRL				(PRCM_BASE_ADDR + 0x0B10)
#define RM_ALWON2_RSTST 				(PRCM_BASE_ADDR + 0x0B14)
#define CM_ALWON2_L3_SLOW_CLKSTCTRL		(PRCM_BASE_ADDR + 0x0514)

// USB's PLL (960 MHz) 
hotmenu USB_PLL_Config()
{
    GEL_TextOut("\tDM814X USB_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(USB_PLL_BASE,OSC_0,19,960,1,ADPLLJ_CLKCRTL_HS2+ADPLLJ_CLKCRTL_CLKDCO);

    WR_MEM_32(CM_ALWON2_USB_CLKCTRL,    0x2); /*Enable USB Clock*/
	while((RD_MEM_32(CM_ALWON2_USB_CLKCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
	
	WR_MEM_32(CM_ALWON2_L3_SLOW_CLKSTCTRL,    0x2); /*Enable USB Clock*/
	while((RD_MEM_32(CM_ALWON2_L3_SLOW_CLKSTCTRL) & 0x103) != 0x102);		/*Poll for Module is functional*/

	/* USB_PINMUX_Config */ 
	WR_MEM_32(PINCNTL258, 0x00010001);
	WR_MEM_32(PINCNTL270, 0x00060001);
	WR_MEM_32(PINCNTL14, 0x00060080);

	
	WR_MEM_32(RM_ALWON2_RSTCTRL, 0x9F); /* Disable local reset */
	while((RD_MEM_32(RM_ALWON2_RSTST) & 0x60) != 0x60);		/*Poll for Module is functional*/
	WR_MEM_32(RM_ALWON2_RSTST, 0x60); /* Write 1 to Clear */
	
	WR_MEM_32(0x48140620, 0x3C1E64F4); /* PHY INIT */
	WR_MEM_32(0x48140628, 0x3C1E64F4); /* PHY INIT */
	
    GEL_TextOut("\tDM814X USB_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X USB_PLL is initialized to 200MHz \n","Output",1,1,1);
}

hotmenu USB_PINMUX_Config()
{
	WR_MEM_32(PINCNTL258, 0x00010001); 
}

//VIDEO0's PLL (54 MHz)
hotmenu VIDEO_0_PLL_Config()
{
	UWORD32 OSC_SOURCE = VIDE0_0_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0)
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffeffff)|0x0);
	}
	else
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffeffff)|0x10000);
	}

    GEL_TextOut("\tDM814X VIDEO_0_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(VIDEO_0_PLL_BASE,OSC_SOURCE,19,540,10,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X VIDEO_0_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X VIDEO0_PLL is initialized to 54MHz \n","Output",1,1,1);
}


//VIDEO 1's PLL (148.5 MHz)
hotmenu VIDEO_1_PLL_Config()
{
	UWORD32 OSC_SOURCE = VIDE0_1_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0)
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xffffffff)|0x0);
	}
	else
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffdffff)|0x20000);
	}

    GEL_TextOut("\tDM814X VIDEO_1_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);
    PLL_Clocks_Config(VIDEO_1_PLL_BASE,OSC_SOURCE,19,594,8,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X VIDEO_1_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X VIDEO1_PLL is initialized to 148.5MHz \n","Output",1,1,1);
}

//AUDIO's PLL (200 MHz)
hotmenu AUDIO_PLL_Config()
{
	UWORD32 OSC_SOURCE = AUDIO_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0)
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfeffffff)|0x0);
	}
	else
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfeffffff)|0x01000000);
	}

    GEL_TextOut("\tDM814X AUDIO_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(AUDIO_PLL_BASE,OSC_SOURCE,19,800,4,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X AUDIO_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X AUDIO_PLL is initialized to 200MHz \n","Output",1,1,1);
}


// DDR's PLL (333 MHz)
hotmenu DDR_PLL_Config()
{
    GEL_TextOut("\tDM814X DDR_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(DDR_PLL_BASE,OSC_0,19,MVAL_DDR_400,2,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X DDR_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X DDR_PLL is initialized to 666MHz \n","Output",1,1,1);
}


//DV01-148.5 HDMI-HFBITCLK 1.485GHz   
hotmenu HDMI_PLL_Config()   
{
	UWORD32 OSC_SOURCE = HDMI_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0)
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffbffff)|0x0);
	}
	else
	{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffbffff)|0x40000);
	}

    GEL_TextOut("\tDM814X HDMI_PLL Init is in Progress, Please wait ..... \n","Output",1,1,1);	 
    PLL_Clocks_Config(HDMI_PLL_BASE,OSC_SOURCE,19,1485,10,ADPLLJ_CLKCRTL_HS1+ADPLLJ_CLKCRTL_CLKDCO);
    GEL_TextOut("\tDM814X HDMI_PLL Init is Done \n","Output",1,1,1);
}

hotmenu SATA_PHY_SEQUENCE_20Mhz()
{
    /* Configuring PHY registers for SATA */
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGRX0_OFFSET, PHY_CFGRX0_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGRX1_OFFSET, PHY_CFGRX1_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGRX2_OFFSET, PHY_CFGRX2_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGRX3_OFFSET, PHY_CFGRX3_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGTX0_OFFSET, PHY_CFGTX0_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGTX1_OFFSET, PHY_CFGTX1_VAL);
    WR_MEM_32(TI81XX_SATA_BASE + TI814X_SATA_PHY_CFGTX2_OFFSET, PHY_CFGTX2_VAL);

  GEL_TextOut("\SATA PHY Initialised..... \n","Output",1,1,1);	
}

//PLL program sequence to get 125Mhz ethernet clockout.   
hotmenu SATA_PLL_Config()
{
	WR_MEM_32(SATA_PLLCFG1, 0xC12C003C);	//cfgpll1
	wait_delay(2000);
	WR_MEM_32(SATA_PLLCFG3, 0x004008E0);	//cfgpll3
	wait_delay(2000);
	//wait for bias to be stable --50us
	WR_MEM_32(SATA_PLLCFG0, 0x80000004);	//cfgpll0
	wait_delay(2000);
	WR_MEM_32(SATA_PLLCFG0, 0x80000014);	//cfgpll0
	wait_delay(2000);
	WR_MEM_32(SATA_PLLCFG0, 0x80000016);	//cfgpll0
	wait_delay(2000);
	WR_MEM_32(SATA_PLLCFG0, 0xc0000017);	//cfgpll0
	wait_delay(2000);
	
	//poll the status field to check if pll lock occured.
	while( ((*(unsigned int *)0x48140734) & 0x1) != 0x1)
	{
	}
	WR_MEM_32(CM_ALWON2_SATA_CLKCTRL,    0x2); /*Enable SATA Clock*/
	while((RD_MEM_32(CM_ALWON2_SATA_CLKCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
	
	WR_MEM_32(CM_ALWON2_L3_MED_CLKSTCTRL,    0x2); /*Enable SATA Clock*/
	while((RD_MEM_32(CM_ALWON2_L3_MED_CLKSTCTRL) & 0x103) != 0x102);		/*Poll for Module is functional*/
	
	GEL_TextOut("\t --- SATA PLL Locked\n","Output",1,1,1);
}


//pci express pll sequence
hotmenu PCIE_PLL_Config()
{
	GEL_TextOut("\t --- \n","Output",1,1,1);	 
    WR_MEM_32(SERDES_REFCLK_CTL,0x00000002); //PowerDown
	GEL_TextOut("\t * \n","Output",1,1,1);	 
    WR_MEM_32(PCIE_PLLCFG0,0x00000000); //cfgpll0
	GEL_TextOut("\t ** \n","Output",1,1,1);	 
    WR_MEM_32(PCIE_PLLCFG1,0x00640000); //cfgpll1
	GEL_TextOut("\t *** \n","Output",1,1,1);	 
    WR_MEM_32(PCIE_PLLCFG2,0x00000000); //cfgpll2
    GEL_TextOut("\t **** \n","Output",1,1,1);	 
	WR_MEM_32(PCIE_PLLCFG3,0x004008E0); //cfgpll3
    GEL_TextOut("\t ***** \n","Output",1,1,1);	 
	WR_MEM_32(PCIE_PLLCFG4,0x0000609C); //cfgpll4
    GEL_TextOut("\t ****** \n","Output",1,1,1);	 
	WR_MEM_32(0x48141318,0x00000E7B); //pcie_serdes_cfg_misc
    wait_delay(3); // Wait 100 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000004); //Config PLL CFG0 bit [2] - ENBGSC_REF
    wait_delay(3); // Wait 250 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000014); //Config PLL CFG0 bit [4] - DIGLDO
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000016); //Config PLL CFG0 bit [1] - ENPLLLDO
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x30000016); // Configure proxy TXLDO and RXLDO enables (DM814X ECO 3/30/10)
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x70007016); // Configure multiplier
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x70007017);  // Enable PLL
	wait_delay(3); // Wait 200 ns
     //poll the status field to check if pll lock occured.  
    while (RD_MEM_32(PCIE_PLLSTATUS) != 0x1);
	
	GEL_TextOut("\t --- PCIe SERDES PLL Locked\n","Output",1,1,1);	 
}

wait_delay(UWORD32 noopcount)
 {
 int i;
  for(i=0;i<noopcount;i++)
  {
  }
 }

PLL_Clocks_Config(UWORD32 Base_Address,UWORD32 OSC_FREQ,UWORD32 N,UWORD32 M,UWORD32 M2,UWORD32 CLKCTRL_VAL)
{
    UWORD32 m2nval,mn2val,read_clkctrl,clk_out,ref_clk,clkout_dco = 0;
    m2nval = (M2<<16) | N;
    mn2val =  M;
	/*ref_clk     = OSC_FREQ/(N+1);
    clkout_dco  = ref_clk*M;
    clk_out     = clkout_dco/M2;
    
	GEL_TextOut("\t ADPLLJ CLKIP   value is  = %d \n",,,,,OSC_FREQ);
	GEL_TextOut("\t ADPLLJ CLKOUT  value is  = %d \n",,,,,clk_out);
	*/
	WR_MEM_32((Base_Address+M2NDIV    ),m2nval);
	WR_MEM_32((Base_Address+MN2DIV    ),mn2val);  
	WR_MEM_32((Base_Address+TENABLEDIV),0x1);
	WR_MEM_32((Base_Address+TENABLEDIV),0x0);
	WR_MEM_32((Base_Address+TENABLE   ),0x1);
	WR_MEM_32((Base_Address+TENABLE   ),0x0);
	read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
	//configure the TINITZ(bit0) and CLKDCO BITS IF REQUIRED  
	WR_MEM_32(Base_Address+CLKCTRL,(read_clkctrl & 0xff7fe3ff) | CLKCTRL_VAL);
	read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
	// poll for the freq,phase lock to occur
	while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000600) != 0x00000600);
	//wait fot the clocks to get stabized
	wait_delay(10); 
}
  


hotmenu Clockout_Enable()
{
	*(unsigned int *)0x481402e4 =0 ;             // clkout0,1 selection
	*(unsigned int *)0x481409f8 |=0x10 ;   // clkout1
	*(unsigned int *)0x48140c08 |=0x4 ;     //clkout0
	*(unsigned int *)0x48180100 = ( (CLKOUT2EN << 7) | (CLKOUT2DIV << 3) | (CLKOUT2SRC << 0) ); 
}



hotmenu ControlModule_ClkEnable()
{

	GEL_TextOut("\tPRCM for Control Module in Progress \n","Output",1,1,1);	 									
	/*Enable the  Clocks*/
	WR_MEM_32(CM_CTRL_CLKCTRL,   2);
	//while(((RD_MEM_32(CM_CTRL_CLKCTRL)&0x30000))!=0x30000);	
	while(RD_MEM_32(CM_CTRL_CLKCTRL)!=0x2);
    GEL_TextOut("\tPRCM for Control Module Done \n","Output",1,1,1);	 									
}

hotmenu PrcmAlwayOnClkEnable()
{
	unsigned int fail=0, k=0;
	GEL_TextOut("\tPRCM for OCMCRAM0/1 Initialization in Progress \n","Output",1,1,1);	 									
	/*Enable the OCMC0RAM Clocks*/
	WR_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL, 2);
	WR_MEM_32(CM_ALWON_OCMC_0_CLKCTRL,   2);
	while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL) & 0x100)>>8)!=1);
	while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKCTRL)&0x30000))!=0x30000);

	for(k=0; k<SIZE; k++) 
	{
		WR_MEM_32(OCMC0RAM_BASE_ADDR+4*k, 0x12345678+k);
	}

    for(k=0;  k<SIZE; k++) 
	{
		if(RD_MEM_32(OCMC0RAM_BASE_ADDR+4*k) != (0x12345678+k) ) 
			{
			fail++;
			}
	  }

    if(fail!=0) 
	{
	   GEL_TextOut("\tOCMCRAM0 Accesses FAILED \n","Output",1,1,1);	 										
	}

	GEL_TextOut("\tOCMCRAM0 Accesses PASSED \n","Output",1,1,1);	 										

    GEL_TextOut("\tPRCM for OCMCRAM0 Initialization Done \n","Output",1,1,1);	 									
}


hotmenu DucatiClkEnable() 
{
	int i;
	GEL_TextOut("\tPRCM for DucatiSS is in Progress  \n","Output",1,1,1);	 									
    	//while(RD_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL)!=0x1);
	 GEL_TextOut("\tPRCM for DucatiSS is in Progress  \n","Output",1,1,1);	 									
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)CM_DEFAULT_DUCATI_CLKSTCTRL);

	WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xEF); /*Enable the Ducati Logic*/

	WR_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL, 2); /*Enable Power Domain Transition*/
	WR_MEM_32(CM_DEFAULT_DUCATI_CLKCTRL,   2); /*Enable Ducati Clocks*/


	/*Check CLKIN200TR & CLKINTR  are active*/
	while(((RD_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL)&0x300)>>8)!=3) ;
    GEL_TextOut("\tClock is Active  \n","Output",1,1,1);	 									

    //----------------------WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xEF); /*Enable the Ducati Logic*/
    //--WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE3); /*Enable the Ducati Logic*/
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)RM_DEFAULT_RSTCTRL);
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)RM_DEFAULT_RSTST);
//	for(i=0;i<100;i++);
//    GEL_TextOut("\tDelay gone  \n","Output",1,1,1);
	/*Write Ducate IRAM Boot Image */
	WR_MEM_32(DUCATI_BASE_ADDR,   	  0x10000);
	WR_MEM_32(DUCATI_BASE_ADDR+0x4,   0x9);
	WR_MEM_32(DUCATI_BASE_ADDR+0x8,   0xE7FEE7FE);
	
	
  //  GEL_TextOut("\tAfter RAM written  \n","Output",1,1,1);	 									

    /*Large Page Translations */
/*    GEL_TextOut("\tAfter RAM written  \n","Output",1,1,1);
	WR_MEM_32(DUCATI_MMU_CFG+0x800,   	  0x60000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x804,   	  0x80000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x808,   	  0x40000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x80C,   	  0xC0000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x820,   	  0x60000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x824,   	  0x80000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x828,   	  0x40000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x82C,   	  0xC0000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x840,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x844,   	  0x00020007);
	WR_MEM_32(DUCATI_MMU_CFG+0x848,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x84C,   	  0xC0020007);

	

	WR_MEM_32(DUCATI_MMU_CFG+0x860,   	  0x00300000);
	WR_MEM_32(DUCATI_MMU_CFG+0x864,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x868,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x86C,   	  0x00000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x8A0,   	  0x40300000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8A4,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8A8,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8AC,   	  0x00000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x8E0,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x8E4,   	  0x00020007);
	WR_MEM_32(DUCATI_MMU_CFG+0x8E8,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8EC,   	  0xC0000000);

	

	WR_MEM_32(DUCATI_MMU_CFG+0x920,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x924,   	  0x40000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x928,   	  0x00004000);
	WR_MEM_32(DUCATI_MMU_CFG+0x92C,   	  0x00008000);
	WR_MEM_32(DUCATI_MMU_CFG+0x930,   	  0x0000C000);

	WR_MEM_32(DUCATI_MMU_CFG+0x9A0,   	  0x55020000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9A4,   	  0x55080000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9A8,   	  0x55024000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9AC,   	  0x55028000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9B0,   	  0x5502C000);

	WR_MEM_32(DUCATI_MMU_CFG+0xA20,   	  0x0001000B);
	WR_MEM_32(DUCATI_MMU_CFG+0xA24,   	  0x0000000B);
	WR_MEM_32(DUCATI_MMU_CFG+0xA28,   	  0x00010007);
	WR_MEM_32(DUCATI_MMU_CFG+0xA2C,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0xA30,   	  0x00000007);
   GEL_TextOut("\tMMU has been written  \n","Output",1,1,1);	 									
*/

WR_MEM_32(DUCATI_MMU_CFG+0x800,   	  0x40000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x804,   	  0x80000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x808,   	  0xA0000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x80C,   	  0x60000000);

  WR_MEM_32(DUCATI_MMU_CFG+0x820,   	  0x40000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x824,   	  0x80000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x828,   	  0xA0000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x82C,   	  0x60000000);

  WR_MEM_32(DUCATI_MMU_CFG+0x840,   	  0x00000007);
  WR_MEM_32(DUCATI_MMU_CFG+0x844,   	  0x000B0007);
  WR_MEM_32(DUCATI_MMU_CFG+0x848,   	  0x00020007);
  WR_MEM_32(DUCATI_MMU_CFG+0x84C,   	  0x00020007);

  /*Medium Page*/
  WR_MEM_32(DUCATI_MMU_CFG+0x860,   	  0x00300000);
  WR_MEM_32(DUCATI_MMU_CFG+0x864,   	  0x00400000);
  /*WR_MEM_32(DUCATI_MMU_CFG+0x868,   	  0x00000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x86C,   	  0x00000000);*/

  WR_MEM_32(DUCATI_MMU_CFG+0x8A0,   	  0x40300000);
  WR_MEM_32(DUCATI_MMU_CFG+0x8A4,   	  0x40400000);
  /*WR_MEM_32(DUCATI_MMU_CFG+0x8A8,   	  0x00000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x8AC,   	  0x00000000);*/

  WR_MEM_32(DUCATI_MMU_CFG+0x8E0,   	  0x00000007);
  WR_MEM_32(DUCATI_MMU_CFG+0x8E4,   	  0x00020007);
  /*WR_MEM_32(DUCATI_MMU_CFG+0x8E8,   	  0x00000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x8EC,   	  0xC0000000);*/

  /*Small Page*/
  WR_MEM_32(DUCATI_MMU_CFG+0x920,   	  0x00000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x924,   	  0x40000000);
  WR_MEM_32(DUCATI_MMU_CFG+0x928,   	  0x00004000);
  WR_MEM_32(DUCATI_MMU_CFG+0x92C,   	  0x00008000);
  WR_MEM_32(DUCATI_MMU_CFG+0x930,   	  0x0000C000);

  WR_MEM_32(DUCATI_MMU_CFG+0x9A0,   	  0x55020000);
  WR_MEM_32(DUCATI_MMU_CFG+0x9A4,   	  0x55080000);
  WR_MEM_32(DUCATI_MMU_CFG+0x9A8,   	  0x55024000);
  WR_MEM_32(DUCATI_MMU_CFG+0x9AC,   	  0x55028000);
  WR_MEM_32(DUCATI_MMU_CFG+0x9B0,   	  0x5502C000);

  WR_MEM_32(DUCATI_MMU_CFG+0xA20,   	  0x0001000B);
  WR_MEM_32(DUCATI_MMU_CFG+0xA24,   	  0x0000000B);
  WR_MEM_32(DUCATI_MMU_CFG+0xA28,   	  0x00010007);
  WR_MEM_32(DUCATI_MMU_CFG+0xA2C,   	  0x00000007);
  WR_MEM_32(DUCATI_MMU_CFG+0xA30,   	  0x00000007);
	GEL_TextOut("\tMMU has been written by DSSTeam \n","Output",1,1,1);

    /*if((RD_MEM_32(CM_DEFAULT_TPPSS_CLKSTCTRL) & 0x7F00) ==0x7F00 ) {
      WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE0);
      GEL_TextOut("\tTPPSS is Already out of Reset, Bring Ducati out of Reset  \n","Output",1,1,1);	 									
	  }
	else */

    WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE3); //0xE3

	/*Check for Ducati M3_0 & M3_1 out of Reset*/
	while(((RD_MEM_32(RM_DEFAULT_RSTST)&0x1C))!=0x1C) ;
 //     GEL_TextOut("\tDucati is out of Reset\n","Output",1,1,1);	 									

	/*Check Module is in Functional Mode */
	while(((RD_MEM_32(CM_DEFAULT_DUCATI_CLKCTRL)&0x30000)>>16)!=0) ;

    GEL_TextOut("\tPRCM for DucatiSS is Done Successfully  \n","Output",1,1,1);	 									
}

	
hotmenu Depleeted_DucatiClkEnable() 
{
	int i;
	
	GEL_TextOut("\tPRCM for DucatiSS is in Progress  \n","Output",1,1,1);	 									
    
	//while(RD_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL)!=0x1);
	GEL_TextOut("\tPRCM for DucatiSS is in Progress  \n","Output",1,1,1);	 									
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)CM_DEFAULT_DUCATI_CLKSTCTRL);

	WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xEF); /*Enable the Ducati Logic*/

	WR_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL, 2); /*Enable Power Domain Transition*/
	WR_MEM_32(CM_DEFAULT_DUCATI_CLKCTRL,   2); /*Enable Ducati Clocks*/


	/*Check CLKIN200TR & CLKINTR  are active*/
	while(((RD_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL)&0x300)>>8)!=3) ;
    GEL_TextOut("\tClock is Active  \n","Output",1,1,1);	 									

    //----------------------WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xEF); /*Enable the Ducati Logic*/
    //--WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE3); /*Enable the Ducati Logic*/
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)RM_DEFAULT_RSTCTRL);
	GEL_TextOut("Tests Executed: %x \n",,,,,*(unsigned int *)RM_DEFAULT_RSTST);

	/*Write Ducate IRAM Boot Image */
	WR_MEM_32(DUCATI_BASE_ADDR,   	  0x10000);
	WR_MEM_32(DUCATI_BASE_ADDR+0x4,   0x9);
	WR_MEM_32(DUCATI_BASE_ADDR+0x8,   0xE7FEE7FE);

    /*Large Page Translations */
	WR_MEM_32(DUCATI_MMU_CFG+0x800,   	  0x60000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x804,   	  0x80000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x808,   	  0xA0000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x80C,   	  0xC0000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x820,   	  0x60000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x824,   	  0x80000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x828,   	  0x40000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x82C,   	  0xC0000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x840,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x844,   	  0x00020007);
	WR_MEM_32(DUCATI_MMU_CFG+0x848,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x84C,   	  0xC0020007);

	/*Medium Page*/

	WR_MEM_32(DUCATI_MMU_CFG+0x860,   	  0x00300000);
	WR_MEM_32(DUCATI_MMU_CFG+0x864,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x868,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x86C,   	  0x00000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x8A0,   	  0x40300000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8A4,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8A8,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8AC,   	  0x00000000);

	WR_MEM_32(DUCATI_MMU_CFG+0x8E0,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0x8E4,   	  0x00020007);
	WR_MEM_32(DUCATI_MMU_CFG+0x8E8,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x8EC,   	  0xC0000000);

	/*Small Page*/

	WR_MEM_32(DUCATI_MMU_CFG+0x920,   	  0x00000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x924,   	  0x40000000);
	WR_MEM_32(DUCATI_MMU_CFG+0x928,   	  0x00004000);
	WR_MEM_32(DUCATI_MMU_CFG+0x92C,   	  0x00008000);
	WR_MEM_32(DUCATI_MMU_CFG+0x930,   	  0x0000C000);

	WR_MEM_32(DUCATI_MMU_CFG+0x9A0,   	  0x55020000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9A4,   	  0x55080000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9A8,   	  0x55024000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9AC,   	  0x55028000);
	WR_MEM_32(DUCATI_MMU_CFG+0x9B0,   	  0x5502C000);

	WR_MEM_32(DUCATI_MMU_CFG+0xA20,   	  0x0001000B);
	WR_MEM_32(DUCATI_MMU_CFG+0xA24,   	  0x0000000B);
	WR_MEM_32(DUCATI_MMU_CFG+0xA28,   	  0x00010007);
	WR_MEM_32(DUCATI_MMU_CFG+0xA2C,   	  0x00000007);
	WR_MEM_32(DUCATI_MMU_CFG+0xA30,   	  0x00000007);
	GEL_TextOut("\tMMU has been written  \n","Output",1,1,1);	 									

    WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE3); //0xE3

	/*Check for Ducati M3_0 & M3_1 out of Reset*/
	while(((RD_MEM_32(RM_DEFAULT_RSTST)&0x1C))!=0x1C) ;

	/*Check Module is in Functional Mode */
	while(((RD_MEM_32(CM_DEFAULT_DUCATI_CLKCTRL)&0x30000)>>16)!=0) ;

    GEL_TextOut("\tPRCM for DucatiSS is Done Successfully  \n","Output",1,1,1);	 									
}



hotmenu IVAHD0ClkEnable()
{
	GEL_TextOut("\tPRCM for IVHD0 is in Progress, Please wait.....  \n","Output",1,1,1);	 									
	WR_MEM_32(CM_IVAHD0_CLKSTCTRL, 		2); /*Enable Power Domain Transition*/
	while(RD_MEM_32(PM_IVAHD0_PWRSTST)!=0x37);	/*Check Power is ON*/
	WR_MEM_32(CM_IVAHD0_IVAHD_CLKCTRL, 	2); /*Enable IVHD0 Clocks*/
	WR_MEM_32(CM_IVAHD0_SL2_CLKCTRL, 	2); /*Enable IVHD0 SL2 Clocks*/

	while(((RD_MEM_32(CM_IVAHD0_CLKSTCTRL)&0x100))!=0x100); /*IVAHD0_GCLK is Active*/

	WR_MEM_32(RM_IVAHD0_RSTCTRL, 	3); /*Enable IVHD0 logic & SL2 */

	while(RD_MEM_32(RM_IVAHD0_RSTST)!=4);

	WR_MEM_32(0x58088000, 0xEAFFFFFE); /*Write Self Branch Instruction in ICONT1 ITCM 0 Location*/

	WR_MEM_32(0x58098000, 0xEAFFFFFE); /*Write Self Branch Instruction in ICONT2 ITCM 0 Location*/

	WR_MEM_32(RM_IVAHD0_RSTCTRL, 	0); /*Bring ICONT1 & ICONT2 out of Reset*/
	
	while(RD_MEM_32(RM_IVAHD0_RSTST)!=7); /*ICONT1 & ICONT2 are out of Reset*/

    GEL_TextOut("\tPRCM for IVHD0 is Done Successfully  \n","Output",1,1,1);	 									
    GEL_TextOut("\tUser Can Connect to ICONT1 & ICONT2 of IVHD0  \n","Output",1,1,1);	 									
}

PrcmTPPSSEnable()
{

	unsigned int fail=0, k=0;

    GEL_TextOut("\tPRCM for TPPSS Initialization in Progress \n","Output",1,1,1);
   	WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xFD); /*Bring TPP ARM out of Reset*/
    	
	/*Enable the TPPSS Clocks*/
	WR_MEM_32(CM_DEFAULT_TPPSS_CLKSTCTRL, 2);
	WR_MEM_32(CM_DEFAULT_TPPSS_CLKCTRL,   2);
	while(((RD_MEM_32(CM_DEFAULT_TPPSS_CLKSTCTRL) & 0x7F00)>>8)!=0x7F);
	while(((RD_MEM_32(CM_DEFAULT_TPPSS_CLKCTRL)&0x30000)>>16)!=0);
    GEL_TextOut("\tPRCM for TPPSS Initialization in Done \n","Output",1,1,1);	 										 

	//Fill the ITCM RAM of TPPSS
	for(k=0; k<10; k++) 
	{
		WR_MEM_32(TPPIRAM_BASE_ADDR+4*k, 0xEAFFFFFE);
	}
    
	/*Check CLKIN200TR & CLKINTR  are active*/
	/*Implement Different Logic in C, Based on Application requirement for TPPSS, Ducati*/
    if((RD_MEM_32(CM_DEFAULT_DUCATI_CLKSTCTRL)&0x300) ==0x300 ) 
	{
		WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xE0); /*Bring Ducati M3_0, M3_1 and TPPSS out of Reset*/
		GEL_TextOut("\tDucati is Already out of Reset, Bring TPPSS out of Reset  \n","Output",1,1,1);	 									
	}
	else 
		WR_MEM_32(RM_DEFAULT_RSTCTRL,   0xFC); /*Bring TPP out of Local Reset*/

	GEL_TextOut("\tTPPSS Initialization in Done \n","Output",1,1,1);	 									
}

hotmenu GEMSSClkEnable()
{
	unsigned int i=0, k=0, fail=0;

	GEL_TextOut("\tPRCM for GEMSS is in Progress, Please wait.....  \n","Output",1,1,1);	 									

	/*Cortex A8 must be in Supervisor Mode to Access the following two registers*/
	WR_MEM_32(DSPMEM_SLEEP, 		0); /*Bring GEM L2RAM out of Power down Mode*/
	WR_MEM_32(DSPBOOTADDR, 		    0x00800000); /*DSPBOOT ADDRESS*/
	
	GEL_TextOut("\t CP0...Done");
	
	/*Enable Clock to MMU CFG*/
	WR_MEM_32(CM_MMUCFG_CLKSTCTRL, 		2); 
	WR_MEM_32(CM_ALWON_MMUCFG_CLKCTRL, 		2); 
	while(((RD_MEM_32(CM_ALWON_MMUCFG_CLKCTRL)&0x0))!=0x0); 
	while(((RD_MEM_32(CM_MMUCFG_CLKSTCTRL)&0x100))!=0x100); 

	GEL_TextOut("\t CP1...Done");

	/*Enable Clock to Data*/
	WR_MEM_32(CM_MMU_CLKSTCTRL, 		2); 
	WR_MEM_32(CM_ALWON_MMUDATA_CLKCTRL, 		2); 
	while(((RD_MEM_32(CM_ALWON_MMUDATA_CLKCTRL)&0x0))!=0x0); 
	while(((RD_MEM_32(CM_MMU_CLKSTCTRL)&0x100))!=0x100); 

	GEL_TextOut("\t CP2...Done");

    /*Enable Clock to GEMSS*/
	WR_MEM_32(CM_GEM_CLKSTCTRL, 		2); /*Enable Power Domain Transition*/
	while(RD_MEM_32(PM_ACTIVE_PWRSTST)!=0x37);	/*Check Power is ON*/
	WR_MEM_32(CM_ACTIVE_GEM_CLKCTRL, 	2); /*Enable GEMSS Clocks*/

	GEL_TextOut("\t CP3...Done");

	while(((RD_MEM_32(CM_GEM_CLKSTCTRL)&0x700))!=0x700); /*GME Clocks are Active*/

	WR_MEM_32(RM_ACTIVE_RSTCTRL, 	1); /*Issue GEM Warm Reset To access GEMSS memories */

    while(((RD_MEM_32(RM_ACTIVE_RSTST)&0x2))!=0x2); /*GEMSS Warm Reset has been Asserted*/

	GEL_TextOut("\t CP4...Done");

    for(i=0; i<8; i++) 
	{
		WR_MEM_32((GEM_L2RAM_BASE_ADDR+4*i), 0x12); /*Write Self Branch Instruction*/
    }

	GEL_TextOut("\t CP5...Done");

	WR_MEM_32(RM_ACTIVE_RSTCTRL, 	0); /*Bring GEM Core out of Reset*/
	
    while(((RD_MEM_32(RM_ACTIVE_RSTST)&0x3))!=0x3); /*GEM core core is out of Reset*/

	GEL_TextOut("\t CP6...Done");

	for(k=0; k<SIZE; k++) 
	{
		WR_MEM_32(GEM_L2RAM_BASE_ADDR+0x100+4*k, 0x12345678+k);
	}

	GEL_TextOut("\t CP7...Done");

    for(k=0;  k<SIZE; k++) 
	{
		if(RD_MEM_32(GEM_L2RAM_BASE_ADDR+0x100+4*k) != (0x12345678+k) ) 
		{
			fail++;
	    }
	}
    if(fail!=0) 
	{
		GEL_TextOut("\tGEM L2 RAM Accesses are FAILED \n","Output",1,1,1);	 										
		GEL_TextOut("\tPRCM for GEMSS is Failed  \n","Output",1,1,1);	 									
		GEL_TextOut("\tDebug the Failed Scenario   \n","Output",1,1,1);	 									
	}

	GEL_TextOut("\tGEM L2 RAM Accesses are PASSED \n","Output",1,1,1);	 										
    GEL_TextOut("\tPRCM for GEMSS is Done Successfully  \n","Output",1,1,1);	 									
    GEL_TextOut("\tUser Can Connect to GEMSS   \n","Output",1,1,1);	 									
}

hotmenu GPMC_ClkEnable()
{
	unsigned int i,data_fail = 0;
	GEL_TextOut("\tEnabling Clock for GPMC is in Progress, Please wait.....  \n","Output",1,1,1);
	WR_MEM_32(CM_ALWON_GPMC_CLKCTRL,    0x2); /*Enable GPMC Clock*/
	while(RD_MEM_32(CM_ALWON_GPMC_CLKCTRL)!=0x2);
	GEL_TextOut("\tGPMC Clock is Active\n","Output",1,1,1);

	GEL_TextOut("Reg default Value: %x \n",,,,,*(unsigned int *)PINCNTL105);

	GEL_TextOut("\tPINMUX configuration is in Progress, Please wait.....  \n","Output",1,1,1);

    WR_MEM_32(PINCNTL235,    RD_MEM_32(PINCNTL235) | 0x1); 
	WR_MEM_32(PINCNTL243,    RD_MEM_32(PINCNTL243) | 0x10); 
	WR_MEM_32(PINCNTL244,    RD_MEM_32(PINCNTL244) | 0x10); 
	WR_MEM_32(PINCNTL245,    RD_MEM_32(PINCNTL245) | 0x10); 
	WR_MEM_32(PINCNTL246,    RD_MEM_32(PINCNTL246) | 0x10); 
	WR_MEM_32(PINCNTL247,    RD_MEM_32(PINCNTL247) | 0x10); 
	WR_MEM_32(PINCNTL248,    RD_MEM_32(PINCNTL248) | 0x10); 
	WR_MEM_32(PINCNTL249,    RD_MEM_32(PINCNTL249) | 0x10); 
	WR_MEM_32(PINCNTL250,    RD_MEM_32(PINCNTL250) | 0x10); 
	WR_MEM_32(PINCNTL251,    RD_MEM_32(PINCNTL251) | 0x10); 
	WR_MEM_32(PINCNTL252,    RD_MEM_32(PINCNTL252) | 0x10); 
	WR_MEM_32(PINCNTL253,    RD_MEM_32(PINCNTL253) | 0x10); 
	WR_MEM_32(PINCNTL254,    RD_MEM_32(PINCNTL254) | 0x10); 
	WR_MEM_32(PINCNTL255,    RD_MEM_32(PINCNTL255) | 0x10); 
	WR_MEM_32(PINCNTL256,    RD_MEM_32(PINCNTL256) | 0x10); 
	WR_MEM_32(PINCNTL257,    RD_MEM_32(PINCNTL257) | 0x10); 
	WR_MEM_32(PINCNTL258,    RD_MEM_32(PINCNTL258) | 0x10); 

	WR_MEM_32(PINCNTL89,    RD_MEM_32(PINCNTL89) | 0x01); 
	WR_MEM_32(PINCNTL90,    RD_MEM_32(PINCNTL90) | 0x01); 
	WR_MEM_32(PINCNTL91,    RD_MEM_32(PINCNTL91) | 0x01); 
	WR_MEM_32(PINCNTL92,    RD_MEM_32(PINCNTL92) | 0x01); 
	WR_MEM_32(PINCNTL93,    RD_MEM_32(PINCNTL93) | 0x01); 
	WR_MEM_32(PINCNTL94,    RD_MEM_32(PINCNTL94) | 0x01); 
	WR_MEM_32(PINCNTL95,    RD_MEM_32(PINCNTL95) | 0x01); 
	WR_MEM_32(PINCNTL96,    RD_MEM_32(PINCNTL96) | 0x01); 
	WR_MEM_32(PINCNTL97,    RD_MEM_32(PINCNTL97) | 0x01); 
	WR_MEM_32(PINCNTL98,    RD_MEM_32(PINCNTL98) | 0x01); 
	WR_MEM_32(PINCNTL99,    RD_MEM_32(PINCNTL99) | 0x01); 
	WR_MEM_32(PINCNTL100,   RD_MEM_32(PINCNTL100) | 0x01); 
	WR_MEM_32(PINCNTL101,   RD_MEM_32(PINCNTL101) | 0x01); 
	WR_MEM_32(PINCNTL102,   RD_MEM_32(PINCNTL102) | 0x01); 
	WR_MEM_32(PINCNTL103,   RD_MEM_32(PINCNTL103) | 0x01); 
	WR_MEM_32(PINCNTL104,   RD_MEM_32(PINCNTL104) | 0x01); 

	WR_MEM_32(PINCNTL105,   RD_MEM_32(PINCNTL105) | 0x01); 
	WR_MEM_32(PINCNTL106,    RD_MEM_32(PINCNTL106) | 0x01); 
	WR_MEM_32(PINCNTL107,    RD_MEM_32(PINCNTL107) | 0x01); 
	WR_MEM_32(PINCNTL108,    RD_MEM_32(PINCNTL108) | 0x01); 
	WR_MEM_32(PINCNTL109,    RD_MEM_32(PINCNTL109) | 0x01); 
	WR_MEM_32(PINCNTL110,    RD_MEM_32(PINCNTL110) | 0x01); 
	WR_MEM_32(PINCNTL111,    RD_MEM_32(PINCNTL111) | 0x01); 
	WR_MEM_32(PINCNTL112,    RD_MEM_32(PINCNTL112) | 0x01); 

	WR_MEM_32(PINCNTL122,    RD_MEM_32(PINCNTL122) | 0x01); 
	WR_MEM_32(PINCNTL123,    RD_MEM_32(PINCNTL123) | 0x01); 
	WR_MEM_32(PINCNTL124,    RD_MEM_32(PINCNTL124) | 0x01); 
	WR_MEM_32(PINCNTL125,    RD_MEM_32(PINCNTL125) | 0x01); 
	WR_MEM_32(PINCNTL126,    RD_MEM_32(PINCNTL126) | 0x01); 
	WR_MEM_32(PINCNTL127,    RD_MEM_32(PINCNTL127) | 0x01); 
	WR_MEM_32(PINCNTL128,    RD_MEM_32(PINCNTL128) | 0x01); 
	WR_MEM_32(PINCNTL129,    RD_MEM_32(PINCNTL129) | 0x01); 
	WR_MEM_32(PINCNTL130,    RD_MEM_32(PINCNTL130) | 0x01); 
	WR_MEM_32(PINCNTL131,    RD_MEM_32(PINCNTL131) | 0x01); 
	WR_MEM_32(PINCNTL132,    RD_MEM_32(PINCNTL132) | 0x01); 
	WR_MEM_32(PINCNTL133,    RD_MEM_32(PINCNTL133) | 0x01); 

	GEL_TextOut("Reg written value: %x \n",,,,,*(unsigned int *)PINCNTL105);


	WR_MEM_32(0x50000060,    RD_MEM_32(0x50000060) & 0xFFFFFCFF);// Bit 9:8 make 00, Non multiplex 
	WR_MEM_32(0x50000078,    RD_MEM_32(0x50000078) & 0xFFFFFFFC); 
	WR_MEM_32(0x50000078,    RD_MEM_32(0x50000078) | 2); // Map to 0x02000000 address
	
	GEL_TextOut("\tPinmux is configured successfully !!!\n","Output",1,1,1);
	GEL_TextOut("\tWait .... busy writing memory \n","Output",1,1,1);

	for(i=0; i<DATA_SIZE; i++) 
	{
	  WR_MEM_32(GPMC_MEM_BASE_ADDR+4*i, 0xABCD0000+i);
	}

	for(i=0; i<DATA_SIZE; i++) 
	{
		if(RD_MEM_32(GPMC_MEM_BASE_ADDR + 4*i) != (0xABCD0000+i) ) 
		{
		    data_fail++;
		}
	}
	if(data_fail != 0)
		GEL_TextOut("\tGPMC Memory write failed, Try again ...\n","Output",1,1,1);
	else
		GEL_TextOut("\tGPMC Memory written successfully !!!\n","Output",1,1,1);


}


hotmenu DDR2_Initialization()
{

	//-EMIF4ClkEnable_Elpida_DDR2();
	EMIF4ClkEnable_Micron_DDR2();

}

EMIF4ClkEnable_Elpida_DDR2() // developed for Elpida componant EDE1116ACBG-1J DDR2-1066 (7-7-7)
{
	unsigned int i,data_fail = 0;

	GEL_TextOut("\t**** EMIF is configured for DDR2 Elpida EDE1116ACBG-1J with Single Device on CS0 **** \n");

	GEL_TextOut("\tPRCM for EMIF0, EMIF1 and DMM are in Progress, Please wait.....  \n","Output",1,1,1);	 									
	WR_MEM_32(CM_DEFAULT_FW_CLKCTRL, 0x2); 		  /*Enable the EMIF FireWall Clocks*/
	WR_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
	WR_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL,    0x2); /*Enable EMIF0 Clock*/
	WR_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL,    0x2); /*Enable EMIF1 Clock*/
	WR_MEM_32(CM_DEFAULT_DMM_CLKCTRL,       0x2); /*Enable EMIF1 Clock*/
	while((RD_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300)!=0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_DMM_CLKCTRL)!=0x2);			/*Poll for Module is functional*/

	//-DDR0_PHY();
	//-DDR1_PHY();

	// Write 1 to ENABLE bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000040 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000040 ); 

	// Write 0 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) & 0xfffffffe ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) & 0xfffffffe ); 
	
	// Write 1 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000001 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000001 ); 

	// Read VTP control registers & check READY bits
	while( (RD_MEM_32(VTP0_CTRL_REG) & 0x00000020) != 0x20);
	while( (RD_MEM_32(VTP1_CTRL_REG) & 0x00000020) != 0x20);

	/*Program the DMM to Access EMIF0 and EMIF1*/
	WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
	WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
		
	GEL_TextOut("\tBusy reading back DMM registers Please wait ...\n","Output",1,1,1);
	while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
	while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);
	GEL_TextOut("\tDMM register read successfully  \n","Output",1,1,1);

	WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

	/*Program EMIF0 CFG Registers*/
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, 0x8);//RL =8 
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, 0x8);//RL =8

	//-WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, 0x9);//RL =9 
	//-WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, 0x9);//RL =9

	WR_MEM_32(EMIF4_0_SDRAM_TIM_1, 0x0EF197EC);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, 0x0EF197EC);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2, 0x144931E2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, 0x144931E2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3, 0x00000447);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, 0x00000447);
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000103D); // ??? should it be depended on actuall freq provided
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, 0x1000103D);
	WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x40801E32);// CL = 7, row size= 13 ODT OFF
	//-WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x41801E32);// CL = 7, row size= 13 ODT 75 Ohms
	//-WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x42801E32);// CL = 7, row size= 13 ODT 150 Ohms
	//-WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x43801E32);// CL = 7, row size= 13 ODT 50 Ohms


	/*Program EMIF1 CFG Registers*/
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, 0x8);
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, 0x8);

	//-WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, 0x9);
	//-WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, 0x9);

	WR_MEM_32(EMIF4_1_SDRAM_TIM_1, 0x0EF197EC);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, 0x0EF197EC);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2, 0x144931E2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, 0x144931E2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3, 0x00000447);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, 0x00000447);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x1000103D);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, 0x1000103D);
	WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x40801E32);// CL = 7, row size= 13 ODT OFF
	//-WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x41801E32);// CL = 7, row size= 13 ODT 75 Ohms     
	//-WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x42801E32);// CL = 7, row size= 13 ODT 150 Ohms    
	//-WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x43801E32);// CL = 7, row size= 13 ODT 50 Ohms     

	GEL_TextOut("\tPRCM for DDR2 EMIF0, EMIF1 and DMM are Initialized Successfully.....  \n","Output",1,1,1);	 									
}

EMIF4ClkEnable_Micron_DDR2() // developed for Micron componant MT476416HR-25
{
	unsigned int i,data_fail = 0;

	GEL_TextOut("\t**** EMIF is configured for DDR2 Elpida EDE1116ACBG-1J with Single Device on CS0 **** \n");

	GEL_TextOut("\tPRCM for EMIF0, EMIF1 and DMM are in Progress, Please wait.....  \n","Output",1,1,1);	 									
	WR_MEM_32(CM_DEFAULT_FW_CLKCTRL, 0x2); 		  /*Enable the EMIF FireWall Clocks*/
	WR_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
	WR_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL,    0x2); /*Enable EMIF0 Clock*/
	WR_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL,    0x2); /*Enable EMIF1 Clock*/
	WR_MEM_32(CM_DEFAULT_DMM_CLKCTRL,       0x2); /*Enable EMIF1 Clock*/
	while((RD_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300)!=0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_DMM_CLKCTRL)!=0x2);			/*Poll for Module is functional*/

	//-DDR0_PHY();
	//-DDR1_PHY();

	// Write 1 to ENABLE bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000040 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000040 ); 

	// Write 0 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) & 0xfffffffe ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) & 0xfffffffe ); 
	
	// Write 1 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000001 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000001 ); 

	// Read VTP control registers & check READY bits
	while( (RD_MEM_32(VTP0_CTRL_REG) & 0x00000020) != 0x20);
	while( (RD_MEM_32(VTP1_CTRL_REG) & 0x00000020) != 0x20);

	/*Program the DMM to Access EMIF0 and EMIF1*/
	WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
	WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
		
	GEL_TextOut("\tBusy reading back DMM registers Please wait ...\n","Output",1,1,1);
	while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
	while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);
	GEL_TextOut("\tDMM register read successfully  \n","Output",1,1,1);

	WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

	/*Program EMIF0 CFG Registers*/
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, 0x7);//RL =5 
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, 0x7);//RL =5
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1, 0x0AAAF552);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, 0x0AAAF552);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2, 0x043631D2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, 0x043631D2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3, 0x00000327);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, 0x00000327);
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x10000C30); 
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, 0x10000C30);
	WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x40801AB2);// CL = 6

	/*Program EMIF1 CFG Registers*/
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, 0x7);
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, 0x7);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1, 0x0AAAF552);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, 0x0AAAF552);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2, 0x043631D2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, 0x043631D2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3, 0x00000327);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, 0x00000327);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x10000C30);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, 0x10000C30);
	WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x40801AB2);// CL = 6

	
	GEL_TextOut("\tPRCM for DDR2 EMIF0, EMIF1 and DMM are Initialized Successfully.....  \n","Output",1,1,1);	 									
}


EMIF4ClkEnable_Elpida_DDR3() // developed for Elpida componant EDJ1116DBSE-DJ DDR3-1333H (9-9-9)
{
	unsigned int i,data_fail = 0;

	GEL_TextOut("\t**** EMIF is configured for DDR2 Elpida EDJ1116DBSE with Single Device on CS0 **** \n");

	GEL_TextOut("\tPRCM for EMIF0, EMIF1 and DMM are in Progress, Please wait.....  \n","Output",1,1,1);	 									
	WR_MEM_32(CM_DEFAULT_FW_CLKCTRL, 0x2); 		  /*Enable the EMIF FireWall Clocks*/
	WR_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
	WR_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL,    0x2); /*Enable EMIF0 Clock*/
	WR_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL,    0x2); /*Enable EMIF1 Clock*/
	WR_MEM_32(CM_DEFAULT_DMM_CLKCTRL,       0x2); /*Enable EMIF1 Clock*/
	while((RD_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300)!=0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_DMM_CLKCTRL)!=0x2);			/*Poll for Module is functional*/

	// Write 1 to ENABLE bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000040 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000040 ); 

	// Write 0 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) & 0xfffffffe ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) & 0xfffffffe ); 
	
	// Write 1 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000001 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000001 ); 

	// Read VTP control registers & check READY bits
	while( (RD_MEM_32(VTP0_CTRL_REG) & 0x00000020) != 0x20);
	while( (RD_MEM_32(VTP1_CTRL_REG) & 0x00000020) != 0x20);

	/*Program the DMM to Access EMIF0 and EMIF1*/
	WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
	WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
		
	GEL_TextOut("\tBusy reading back DMM registers Please wait ...\n","Output",1,1,1);
	while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
	while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);
	GEL_TextOut("\tDMM register read successfully  \n","Output",1,1,1);

	WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

	/*Program EMIF0 CFG Registers*/
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, 0xA);//RL =10 
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, 0xA);//RL =10
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1, 0x1113781C);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, 0x1113781C);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2, 0x384F31E2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, 0x384F31E2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3, 0x00000498);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, 0x00000498);
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000144A); // ??? should it be depended on actuall freq provided
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, 0x1000144A);
	WR_MEM_32(EMIF4_0_SDRAM_CONFIG, 0x60822A32);// CL = 9(prog 10),CWL = 7(prog 2) row size= 13

	/*Program EMIF1 CFG Registers*/
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, 0xA);
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, 0xA);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1, 0x1113781C);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, 0x1113781C);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2, 0x384F31E2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, 0x384F31E2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3, 0x00000498);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, 0x00000498);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x1000144A);
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, 0x1000144A);
	WR_MEM_32(EMIF4_1_SDRAM_CONFIG, 0x60822A32);// CL = 9(prog 10),CWL = 7(prog 2) row size= 13

	GEL_TextOut("\tPRCM for DDR3 EMIF0, EMIF1 and DMM are Initialized Successfully.....  \n","Output",1,1,1);	 									
}


DDR0_PHY()
{
unsigned int Data_Value;	

	Data_Value = ( (PHY_INVERT_CLKOUT << 14) | (CMD_SLAVE_RATIO << 4) | (DLL_LOCK_DIFF) );
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, Data_Value);

	//-- ALL IO cntl for CMD and DATA are at default reset values. Not req. to program.

	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_fifo_we_slave_ratio    FIFO WE */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_1
	WR_MEM_32(DDR0_DATA0_CS0_CTRL1, RD_MEM_32(DDR0_DATA0_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA0_CS0_CTRL1, RD_MEM_32(DDR0_DATA0_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data0 cs1 cntl_1
	WR_MEM_32(DDR0_DATA0_CS1_CTRL1, RD_MEM_32(DDR0_DATA0_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA0_CS1_CTRL1, RD_MEM_32(DDR0_DATA0_CS1_CTRL1) | (PHY_FIFO_WE) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR0_DATA1_CS0_CTRL1, RD_MEM_32(DDR0_DATA1_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA1_CS0_CTRL1, RD_MEM_32(DDR0_DATA1_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR0_DATA1_CS1_CTRL1, RD_MEM_32(DDR0_DATA1_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA1_CS1_CTRL1, RD_MEM_32(DDR0_DATA1_CS1_CTRL1) | (PHY_FIFO_WE) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR0_DATA2_CS0_CTRL1, RD_MEM_32(DDR0_DATA2_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA2_CS0_CTRL1, RD_MEM_32(DDR0_DATA2_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR0_DATA2_CS1_CTRL1, RD_MEM_32(DDR0_DATA2_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA2_CS1_CTRL1, RD_MEM_32(DDR0_DATA2_CS1_CTRL1) | (PHY_FIFO_WE) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR0_DATA3_CS0_CTRL1, RD_MEM_32(DDR0_DATA3_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA3_CS0_CTRL1, RD_MEM_32(DDR0_DATA3_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR0_DATA3_CS1_CTRL1, RD_MEM_32(DDR0_DATA3_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR0_DATA3_CS1_CTRL1, RD_MEM_32(DDR0_DATA3_CS1_CTRL1) | (PHY_FIFO_WE) );

	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_wr_dqs_slave_ratio  Write DQS  */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_0
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) | (PHY_WR_DQS << 10) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) | (PHY_WR_DQS << 10) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) | (PHY_WR_DQS << 10) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) | (PHY_WR_DQS << 10) );


	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_wr_data_slave_ratio   Write Data ratio */
	/*-----------------------------------------------------------------------------------*/
	
	//- data0 cs0 cntl_0
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) & 0xC00FFFFF );
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) | (PHY_WR_DATA << 20) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) | (PHY_WR_DATA << 20) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) | (PHY_WR_DATA << 20) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) | (PHY_WR_DATA << 20) );


	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_rd_dqs_slave_ratio  read DQS */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_0
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA0_CS0_CTRL0, RD_MEM_32(DDR0_DATA0_CS0_CTRL0) | (PHY_RD_DQS));
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA0_CS1_CTRL0, RD_MEM_32(DDR0_DATA0_CS1_CTRL0) | (PHY_RD_DQS));

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA1_CS0_CTRL0, RD_MEM_32(DDR0_DATA1_CS0_CTRL0) | (PHY_RD_DQS));
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA1_CS1_CTRL0, RD_MEM_32(DDR0_DATA1_CS1_CTRL0) | (PHY_RD_DQS));

	//- data2 cs0 cntl_0
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA2_CS0_CTRL0, RD_MEM_32(DDR0_DATA2_CS0_CTRL0) | (PHY_RD_DQS));
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA2_CS1_CTRL0, RD_MEM_32(DDR0_DATA2_CS1_CTRL0) | (PHY_RD_DQS));

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA3_CS0_CTRL0, RD_MEM_32(DDR0_DATA3_CS0_CTRL0) | (PHY_RD_DQS));
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR0_DATA3_CS1_CTRL0, RD_MEM_32(DDR0_DATA3_CS1_CTRL0) | (PHY_RD_DQS));

	/*-----------------------------------------------------------------------------------*/
	/* program dq_offset  DQ vs DQS */
	/*-----------------------------------------------------------------------------------*/

	//- program if required... Netra has not programmed
	// WR_MEM_32(DDR0_DATA0_CTRL, RD_MEM_32(DDR0_DATA0_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR0_DATA0_CTRL, RD_MEM_32(DDR0_DATA0_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR0_DATA1_CTRL, RD_MEM_32(DDR0_DATA1_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR0_DATA1_CTRL, RD_MEM_32(DDR0_DATA1_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR0_DATA2_CTRL, RD_MEM_32(DDR0_DATA2_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR0_DATA2_CTRL, RD_MEM_32(DDR0_DATA2_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR0_DATA3_CTRL, RD_MEM_32(DDR0_DATA3_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR0_DATA3_CTRL, RD_MEM_32(DDR0_DATA3_CTRL) | (PHY_REG_DQ_OFFSET));

}



DDR1_PHY()
{
unsigned int Data_Value;	

	Data_Value = ( (PHY_INVERT_CLKOUT << 14) | (CMD_SLAVE_RATIO << 4) | (DLL_LOCK_DIFF) );
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, Data_Value);

	//-- ALL IO cntl for CMD and DATA are at default reset values. Not req. to program.

	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_fifo_we_slave_ratio    FIFO WE */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_1
	WR_MEM_32(DDR1_DATA0_CS0_CTRL1, RD_MEM_32(DDR1_DATA0_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA0_CS0_CTRL1, RD_MEM_32(DDR1_DATA0_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data0 cs1 cntl_1
	WR_MEM_32(DDR1_DATA0_CS1_CTRL1, RD_MEM_32(DDR1_DATA0_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA0_CS1_CTRL1, RD_MEM_32(DDR1_DATA0_CS1_CTRL1) | (PHY_FIFO_WE) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR1_DATA1_CS0_CTRL1, RD_MEM_32(DDR1_DATA1_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA1_CS0_CTRL1, RD_MEM_32(DDR1_DATA1_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR1_DATA1_CS1_CTRL1, RD_MEM_32(DDR1_DATA1_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA1_CS1_CTRL1, RD_MEM_32(DDR1_DATA1_CS1_CTRL1) | (PHY_FIFO_WE) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR1_DATA2_CS0_CTRL1, RD_MEM_32(DDR1_DATA2_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA2_CS0_CTRL1, RD_MEM_32(DDR1_DATA2_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR1_DATA2_CS1_CTRL1, RD_MEM_32(DDR1_DATA2_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA2_CS1_CTRL1, RD_MEM_32(DDR1_DATA2_CS1_CTRL1) | (PHY_FIFO_WE) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR1_DATA3_CS0_CTRL1, RD_MEM_32(DDR1_DATA3_CS0_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA3_CS0_CTRL1, RD_MEM_32(DDR1_DATA3_CS0_CTRL1) | (PHY_FIFO_WE) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR1_DATA3_CS1_CTRL1, RD_MEM_32(DDR1_DATA3_CS1_CTRL1) & 0xFFFFF800 );
	WR_MEM_32(DDR1_DATA3_CS1_CTRL1, RD_MEM_32(DDR1_DATA3_CS1_CTRL1) | (PHY_FIFO_WE) );

	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_wr_dqs_slave_ratio  Write DQS  */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_0
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) | (PHY_WR_DQS << 10) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) | (PHY_WR_DQS << 10) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) | (PHY_WR_DQS << 10) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) | (PHY_WR_DQS << 10) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) | (PHY_WR_DQS << 10) );


	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_wr_data_slave_ratio   Write Data ratio */
	/*-----------------------------------------------------------------------------------*/
	
	//- data0 cs0 cntl_0
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) & 0xC00FFFFF );
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) | (PHY_WR_DATA << 20) );

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) | (PHY_WR_DATA << 20) );


	//- data2 cs0 cntl_0
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) | (PHY_WR_DATA << 20) );

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) | (PHY_WR_DATA << 20) );
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) & 0xFFF003FF );
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) | (PHY_WR_DATA << 20) );


	/*-----------------------------------------------------------------------------------*/
	/* program data_reg_phy_rd_dqs_slave_ratio  read DQS */
	/*-----------------------------------------------------------------------------------*/

	//- data0 cs0 cntl_0
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA0_CS0_CTRL0, RD_MEM_32(DDR1_DATA0_CS0_CTRL0) | (PHY_RD_DQS));
	//- data0 cs1 cntl_0
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA0_CS1_CTRL0, RD_MEM_32(DDR1_DATA0_CS1_CTRL0) | (PHY_RD_DQS));

	//- data1 cs0 cntl_0
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA1_CS0_CTRL0, RD_MEM_32(DDR1_DATA1_CS0_CTRL0) | (PHY_RD_DQS));
	//- data1 cs1 cntl_0
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA1_CS1_CTRL0, RD_MEM_32(DDR1_DATA1_CS1_CTRL0) | (PHY_RD_DQS));

	//- data2 cs0 cntl_0
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA2_CS0_CTRL0, RD_MEM_32(DDR1_DATA2_CS0_CTRL0) | (PHY_RD_DQS));
	//- data2 cs1 cntl_0
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA2_CS1_CTRL0, RD_MEM_32(DDR1_DATA2_CS1_CTRL0) | (PHY_RD_DQS));

	//- data3 cs0 cntl_0
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA3_CS0_CTRL0, RD_MEM_32(DDR1_DATA3_CS0_CTRL0) | (PHY_RD_DQS));
	//- data3 cs1 cntl_0
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) & 0xFFFFFC00 );
	WR_MEM_32(DDR1_DATA3_CS1_CTRL0, RD_MEM_32(DDR1_DATA3_CS1_CTRL0) | (PHY_RD_DQS));

	/*-----------------------------------------------------------------------------------*/
	/* program dq_offset  DQ vs DQS */
	/*-----------------------------------------------------------------------------------*/

	//- program if required... Netra has not programmed
	// WR_MEM_32(DDR1_DATA0_CTRL, RD_MEM_32(DDR1_DATA0_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR1_DATA0_CTRL, RD_MEM_32(DDR1_DATA0_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR1_DATA1_CTRL, RD_MEM_32(DDR1_DATA1_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR1_DATA1_CTRL, RD_MEM_32(DDR1_DATA1_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR1_DATA2_CTRL, RD_MEM_32(DDR1_DATA2_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR1_DATA2_CTRL, RD_MEM_32(DDR1_DATA2_CTRL) | (PHY_REG_DQ_OFFSET));

	// WR_MEM_32(DDR1_DATA3_CTRL, RD_MEM_32(DDR1_DATA3_CTRL) & 0xFFFFF80F);
	// WR_MEM_32(DDR1_DATA3_CTRL, RD_MEM_32(DDR1_DATA3_CTRL) | (PHY_REG_DQ_OFFSET));

}

hotmenu I2C2Enable()
{
	GEL_TextOut("\t ***** This GEL function is not yet tested....***** \n");	 									
	
	WR_MEM_32(PINCNTL74, 0x00060020);  
	WR_MEM_32(PINCNTL75, 0x00060020);  

	WR_MEM_32(CM_ALWON_I2C_1_CLKSTCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_I2C_1_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
	
	GEL_TextOut("\t ***** I2C[2] is initialized....***** \n");	 									
}

hotmenu I2C0Enable()
{
	GEL_TextOut("\t ***** This GEL function is not yet tested....***** \n");	 									

	UARTClkEnable();
	WR_MEM_32(CM_ALWON_I2C_0_CLKSTCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_I2C_0_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
	
	WR_MEM_32(PINCNTL263, 0x00060001);  
	WR_MEM_32(PINCNTL264, 0x00060001);  
		
	GEL_TextOut("\t ***** I2C[0] is initialized....***** \n");	 									
}
hotmenu BB_IR_Config()
{
	  //PLL_CLOCKS_Config();
      UARTClkEnable();
	  I2C0Enable();	
      WR_MEM_32(PINCNTL77, 0x00050004);
	   GEL_TextOut("\t IR configurations Done Successfully.....  \n","Output",1,1,1);	
}

hotmenu Aic3106_BaseBoard_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for AIC3106 test....***** \n");
    
    //PLL_CLOCKS_Config();
    I2C0Enable();	
    
	WR_MEM_32(PINCNTL16, 0x00060004);  /* MCA2- AHCLKX */
	WR_MEM_32(PINCNTL39, 0x00060001);  /* MCA2- ACLKX */
	WR_MEM_32(PINCNTL40, 0x00060001);  /* MCA2- AFSX */
	WR_MEM_32(PINCNTL41, 0x00060001);  /* MCA2- AXR0 */
	WR_MEM_32(PINCNTL42, 0x00060001);  /* MCA2- AXR1 */
	
	WR_MEM_32(CM_ALWON_MCA_2_CLKSTCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_MCA_2_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/

	GEL_TextOut("\t ***** AIC3106 McASP2 is initialized....***** \n");	 									

}
#define CM_SYSCLK18_CLKSRC				(CTRL_MODULE_BASE_ADDR + 0x020F)
#define CM_SYSCLK18_CLKSEL				(PRCM_BASE_ADDR + 0x0378)
#define CM_DMTIMER_CLKSRC				(CTRL_MODULE_BASE_ADDR + 0x02E0)


hotmenu TIMER_CLOCKS_Config()
{
	GEL_TextOut("\t ***** Initializing Timer-6....***** \n");
	
	WR_MEM_32(CM_SYSCLK18_CLKSEL, 0x1);
	WR_MEM_32(CM_SYSCLK18_CLKSRC, 0x1); /* Set clksrc to 32.768 MHz, Lock Bit? */

	WR_MEM_32(CM_DMTIMER_CLKSRC, RD_MEM_32(CM_DMTIMER_CLKSRC) & 0xFE3FFFFF); /* Selected sysclk18 */
	
	WR_MEM_32(CM_TIMER6_CLKSEL, 0x1);

	WR_MEM_32(CM_ALWON_TIMER_6_CLKCTRL,    0x2); /* Enable Timer-6 Clock */
	while((RD_MEM_32(CM_ALWON_TIMER_6_CLKCTRL) & 0x0F) !=0x2);		/* Poll for Module is functional */
	
	WR_MEM_32(PINCNTL115, 0x00010040);
	GEL_TextOut("\t ***** Timer-6 Initialized....***** \n");
}


hotmenu Ethernet_PinMux_Setup()
{
	GEL_TextOut("\t ***** Configuring ethernet Clk and Mux....***** \n");	 									
	/*
	PINCNTL232 :- rmii_refClk			[40001]
	PINCNTL233 :- rmdio_mclk			[A0001]
	PINCNTL234 :- mdio_d				[E0001]
	*/
	
	/* PIN MUX for EMAC0 */
	
	WR_MEM_32(PINCNTL232, 0x00040001);  
	WR_MEM_32(PINCNTL233, 0x000A0001);  
	WR_MEM_32(PINCNTL234, 0x000E0001);   
	
	WR_MEM_32(PINCNTL235, 0x000C0001);  
	WR_MEM_32(PINCNTL236, 0x000C0001);  
	WR_MEM_32(PINCNTL237, 0x000C0001); 
	WR_MEM_32(PINCNTL238, 0x000C0001);  
	WR_MEM_32(PINCNTL239, 0x00040001);  
	WR_MEM_32(PINCNTL240, 0x00040001); 
	WR_MEM_32(PINCNTL241, 0x00040001);  
	WR_MEM_32(PINCNTL242, 0x00040001);  
	WR_MEM_32(PINCNTL243, 0x00040001); 
	WR_MEM_32(PINCNTL244, 0x00040001);  
	WR_MEM_32(PINCNTL245, 0x00040001);  
	WR_MEM_32(PINCNTL246, 0x00040001); 
    WR_MEM_32(PINCNTL247, 0x00040001); 
	WR_MEM_32(PINCNTL248, 0x00040001);
	WR_MEM_32(PINCNTL249, 0x00000001);
	WR_MEM_32(PINCNTL250, 0x00000001);
	WR_MEM_32(PINCNTL251, 0x00000001);
	WR_MEM_32(PINCNTL252, 0x00000001);  	
	WR_MEM_32(PINCNTL253, 0x00000001);  	
	WR_MEM_32(PINCNTL254, 0x00000001);  	
	WR_MEM_32(PINCNTL255, 0x00000001); 
	WR_MEM_32(PINCNTL256, 0x00000001);  	
	WR_MEM_32(PINCNTL257, 0x00000001);  	
	WR_MEM_32(PINCNTL258, 0x00000001); 

	/* PIN MUX for EMAC1 */	
	WR_MEM_32(PINCNTL204, 0x000C0002);  
	WR_MEM_32(PINCNTL205, 0x000C0002);  
	WR_MEM_32(PINCNTL206, 0x000C0002); 
	WR_MEM_32(PINCNTL207, 0x000C0002);  
	WR_MEM_32(PINCNTL208, 0x00040002);  
	WR_MEM_32(PINCNTL209, 0x00040002); 
	WR_MEM_32(PINCNTL210, 0x00040002);  
	WR_MEM_32(PINCNTL211, 0x00040002);  
	WR_MEM_32(PINCNTL212, 0x00040002); 
	WR_MEM_32(PINCNTL213, 0x00040002);  
	WR_MEM_32(PINCNTL214, 0x00040002);  
	WR_MEM_32(PINCNTL215, 0x00040002); 
    WR_MEM_32(PINCNTL216, 0x00040002); 
	WR_MEM_32(PINCNTL217, 0x00040002);
	WR_MEM_32(PINCNTL218, 0x00000002);
	WR_MEM_32(PINCNTL219, 0x00000002);
	WR_MEM_32(PINCNTL220, 0x00000002);
	WR_MEM_32(PINCNTL221, 0x00000002);  	
	WR_MEM_32(PINCNTL222, 0x00000002);  	
	WR_MEM_32(PINCNTL223, 0x00000002);  	
	WR_MEM_32(PINCNTL224, 0x00000002); 
	WR_MEM_32(PINCNTL225, 0x00000002);  	
	WR_MEM_32(PINCNTL226, 0x00000002);  	
	WR_MEM_32(PINCNTL227, 0x00000002);  
	
	WR_MEM_32(MC_ALWON_ETHNET_CLKSTCTRL,    0x2); /* Enable Ethernet Clock*/
	while((RD_MEM_32(MC_ALWON_ETHNET_CLKSTCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
	
	WR_MEM_32(MC_ALWON_ETH_0_CLKSTCTRL,    0x2); /*Enable Ethernet Clock*/
	while((RD_MEM_32(MC_ALWON_ETH_0_CLKSTCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
	
	WR_MEM_32(MC_ALWON_ETH_1_CLKSTCTRL,    0x2); /*Enable Ethernet Clock*/
	while((RD_MEM_32(MC_ALWON_ETH_1_CLKSTCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/

	while(RD_MEM_32(MC_ALWON_ETHNET_CLKSTCTRL)!=0x302);		/*Poll for Module is functional*/	
	
	GEL_TextOut("\t ***** GMII pin mux and Clk initialized....***** \n");	 									
}

hotmenu SPI_Setup()
{
	GEL_TextOut("\t ***** This GEL function is not yet tested....***** \n");	 									
	
	WR_MEM_32(PINCNTL81, 0x00060001);  	/* SPI0-CS[0] */
	WR_MEM_32(PINCNTL82, 0x00060001);  	/* SPI0-SCLK */
	WR_MEM_32(PINCNTL83, 0x00060001);  	/* SPI0-D0 */
	WR_MEM_32(PINCNTL84, 0x00060001);  	/* SPI0-D1 */
	
	WR_MEM_32(CM_ALWON_SPI_0_CLKSTCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_SPI_0_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/

	GEL_TextOut("\t ***** SPI-0 CS-0 is initialized....***** \n");	 									

}

hotmenu SD_MMC_Setup()
{
	GEL_TextOut("\t ***** This GEL function is not yet tested....***** \n");	 									
	
	WR_MEM_32(PINCNTL1, 0x00050001);  
	WR_MEM_32(PINCNTL2, 0x00060001);  
	WR_MEM_32(PINCNTL3, 0x00060001);  
	WR_MEM_32(PINCNTL4, 0x00060001);  
	WR_MEM_32(PINCNTL5, 0x00060001);  	
	WR_MEM_32(PINCNTL6, 0x00060001);  
	
	WR_MEM_32(CM_ALWON_MMC_HS_1_CLKSTCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_MMC_HS_1_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/

	GEL_TextOut("\t ***** MMC/SD -1 is initialized....***** \n");	 									

}

hotmenu UARTClkEnable()
{
	GEL_TextOut("\t ***** This GEL function is not yet tested....***** \n");	 									

	GEL_TextOut("\tPRCM for UART0, UART2 and UART2 are in Progress, Please wait.....  \n","Output",1,1,1);	 									

	WR_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Slow Domain Peripheral*/

	WR_MEM_32(CM_ALWON_UART_0_CLKCTRL,    0x2); /*Enable UART0 Clock*/
	while(RD_MEM_32(CM_ALWON_UART_0_CLKCTRL)!=0x2);

	WR_MEM_32(CM_ALWON_UART_1_CLKCTRL,    0x2); /*Enable UART1 Clock*/
	while(RD_MEM_32(CM_ALWON_UART_1_CLKCTRL)!=0x2);

	WR_MEM_32(CM_ALWON_UART_2_CLKCTRL,    0x2); /*Enable UART2 Clock*/
	while(RD_MEM_32(CM_ALWON_UART_2_CLKCTRL)!=0x2);
	
	WR_MEM_32(CM_ALWON_UART_3_CLKCTRL,    0x2); /*Enable UART3 Clock*/
	while(RD_MEM_32(CM_ALWON_UART_3_CLKCTRL)!=0x2);
	

	while(RD_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x2100 !=0x2100);

	GEL_TextOut("\tPRCM for UART0, UART1 and UART2 are Done Successfully.....  \n","Output",1,1,1);	 									
}

hotmenu ISS_A8_Enable()
{
     WR_MEM_32(0x48180D00, 0x2); //PM_ISP_PWRSTCTRL
     WR_MEM_32(0x48180D10, 0x3); //RM_ISP_RSTCTRL
     WR_MEM_32(0x48180700, 0x2) ; //CM_ISP_CLKSTCTRL
     WR_MEM_32(0x48180720, 0x2) ;  //CM_ISP_ISP_CLKCTRL
     WR_MEM_32(0x48180724, 0x2) ;  //CM_ISP_FDIF_CLKCTRL
     
	GEL_TextOut("\tPRCM for ISS Done Successfully.....  \n","Output",1,1,1);	 									
}



hotmenu DSSClkEnable()
{
*(unsigned int *)0x48180E10 =0;
GEL_TextOut("\tPower Enabled.....  \n","Output",1,1,1);
/* Enabling DSS Clocks */
	*(unsigned int *)0x48180800=2 ;
	delay();
	*(unsigned int *)0x48180820=2 ;
	delay();
	*(unsigned int *)0x48180824=2 ;	
	delay();


	GEL_TextOut("\tPRCM for DSS in Progress, Please wait.....  \n","Output",1,1,1);
	while ( (*(unsigned int *)0x48180800 & 0x100) != 0x100)
	{
	}

/*Deasserting resets */

*(unsigned int *)0x48180E10 =0;
	GEL_TextOut("\tPRCM for DSS Done Successfully.....  \n","Output",1,1,1);	 							
		
}

hotmenu MLBClkEnable()
{
	GEL_TextOut("\tPRCM for MLB is in Progress, Please wait.....  \n","Output",1,1,1);	 									

	WR_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Slow Domain Peripheral*/

	WR_MEM_32(CM_ALWON_TIMER_2_CLKCTRL, 0x2); /*Enable MLB Clk domain */
	while(RD_MEM_32(CM_ALWON_TIMER_2_CLKCTRL) != 0x2);
	//while(((RD_MEM_32(CM_ALWON_MLB_CLKCTRL)) & (0x3 << 16)) != 0);
	GEL_TextOut("\t1st while loop done...\n");

	/*Ensure the Clk domains are fully functional */

	/* SHB Clk */
	while(RD_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x100 != 0x100);
	GEL_TextOut("\t 2nd while loop done...\n");

	/* SPB and SYS Clk Domain */
	while(RD_MEM_32(CM_ALWON_SYSCLK5_CLKSTCTRL) & 0x100 != 0x100);
	GEL_TextOut("\t 3rd while loop done ... \n");
	// mlb data pin mux
	WR_MEM_32(PINCNTL60, 0x00040001);  
/* 0000 0000 0000 0100 0000 0000 0000 0001*/
	// mlb sig pin mux
	WR_MEM_32(PINCNTL59, 0x00040001);  

	GEL_TextOut("\tPRCM for MLB has been done successfully.\n","Output",1,1,1);
	

}
hotmenu DCANClkEnable()
{
	GEL_TextOut("\tPRCM for DCAN is in Progress, Please wait.....  \n","Output",1,1,1);	 									

	WR_MEM_32(CM_ALWON_L3_SLOW_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Slow Domain Peripheral*/

	WR_MEM_32(CM_ALWON_DCAN_0_1_CLKCTRL, 0x2); /*Enable DCAN Clk domain */
	while(RD_MEM_32(CM_ALWON_DCAN_0_1_CLKCTRL) != 0x2);
	// DCAN0 RX pin mux
	WR_MEM_32(PINCNTL69, 0x00040001);  
	// DCAN0 TX pin mux
//	WR_MEM_32(PINCNTL68, 0x00000001);  
	// DCAN1 RX pin mux, func4
//	WR_MEM_32(PINCNTL73, 0x00040008);  
	// DCAN1 TX pin mux, func4
	WR_MEM_32(PINCNTL72, 0x00000008);  
	GEL_TextOut("\t1st while loop done...\n");



	GEL_TextOut("\tPRCM for DCAN has been done successfully.\n","Output",1,1,1);
	

}

delay()
{
	int del_cnt;
	for(del_cnt=0;del_cnt<200;del_cnt++);
}

HdvpssClkEnable ()
{
	GEL_TextOut("\t Enabling the HDVPSS Clocks.... \n");
	WR_MEM_32(CM_HDVPSS_CLKSTCTRL,0x2);
	WR_MEM_32(CM_HDVPSS_HDMI_CLKCTRL,0x2);
	WR_MEM_32(CM_HDVPSS_HDVPSS_CLKCTRL,0x2);

	WR_MEM_32(0x48180E00,0x3);
	WR_MEM_32(0x48180E10, 0x0);
	
	GEL_TextOut("\t CM_HDVPSS_CLKSTCTRL... \n");
	while((RD_MEM_32(CM_HDVPSS_CLKSTCTRL) & 0x100)!=0x100);
	GEL_TextOut("\t CM_HDVPSS_HDMI_CLKCTRL... \n");
	while(RD_MEM_32(CM_HDVPSS_HDMI_CLKCTRL)!=0x2);
	GEL_TextOut("\t CM_HDVPSS_HDVPSS_CLKCTRL... \n");
	while(RD_MEM_32(CM_HDVPSS_HDVPSS_CLKCTRL)!=0x2);
	GEL_TextOut("\t Done Enabling HDVPSS Clock.... \n");
}

Enable_dvo_hdmi_clk_dss_level()
{
    *(unsigned int *)0x48100100 = 0x01031fff;	         // dss module enable
    *(unsigned int *)0x48100114 = (0x9000D);                //venc settings
    *(unsigned int *)0x48100118 = (0xD);                //venc settings

    //*(volatile Uint32*)0x48100118 = (0xF);
}

Vid0CapturePinMuxConfig ()
{
	GEL_TextOut("\t Setting up Pin-Mux for Video-0 Capture \n");

	WR_MEM_32(PINCNTL134, 0x00040001);  /* VIN0_CLK1 */
    WR_MEM_32(PINCNTL135, 0x00040010);  /* VIN0_A_HSYNC1*/
    WR_MEM_32(PINCNTL136, 0x00040010);  /* VIN0_A_VSYNC1 */
    WR_MEM_32(PINCNTL136, 0x00040001);  /* VIN0_FLD0_MUX0 */
	WR_MEM_32(PINCNTL137, 0x00040001);  /* VIN0_CLK0 */
	WR_MEM_32(PINCNTL138, 0x00040001);  /* VIN0_A_HSYNC */
	WR_MEM_32(PINCNTL139, 0x00040001);  /* VIN0_A_VSYNC */
	WR_MEM_32(PINCNTL140, 0x00040001);  /* VIN0_D0 */
	WR_MEM_32(PINCNTL141, 0x00040001);  /* VIN0_D1 */
	WR_MEM_32(PINCNTL142, 0x00040001);  /* VIN0_D2 */
	WR_MEM_32(PINCNTL143, 0x00040001);  /* VIN0_D3 */
	WR_MEM_32(PINCNTL144, 0x00040001);  /* VIN0_D4 */
	WR_MEM_32(PINCNTL145, 0x00040001);  /* VIN0_D5 */
	WR_MEM_32(PINCNTL146, 0x00040001);  /* VIN0_D6 */
	WR_MEM_32(PINCNTL147, 0x00040001);  /* VIN0_D7 */
	WR_MEM_32(PINCNTL148, 0x00040001);  /* VIN0_D8 */
	WR_MEM_32(PINCNTL149, 0x00040001);  /* VIN0_D9 */
	WR_MEM_32(PINCNTL150, 0x00040001);  /* VIN0_D10 */
	WR_MEM_32(PINCNTL151, 0x00040001);  /* VIN0_D11 */
	WR_MEM_32(PINCNTL152, 0x00040001);  /* VIN0_D12 */
	WR_MEM_32(PINCNTL153, 0x00040001);  /* VIN0_D13 */
	WR_MEM_32(PINCNTL154, 0x00040001);  /* VIN0_D14 */
	WR_MEM_32(PINCNTL155, 0x00040001);  /* VIN0_D15 */
	WR_MEM_32(PINCNTL156, 0x00040001);  /* VIN0_D16 */
	WR_MEM_32(PINCNTL157, 0x00040001);  /* VIN0_D17 */
	WR_MEM_32(PINCNTL158, 0x00040001);  /* VIN0_D18 */
	WR_MEM_32(PINCNTL159, 0x00040001);  /* VIN0_D19 */
	WR_MEM_32(PINCNTL160, 0x00040001);  /* VIN0_D20 */
	WR_MEM_32(PINCNTL161, 0x00040001);  /* VIN0_D21 */
	WR_MEM_32(PINCNTL162, 0x00040001);  /* VIN0_D22 */
	WR_MEM_32(PINCNTL163, 0x00040001);  /* VIN0_D23 */
    WR_MEM_32(PINCNTL164, 0x00040001);  /* vin0_de0_mux1 */
    WR_MEM_32(PINCNTL165, 0x00040001);  /* vin0_de1 */
    WR_MEM_32(PINCNTL166, 0x00040001);  /* vin0_fid0_mux1 */
    WR_MEM_32(PINCNTL167, 0x00040001);  /* vin0_fid1 */
	
    GEL_TextOut("\t ============================================= \n");

}

VidOut0PinConfig()
{
    GEL_TextOut("\Configuring the Pin-Mux for Video-0 output.\n");
    WR_MEM_32(PINCNTL175, 0x00010001);  /* VOUT0_FlD_MUX1 */
    WR_MEM_32(PINCNTL176, 0x00010001);  /* VOUT0_CLK */
    WR_MEM_32(PINCNTL177, 0x00010001);  /* VOUT0_HSYNC */
    WR_MEM_32(PINCNTL178, 0x00010001);  /* VOUT0_VSYNC */
    WR_MEM_32(PINCNTL179, 0x00010001);  /* VOUT0_AVID */
    WR_MEM_32(PINCNTL180, 0x00010001);  /* VOUT0_B_CB_C2 */
    WR_MEM_32(PINCNTL181, 0x00010001);  /* VOUT0_B_CB_C3 */
    WR_MEM_32(PINCNTL182, 0x00010001);  /* VOUT0_B_CB_C4 */
    WR_MEM_32(PINCNTL183, 0x00010001);  /* VOUT0_B_CB_C5 */
    WR_MEM_32(PINCNTL184, 0x00010001);  /* VOUT0_B_CB_C6 */
    WR_MEM_32(PINCNTL185, 0x00010001);  /* VOUT0_B_CB_C7 */
    WR_MEM_32(PINCNTL186, 0x00010001);  /* VOUT0_B_CB_C8 */
    WR_MEM_32(PINCNTL187, 0x00010001);  /* VOUT0_B_CB_C9 */
    WR_MEM_32(PINCNTL188, 0x00010001);  /* VOUT_G_Y_YC2 */
    WR_MEM_32(PINCNTL189, 0x00010001);  /* VOUT_G_Y_YC3 */
    WR_MEM_32(PINCNTL190, 0x00010001);  /* VOUT_G_Y_YC4 */
    WR_MEM_32(PINCNTL191, 0x00010001);  /* VOUT_G_Y_YC5 */
    WR_MEM_32(PINCNTL192, 0x00010001);  /* VOUT_G_Y_YC6 */
    WR_MEM_32(PINCNTL193, 0x00010001);  /* VOUT_G_Y_YC7 */
    WR_MEM_32(PINCNTL194, 0x00010001);  /* VOUT_G_Y_YC8 */
    WR_MEM_32(PINCNTL195, 0x00010001);  /* VOUT_G_Y_YC9 */
    WR_MEM_32(PINCNTL196, 0x00010001);  /* VOUT_R_CR2 */
    WR_MEM_32(PINCNTL197, 0x00010001);  /* VOUT_R_CR3 */
    WR_MEM_32(PINCNTL198, 0x00010001);  /* VOUT_R_CR4 */
    WR_MEM_32(PINCNTL199, 0x00010001);  /* VOUT_R_CR5 */
    WR_MEM_32(PINCNTL200, 0x00010001);  /* VOUT_R_CR6 */
    WR_MEM_32(PINCNTL201, 0x00010001);  /* VOUT_R_CR7 */
    WR_MEM_32(PINCNTL202, 0x00010001);  /* VOUT_R_CR8 */
    WR_MEM_32(PINCNTL203, 0x00010001);  /* VOUT_R_CR9 */
    GEL_TextOut("\tCompleted the Pin-Mux for Video-0 output.\n");

}

hotmenu IS_DEVICE_GP_TEST()

{
    if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0)  {
    
          GEL_TextOut("\tDevice type is TEST \n","Output",1,1,1);
          
        }

    else if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0x300)  {

          GEL_TextOut("\tDevice type is GP \n","Output",1,1,1);

         }
//-    GEL_TextOut("\t control status =  %d\n",RD_MEM_32(CONTROL_STATUS),1,1,1);
    GEL_TextOut("\t control status =  = %x \n",,,,,RD_MEM_32(CONTROL_STATUS));
    
    if( (RD_MEM_32(MODENAPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
       if( (RD_MEM_32(DSPPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {   
          if( (RD_MEM_32(SGXPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
             if( (RD_MEM_32(IVAPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
               if( (RD_MEM_32(L3PLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {   
                  if( (RD_MEM_32(ISSPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
                    if( (RD_MEM_32(DSSPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {   
                      if( (RD_MEM_32(VID0PLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
                        if( (RD_MEM_32(VID1PLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
                          if( (RD_MEM_32(HDMIPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {   
                            if( (RD_MEM_32(AUDIOPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
                               if( (RD_MEM_32(USBPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {   
                                 if( (RD_MEM_32(DDRPLL_CLOCK_CONTROL) & 0x1F000000) == 0x06000000 )  {
                                
                                      GEL_TextOut("\tPLL EFuse are corerct \n","Output",1,1,1);
                                      
                                 }
                               }
                            }
                          }
                        }
                      }
                    }
                  }
                }
              }
            }
          }         
        }

    else  {

          GEL_TextOut("\tPLL EFuse are not corerct \n","Output",1,1,1);

         }   
         
    if( ((RD_MEM_32(BANDGAP0_TRIM) & 0x00FF0000) == 0x00A30000) && ((RD_MEM_32(BANDGAP1_TRIM) & 0x00FF0000) == 0x00A30000) )  {
    
          GEL_TextOut("\tRAM LDO EFuse are corerct \n","Output",1,1,1);
          
        }

    else  {

          GEL_TextOut("\tRAM LDO EFuse are not corerct \n","Output",1,1,1);

         }   
}



hotmenu Unlock_PLL_Control_MMR()

{
    *(unsigned int *)0x481C5040 = 0x1EDA4C3D;
    *(unsigned int *)0x48140060 = 0x2FF1AC2B;
    *(unsigned int *)0x48140064 = 0xF757FDC0;
    *(unsigned int *)0x48140068 = 0xE2BC3A6D;
    *(unsigned int *)0x4814006c = 0x1EBF131D;
    *(unsigned int *)0x48140070 = 0x6F361E05;
    GEL_TextOut("\n PLL and Control MMR unlock done ... \n");   
}


hotmenu OpenFireWall()
{

  if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0)  {
    GEL_TextOut("\tDevice type is TEST \n","Output",1,1,1);
    GEL_TextOut("\tOpen the Firewall for public \n","Output",1,1,1);
    WR_MEM_32(VLYNQ_FW	   ,	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(GPMC_FW 	   ,	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(OCMC_RAM0_FW,		NETRA_TEST_DEVICE_FW_VAL);
//    WR_MEM_32(OCMC_RAM1_FW,		NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(SGX530_FW,	    NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(GEM_SDMA_FW,		NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(DUCATI_FW,		NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(PCIE_FW,		    NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(TPPSS_FW,	    	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(IVAHD_SL2_FW,		NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(IVAHD_CFG_FW,		NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(MCASP_FW, 	    NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(HDMI_FW, 	    	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(MCBSP_FW,	    	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(TPTC_FW, 	    	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(TPCC_FW, 	    	NETRA_TEST_DEVICE_FW_VAL);
    WR_MEM_32(USB_FW, 		    NETRA_TEST_DEVICE_FW_VAL);
  }
  else if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0x300)  {
    GEL_TextOut("\tDevice type is GP \n","Output",1,1,1);
  }
}

hotmenu BaseBoard_CompositeVideo ()
{

	GEL_TextOut("\t ***** Configuring DSS, VENC, DAC for CVBS Output ***** \n");
	
	ALL_ADPLL_CLOCKS_ENABLE_API();
	DSSClkEnable();
	HdvpssClkEnable();
	Enable_dvo_hdmi_clk_dss_level();	
	
	/* VENC Register settings */
	WR_MEM_32(0x48105e00, 0x4fff0000);
	WR_MEM_32(0x48105e04, 0x00000015); /* Color Bar */
	WR_MEM_32(0x48105e08, 0x00000000);	
	WR_MEM_32(0x48105e0c, 0x020d06b4);
	WR_MEM_32(0x48105e10, 0x00000000);
	WR_MEM_32(0x48105e14, 0x00040000);
	WR_MEM_32(0x48105e18, 0x00090005);
	WR_MEM_32(0x48105e1c, 0x000c0006);
	WR_MEM_32(0x48105e20, 0x00000008);
	WR_MEM_32(0x48105e24, 0x200c000e);
	WR_MEM_32(0x48105e28, 0x069200f2);
	WR_MEM_32(0x48105e2c, 0x02060022);
	WR_MEM_32(0x48105e30, 0x02070021);
	WR_MEM_32(0x48105e34, 0x00040000);
	WR_MEM_32(0x48105e38, 0x00090005);
	WR_MEM_32(0x48105e3c, 0x000c0006);
	WR_MEM_32(0x48105e40, 0x00000008);
	WR_MEM_32(0x48105e44, 0x200c000e);
	WR_MEM_32(0x48105e48, 0x069200f2);
	WR_MEM_32(0x48105e4c, 0x02060022);
	WR_MEM_32(0x48105e50, 0x02070021);
	WR_MEM_32(0x48105e54, 0x00000000);
	WR_MEM_32(0x48105e58, 0x00010000);
	WR_MEM_32(0x48105e5c, 0x00000000);
	WR_MEM_32(0x48105e60, 0x00000000);
	WR_MEM_32(0x48105e64, 0x00000000);
	WR_MEM_32(0x48105e68, 0x00000000);
	WR_MEM_32(0x48105e6c, 0x00000000);
	WR_MEM_32(0x48105e70, 0x00000000);
	WR_MEM_32(0x48105e74, 0x00000000);
	WR_MEM_32(0x48105e78, 0x00000000);
	WR_MEM_32(0x48105e7c, 0x00000000);
	WR_MEM_32(0x48105e80, 0x00000003);
	WR_MEM_32(0x48105e84, 0x00000004);
	WR_MEM_32(0x48105e88, 0x069400f4);
	WR_MEM_32(0x48105e8c, 0x02070022);
	WR_MEM_32(0x48105e90, 0x02070022);
	WR_MEM_32(0x48105e94, 0x00d3008f);
	WR_MEM_32(0x48105e98, 0x00000000);
	WR_MEM_32(0x48105e9c, 0x034400bc);
	WR_MEM_32(0x48105ea0, 0x01a20006);
	WR_MEM_32(0x48105ea4, 0x034400bc);
	WR_MEM_32(0x48105ea8, 0x00000010);
	WR_MEM_32(0x48105eac, 0x003700ff);
	WR_MEM_32(0x48105eb0, 0x00000091);
	WR_MEM_32(0x48105eb4, 0x0000009d);
	WR_MEM_32(0x48105eb8, 0x00d31f74);
	WR_MEM_32(0x48105ebc, 0x00001fb9);
	WR_MEM_32(0x48105ec0, 0x00000000);
	WR_MEM_32(0x48105ec4, 0x1fd01f06);
	WR_MEM_32(0x48105ec8, 0x0000012a);
	WR_MEM_32(0x48105ecc, 0x00000000);
	WR_MEM_32(0x48105ed0, 0x003700ff);
	WR_MEM_32(0x48105ed4, 0x00000091);
	WR_MEM_32(0x48105ed8, 0x0000009d);
	WR_MEM_32(0x48105edc, 0x00d31f74);
	WR_MEM_32(0x48105ee0, 0x00001fb9);
	WR_MEM_32(0x48105ee4, 0x00000000);
	WR_MEM_32(0x48105ee8, 0x1fd01f06);
	WR_MEM_32(0x48105eec, 0x00001fb9);
	WR_MEM_32(0x48105ef0, 0x00000000);
	WR_MEM_32(0x48105ef4, 0x00000fff);
	WR_MEM_32(0x48105ef8, 0x180007ff);
	WR_MEM_32(0x48105efc, 0x180007ff);
	WR_MEM_32(0x48105f00, 0x00000fff);
	WR_MEM_32(0x48105f04, 0x00000fff);
	WR_MEM_32(0x48105f08, 0x00000fff);
	WR_MEM_32(0x48105f0c, 0x00000000);
	WR_MEM_32(0x48105f10, 0x00004020);
	WR_MEM_32(0x48105f14, 0xfc000000);
	WR_MEM_32(0x48105f18, 0x00004820);
	WR_MEM_32(0x48105f1c, 0x00000000);
	WR_MEM_32(0x48105f20, 0x004eec06);
	WR_MEM_32(0x48105f24, 0x00000000);
	WR_MEM_32(0x48105f28, 0x00000000);
	WR_MEM_32(0x48105f2c, 0x00000000);
	WR_MEM_32(0x48105f30, 0x00000000);
	WR_MEM_32(0x48105f34, 0x00000000);
	WR_MEM_32(0x48105f38, 0x00000000);
	WR_MEM_32(0x48105f3c, 0x00000000);
	WR_MEM_32(0x48105f40, 0x00000000);
	WR_MEM_32(0x48105f44, 0x00000000);
	WR_MEM_32(0x48105f48, 0x00870000);
	WR_MEM_32(0x48105f4c, 0x00210019);
	WR_MEM_32(0x48105f50, 0x00000000);
	WR_MEM_32(0x48105f54, 0x00000000);
	WR_MEM_32(0x48105f58, 0x004eec06);
	WR_MEM_32(0x48105f5c, 0x00000000);
	WR_MEM_32(0x48105f60, 0x00000000);
	
	WR_MEM_32(0x48140670, 0x0000000DB); /* Enable DACS for CVBS with Calibration Bit Support */

	//WR_MEM_32(0x48140670, 0x018800DB);
//	WR_MEM_32(0x48105e04, 0x00000015); // Start Color Bar

	
	GEL_TextOut("\t ***** Successfully Configured for Composite Video ....***** \n");
}

hotmenu BaseBoard_SVideo ()
{

	GEL_TextOut("\t ***** Configuring DSS, VENC, DAC for S-Video Output ***** \n");
	
	ALL_ADPLL_CLOCKS_ENABLE_API();
	DSSClkEnable();
	HdvpssClkEnable();
	Enable_dvo_hdmi_clk_dss_level();	
	
	/* VENC Register settings */
	WR_MEM_32(0x48105e00, 0x4fff0000);
	WR_MEM_32(0x48105e04, 0x00000015); /* Color Bar */
	WR_MEM_32(0x48105e08, 0x00000000);	
	WR_MEM_32(0x48105e0c, 0x020d06b4);
	WR_MEM_32(0x48105e10, 0x00000000);
	WR_MEM_32(0x48105e14, 0x00040000);
	WR_MEM_32(0x48105e18, 0x00090005);
	WR_MEM_32(0x48105e1c, 0x000c0006);
	WR_MEM_32(0x48105e20, 0x00000008);
	WR_MEM_32(0x48105e24, 0x200c000e);
	WR_MEM_32(0x48105e28, 0x069200f2);
	WR_MEM_32(0x48105e2c, 0x02060022);
	WR_MEM_32(0x48105e30, 0x02070021);
	WR_MEM_32(0x48105e34, 0x00040000);
	WR_MEM_32(0x48105e38, 0x00090005);
	WR_MEM_32(0x48105e3c, 0x000c0006);
	WR_MEM_32(0x48105e40, 0x00000008);
	WR_MEM_32(0x48105e44, 0x200c000e);
	WR_MEM_32(0x48105e48, 0x069200f2);
	WR_MEM_32(0x48105e4c, 0x02060022);
	WR_MEM_32(0x48105e50, 0x02070021);
	WR_MEM_32(0x48105e54, 0x00000000);
	WR_MEM_32(0x48105e58, 0x00010000);
	WR_MEM_32(0x48105e5c, 0x00000000);
	WR_MEM_32(0x48105e60, 0x00000000);
	WR_MEM_32(0x48105e64, 0x00000000);
	WR_MEM_32(0x48105e68, 0x00000000);
	WR_MEM_32(0x48105e6c, 0x00000000);
	WR_MEM_32(0x48105e70, 0x00000000);
	WR_MEM_32(0x48105e74, 0x00000000);
	WR_MEM_32(0x48105e78, 0x00000000);
	WR_MEM_32(0x48105e7c, 0x00000000);
	WR_MEM_32(0x48105e80, 0x00000003);
	WR_MEM_32(0x48105e84, 0x00000004);
	WR_MEM_32(0x48105e88, 0x069400f4);
	WR_MEM_32(0x48105e8c, 0x02070022);
	WR_MEM_32(0x48105e90, 0x02070022);
	WR_MEM_32(0x48105e94, 0x00d3008f);
	WR_MEM_32(0x48105e98, 0x00000000);
	WR_MEM_32(0x48105e9c, 0x034400bc);
	WR_MEM_32(0x48105ea0, 0x01a20006);
	WR_MEM_32(0x48105ea4, 0x034400bc);
	WR_MEM_32(0x48105ea8, 0x00000010);
	WR_MEM_32(0x48105eac, 0x003700ff);
	WR_MEM_32(0x48105eb0, 0x00000091);
	WR_MEM_32(0x48105eb4, 0x0000009d);
	WR_MEM_32(0x48105eb8, 0x00d31f74);
	WR_MEM_32(0x48105ebc, 0x00001fb9);
	WR_MEM_32(0x48105ec0, 0x00000000);
	WR_MEM_32(0x48105ec4, 0x1fd01f06);
	WR_MEM_32(0x48105ec8, 0x0000012a);
	WR_MEM_32(0x48105ecc, 0x00000000);
	WR_MEM_32(0x48105ed0, 0x003700ff);
	WR_MEM_32(0x48105ed4, 0x00000091);
	WR_MEM_32(0x48105ed8, 0x0000009d);
	WR_MEM_32(0x48105edc, 0x00d31f74);
	WR_MEM_32(0x48105ee0, 0x00001fb9);
	WR_MEM_32(0x48105ee4, 0x00000000);
	WR_MEM_32(0x48105ee8, 0x1fd01f06);
	WR_MEM_32(0x48105eec, 0x00001fb9);
	WR_MEM_32(0x48105ef0, 0x00000000);
	WR_MEM_32(0x48105ef4, 0x00000fff);
	WR_MEM_32(0x48105ef8, 0x180007ff);
	WR_MEM_32(0x48105efc, 0x180007ff);
	WR_MEM_32(0x48105f00, 0x00000fff);
	WR_MEM_32(0x48105f04, 0x00000fff);
	WR_MEM_32(0x48105f08, 0x00000fff);
	WR_MEM_32(0x48105f0c, 0x00000000);
	WR_MEM_32(0x48105f10, 0x00004020);
	WR_MEM_32(0x48105f14, 0xfc000000);
	WR_MEM_32(0x48105f18, 0x00004820);
	WR_MEM_32(0x48105f1c, 0x00000000);
	WR_MEM_32(0x48105f20, 0x004eec06);
	WR_MEM_32(0x48105f24, 0x00000000);
	WR_MEM_32(0x48105f28, 0x00000000);
	WR_MEM_32(0x48105f2c, 0x00000000);
	WR_MEM_32(0x48105f30, 0x00000000);
	WR_MEM_32(0x48105f34, 0x00000000);
	WR_MEM_32(0x48105f38, 0x00000000);
	WR_MEM_32(0x48105f3c, 0x00000000);
	WR_MEM_32(0x48105f40, 0x00000000);
	WR_MEM_32(0x48105f44, 0x00000000);
	WR_MEM_32(0x48105f48, 0x00870000);
	WR_MEM_32(0x48105f4c, 0x00210019);
	WR_MEM_32(0x48105f50, 0x00000021); /* S-Video with all DACS Enabled */
	WR_MEM_32(0x48105f54, 0x00000000);
	WR_MEM_32(0x48105f58, 0x004eec06);
	WR_MEM_32(0x48105f5c, 0x00000000);
	WR_MEM_32(0x48105f60, 0x00000000);
	
	WR_MEM_32(0x48140670, 0x18800DB); /* Enable DACS for S-Video with calibration Enabled */

//	WR_MEM_32(0x48105e04, 0x00000015); // Start Color Bar

	
	GEL_TextOut("\t ***** Successfully Configured for S-Video ....***** \n");
}


hotmenu hdmipinmux_cec_ddc()
{
WR_MEM_32(0x481409B8,     0x60010);  /*hdmi_cec_mux0 pinmmr111[4] */
WR_MEM_32(0x48140934,     0xE0002); /*hdmi_ddc_scl_mux0 pinmmr78[1]*/
WR_MEM_32(0x48140938,     0xE0002);  /*hdmi_ddc_sda_mux0 pinmmr79[1] */
WR_MEM_32(0x481409BC,     0x40010);  //hdmi_hpd_mux0 pinmmr112[4]
}

hotmenu configure_hdmi_phy()
{
	unsigned int temp , temp1;
	GEL_TextOut("\tinitialise hdmi phy  config... \n","Output",1,1,1);


 	*(unsigned int *)(0x481815B0) =  0x2;
  	GEL_TextOut("\t48 Mhz Clock input to HDMI ie SDIO clock output from PRCM done... \n","Output",1,1,1);
 
  	/* Power on the phy from wrapper */
  	WR_MEM_32(0x46C00040, 0x8);
 

   	while((RD_MEM_32(0x46C00040) & 0x00000003) != 2);
	GEL_TextOut("\tHDMI PLL CONTROL MODULE IN on STAE DONE... \n","Output",1,1,1);
  	
	WR_MEM_32(0x46C00040, 0x4A);
	while((RD_MEM_32(0x46C00040) & 0x000000FF )  != 0x5A);
 					
	WR_MEM_32(0x46C00040, 0x8A);
	GEL_TextOut("\tinse hdmi reg  config... \n","Output",1,1,1);
  
	while((RD_MEM_32(0x46C00040) & 0xFF)  != 0xAA);
	GEL_TextOut("\tinitialise   config... \n","Output",1,1,1);
	GEL_TextOut("\tHDMI PHY  IN on STAE DONE... \n","Output",1,1,1);
  
	temp =   RD_MEM_32(0x46C00300);			/* Dummy read to PHY base to complete the SCP reset process HDMI_PHY_U_BAS*/
	temp = RD_MEM_32(0x46C00300) ;
  	temp1 = ((temp & 0x3FFFFFFF)| 0x40000000 );
  	WR_MEM_32(0x46C00300, temp1);

  	temp = RD_MEM_32(0x46C0030C) ;
  	temp1 = ((temp & 0x000FFFFF)| 0x85400000 );
	WR_MEM_32(0x46C0030C, temp1);
      WR_MEM_32(0x46C00304, 0xF0000000);
  	GEL_TextOut("\tHDMI PHY  TMDS CLOCK ENABLE DONE ... \n","Output",1,1,1);

	/*temp = RD_MEM_32(0x46C0030C) ;
  	temp1 = ((temp & 0xF7FFFFFF)| 0x08000000 );
  	WR_MEM_32(0x46C0030C, temp1); */

      temp = 0;
  	while (temp ++ < 20 ) {}

	/*WR_MEM_32(0x48141300, 0x02); */                    /* HDMITXPHY pullupdet must be 0 */
	GEL_TextOut("\tinitialise  hdmi phy  done  \n","Output",1,1,1);
}

hotmenu configure_hdvenc_1080p60() 
{
	WR_MEM_32(0x48106000,     0x4003A033); 
	WR_MEM_32(0x48106004,     0x003F0275); 
	WR_MEM_32(0x48106008,     0x1EA500BB); 
	WR_MEM_32(0x4810600C,     0x1F9901C2); 
	WR_MEM_32(0x48106010,     0x1FD71E67); 
	WR_MEM_32(0x48106014,     0x004001C2); 
	WR_MEM_32(0x48106018,     0x00200200); 
	WR_MEM_32(0x4810601C,     0x1B6C0C77); 
	WR_MEM_32(0x48106020,     0x1C0C0C30); 
	WR_MEM_32(0x48106024,     0x1C0C0C30); 
	WR_MEM_32(0x48106028,     0x84465898); 
	WR_MEM_32(0x4810602C,     0x3F000028); 
	WR_MEM_32(0x48106030,     0x587800BF); 
	WR_MEM_32(0x48106034,     0x00000460); 
	WR_MEM_32(0x48106038,     0x000C39E7); 
	WR_MEM_32(0x4810603C,     0x58780118); 
	WR_MEM_32(0x48106040,     0x0002A86D); 
	WR_MEM_32(0x48106044,     0x00438000); 
	WR_MEM_32(0x48106048,     0x05000000); 
	WR_MEM_32(0x4810604C,     0x00003000); 
	WR_MEM_32(0x48106050,     0x00000000); 
	WR_MEM_32(0x48106054,     0x58780110); 
	WR_MEM_32(0x48106058,     0x0002A86D); 
	WR_MEM_32(0x4810605c,     0x00438000); 
	WR_MEM_32(0x48106060,     0x05000000); 
	WR_MEM_32(0x48106064,     0x00003000); 
	WR_MEM_32(0x48106068,     0x00000000); 
	WR_MEM_32(0x4810606c,     0x00000000);
	
}

hotmenu PLL_CLOCKS_Config_hdmi_1_48(){
	unsigned int temp , temp1;
    GEL_TextOut("\tDM814X ALL ADPLL INIT IS IN PROGRESS,Please wait ..... \n","Output",1,1,1);
	ALL_ADPLL_CLOCKS_ENABLE_API();	
	DSSClkEnable();
	
	
	WR_MEM_32(0x48180324, 0x3);   //192Mhz from usb pll divide by 4 to get 48Mhz ddc_cec clock
	WR_MEM_32(0x48100100, 0x01031FFF);
      WR_MEM_32(0x48100114, 0xC010F);
      WR_MEM_32(0x48100118, 0xF);
      *(unsigned int *)0x48100000 = 0x01000000 ;	 //enable dss start of frame interrupt
    
	VIDEO_0_PLL_Config();
	VIDEO_1_PLL_Config();
	GEL_TextOut("\t ****  DM814X ALL ADPLL INIT IS COMPLETE  ******* \n","Output",1,1,1);
	
    hdmipinmux_cec_ddc();
    GEL_TextOut("\t ****  hdmi pin mux  complete  ******* \n","Output",1,1,1);
    
    temp = RD_MEM_32(0x46C00010) ;
    temp1 = ((temp & 0xFFFFFFFE)| 0x1 );
    WR_MEM_32(0x46C00300, temp1);
    
    temp = 0;
    while (temp ++ < 20 ) {}
    GEL_TextOut("\t ****  wrapper soft reset complete  ******* \n","Output",1,1,1);
    
    configure_hdmi_phy();
    GEL_TextOut("\t ****  configure hdmi phy  complete  ******* \n","Output",1,1,1);
    
    temp = RD_MEM_32(0x46C00070) ;
    temp1 = temp | 0x00000218;
    WR_MEM_32(0x46C00070, temp1);
    GEL_TextOut("\t ****  cec clock divider config   complete  ******* \n","Output",1,1,1); 
    
    temp = RD_MEM_32(0x46C00044) ;
    temp1 = temp | 0x00001414;
    WR_MEM_32(0x46C00044, temp1);
    GEL_TextOut("\t ****  wrapper debounce  config   complete  ******* \n","Output",1,1,1); 
 
    temp = RD_MEM_32(0x46C00050) ;
    temp1 = temp | 0x100;
    WR_MEM_32(0x46C00050, temp1);
    GEL_TextOut("\t ****  packing mode configuration    complete  ******* \n","Output",1,1,1); 
  
    WR_MEM_32(0x46C00080, 0x0);
    GEL_TextOut("\t ****  disable audio    complete  ******* \n","Output",1,1,1);
  
    WR_MEM_32(0x46C00414, 0x1); 
    WR_MEM_32(0x46C00424, 0x1);  
    GEL_TextOut("\t ****  release HDMI IP CORE reset and release power down of core complete  ******* \n","Output",1,1,1); 
    
    WR_MEM_32(0x46C00524, 0x0);
    GEL_TextOut("\t ****  video action  config of hdmi  complete  ******* \n","Output",1,1,1); 
    
    WR_MEM_32(0x46C00420, 0x7); 
    GEL_TextOut("\t ****  config input data bus width done   ******* \n","Output",1,1,1); 
    
    WR_MEM_32(0x46C00528, 0x0);   //VID_MODE  CONFIG
    WR_MEM_32(0x46C004CC, 0x1);  //DATA ENABLE CNTRL
    WR_MEM_32(0x46C00420, 0x37);  //ENABLE VSYNC AND HSYNC
    WR_MEM_32(0x46C004F8, 0x0);  //iadjust config to enable vsync
    WR_MEM_32(0x46C00520, 0x10); // csc is bt709 
    WR_MEM_32(0x46C009BC, 0x21);  //enable hdmi 
    
    WR_MEM_32(0x46C00608, 0x20);  //tmds_ctrl
    WR_MEM_32(0x46C00904, 0x0);   //disable n/cts of actrl
    WR_MEM_32(0x46C00950, 0x0);     //disable audio   
    WR_MEM_32(0x46C00414, 0x0);      //   keep audio  operation in reset state
    GEL_TextOut("\t ****  configuring AVI INFOFRAME   ******* \n","Output",1,1,1); 
    
    WR_MEM_32(0x46C00A00 , 0x82);
    WR_MEM_32(0x46C00A04 , 0x2);
    WR_MEM_32(0x46C00A08 , 0xD); 
    WR_MEM_32(0x46C00A10 , 0x1);
    WR_MEM_32(0x46C00A14 , 0xA0);		
    WR_MEM_32(0x46C00A1C , 0x8F);	
    GEL_TextOut("\t ****  configuring AVI INFOFRAME done   ******* \n","Output",1,1,1);     
    

    WR_MEM_32(0x46C00538 , 0x3);    //DISABLE DEEP COLOR MODE IN DC PACKET 
    WR_MEM_32(0x46C009C0 , 0x10);	
    WR_MEM_32(0x46C009F8 , 0x3);	  //ENABLE AND REPEAT AVI INFOFRAM TRANSMISSON
    WR_MEM_32(0x46C009FC , 0xF);    //ENABLE AND REPEAT GENEERAL PACKET TRANSMISSION
    configure_hdvenc_1080p60();
    GEL_TextOut("\t ****  configuring hdvenc for 1080p60 complete   ******* \n","Output",1,1,1);   		 
}

hotmenu PCIE_configure_EP_all()
{

  GEL_TextOut("\tStarting PCIe config... \n","Output",1,1,1);
 control_pcie(); 
  GEL_TextOut("\tPCIe PLL initialiation done ... \n","Output",1,1,1);
  Configure_PLL(); 
  GEL_TextOut("\tConfigure_PLL done  \n","Output",1,1,1);

  ep_configure_mode(); 
  GEL_TextOut("\tconfigure mode as EP done  \n","Output",1,1,1);

  ep_start_link_train();
  GEL_TextOut("\tLink training EP Done  \n","Output",1,1,1); 
  
  configure_ep();
  GEL_TextOut("\tconfigure EP done  \n","Output",1,1,1);
  
  GEL_TextOut("\twaiting for data transfer EP \n","Output",1,1,1);
  
}

Configure_PLL ()
{
 unsigned int temp, temp1;
 /*     RM_DEFAULT_RSTCTRL register which has the reset enable for PCIE */
 temp =  *(unsigned int *) (0x48180b10);
 
 /* RM_DEFAULT_RSTST register is used for clearing the reset for PCIE  */
 temp1 =  *(unsigned int *) (0x48180b14);

 /*-------reset sequence-------------------------*/

 if((temp & 0x80) == 0x80)
    *(unsigned int *)(0x48180b10) = (temp & (~0x80)); /* clearing the PCIE reset */

 if((temp1 & 0x80) == 0x80)
    *(unsigned int *)(0x48180b14) = (temp1 | 0x80); /* clearing the PCIE reset */


 /*---------clock enable sequence------------------*/
  temp =  *(unsigned int *) (0x48180510);
 /* CM_DEFAULT_PCI_CLKSTCTRL - Start a software forced wake-up transition on the domain. */
 *(unsigned int *)(0x48180510) = 0x2; 
   GEL_TextOut("\tCM_DEFAULT_PCI_CLKSTCTRL - Start a software forced wake-up transition on the domain... \n","Output",1,1,1);

/*
     //CM_DEFAULT_PCI_CLKCTRL - Module is explicitly enabled.
     //Interface clock (if not used for functions) may be gated according to the clock domain state.
     //Functional clocks are guarantied to stay present.
     //As long as in this configuration, power domain sleep transition cannot happen.
 	WR_MEM_32_VOLATILE(0x48180578, 0x2);
 	while((RD_MEM_32_VOLATILE(0x48180578) & 0x70000) != 0);
*/
 *(unsigned int *)(0x48180578) = 0x2; 
  GEL_TextOut("\tCM_DEFAULT_PCI_CLKCTRL - Module is explicitly enabled... \n","Output",1,1,1);
  while((RD_MEM_32(0x48180578) & 0x70000) != 0);
}

ep_configure_mode()
{
unsigned int temp , temp1 ;	 	

  *(unsigned int *)(0x48140480) = 0x000000;
  *(unsigned int *)(0x5100180C) = 0x00010F;
  temp1 = RD_MEM_32(0x51001710) | 0x10000;
  WR_MEM_32(0x51001710, temp1);
 GEL_TextOut("\tMode configured to EP \n","Output",1,1,1);

}

configure_ep()
{
  unsigned int temp = 0;
  
  GEL_TextOut("\tEntering configure EP \n","Output",1,1,1);
  
     
     // Data transfer configuration
 	temp = RD_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS) | 0x20;
 	WR_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS,temp);
 
        GEL_TextOut("\tBAR size write EP \n","Output",1,1,1);
 
     //Configure BAR size
        WR_MEM_32(PCIE_REGISTER_BASE + EP_TYP0_BAR0,0xFFF);
 	WR_MEM_32(PCIE_REGISTER_BASE + EP_TYP0_BAR1,0xFFFFF);

 
 	temp = RD_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS) & 0xffffff0f;
 	WR_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS,temp);
 
        GEL_TextOut("\tBAR value write EP \n","Output",1,1,1);
 
 	WR_MEM_32(PCIE_REGISTER_BASE + EP_TYP0_BAR0, 0);
	WR_MEM_32(PCIE_REGISTER_BASE + EP_TYP0_BAR1, 0x80000000 + 0x8);
 
    GEL_TextOut("\tIB config write EP \n","Output",1,1,1);
 
 	WR_MEM_32(PCIE_REGISTER_BASE + 0x300, 0x1);
 	WR_MEM_32(PCIE_REGISTER_BASE + 0x304, 0x80000000);
 	WR_MEM_32(PCIE_REGISTER_BASE + 0x308, 0x0);
	WR_MEM_32(PCIE_REGISTER_BASE + 0x30C, 0x40300000);
		
	GEL_TextOut("\tEnable IB translation EP \n","Output",1,1,1);
	
	temp = RD_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS) | 0x4;
    WR_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS, temp);
    
    WR_MEM_32(PCIE_REGISTER_BASE+ EP_TYP0_STAT_CMD, 0x2); 
        
 
} 
 
ep_start_link_train()
{
    unsigned int temp = 0;
    
       GEL_TextOut("\tlink training start EP \n","Output",1,1,1);
    
       /* Set PCS_CFG0*/
        *(unsigned int *)(0x51000710) = *(unsigned int *)(0x51000710) & 0xFFC1FFFF ;
       *(unsigned int *)(0x51000380) = 0x2110;
   
      /* Start link training */
        temp = RD_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS) | 0x1; 
        WR_MEM_32(PCIE_REGISTER_BASE + EP_APPL_CMD_STATUS, temp);  
		
        while((RD_MEM_32(PCIE_REGISTER_BASE + EP_PL_DEBUG0) & 0x1F) != 0x11);
        
}


wait_idle(int var)
{ 
int temp;
for (temp =0; temp < var ; temp++);
}


control_pcie()
{
     WR_MEM_32(0x481409A0,0x00000001);
    WR_MEM_32(0x481409A4,0x00000001);
    WR_MEM_32(0x481409A8,0x00000001);
    WR_MEM_32(0x481409AC,0x00000001);
    WR_MEM_32(0x48140E24,0x00000002); /* PowerDown */
    WR_MEM_32(0x481406D8,0x00000000); /* cfgpll0 */
    WR_MEM_32(0x481406DC,0x00640000); /* cfgpll1 */
    WR_MEM_32(0x481406E0,0x00000000); /* cfgpll2 */
    WR_MEM_32(0x481406E4,0x004008E0); /* cfgpll3 */
    WR_MEM_32(0x481406E8,0x0000609C); /* cfgpll4 */
    WR_MEM_32(0x48141318,0x00000E7B); /* pcie_serdes_cfg_misc */
    wait_idle(1); // Wait 100 ns
    WR_MEM_32(0x481406D8,0x00000004); /* Config PLL CFG0 bit [2] - ENBGSC_REF  */
    wait_idle(3); // Wait 250 ns 
    WR_MEM_32(0x481406D8,0x00000014); /* Config PLL CFG0 bit [4] - DIGLDO */
    wait_idle(2); // Wait 200 ns
    WR_MEM_32(0x481406D8,0x00000016); /* Config PLL CFG0 bit [1] - ENPLLLDO */
    wait_idle(2); // Wait 200 ns
    WR_MEM_32(0x481406D8,0x30000016); /*  Configure proxy TXLDO and RXLDO enables (DM814X ECO 3/30/10) */
    wait_idle(2); // Wait 200 ns
    WR_MEM_32(0x481406D8,0x70007016);  /* Configure multiplier */
    wait_idle(2); // Wait 200 ns
    WR_MEM_32(0x481406D8,0x70007017);  /* Enable PLL */
}

hotmenu PCIE_configure_RC_all()
{

  GEL_TextOut("\tStarting PCIe config... \n","Output",1,1,1);
  control_pcie(); 
  GEL_TextOut("\tPCIe PLL initialiation done ... \n","Output",1,1,1);
  Configure_PLL(); 
  GEL_TextOut("\tConfigure PLL done  \n","Output",1,1,1);

  rc_configure_mode(); 
  GEL_TextOut("\tconfigure mode as RC done  \n","Output",1,1,1);

  rc_start_link_train();
  GEL_TextOut("\tLink training RC Done  \n","Output",1,1,1);

  configure_rc();
  GEL_TextOut("\tconfigure RC done   \n","Output",1,1,1);
  
   PCIE_rc_data_transfer();
  GEL_TextOut("\tData transfer done  \n","Output",1,1,1);
  

}


hotmenu PCIE_read_bar_size()
{
   unsigned int temp1 = 0, temp2 = 0;
  GEL_TextOut("\tReading bar size on EP... \n","Output",1,1,1);
  
  WR_MEM_32(PCIE_REGISTER_BASE + RM_RC_TYP0_BAR0, 0xFFFFFFFF) ;
  WR_MEM_32(PCIE_REGISTER_BASE + RM_RC_TYP0_BAR1, 0xFFFFFFFF) ;  
  
  temp1 = RD_MEM_32(PCIE_REGISTER_BASE + RM_RC_TYP0_BAR0);
  temp2 = RD_MEM_32(PCIE_REGISTER_BASE + RM_RC_TYP0_BAR1);
  
  
  WR_MEM_32(0x40300100, temp1) ;
  WR_MEM_32(0x40300104, temp2) ;
  GEL_TextOut("\tReading bar size done \n","Output",1,1,1);  
  
  
}

rc_configure_mode()
{
unsigned int temp ,temp1;

/* check for PLL PCIe lock */
/* while((RD_MEM_32(0x48140640) & 0xF00) != 0x100); */

 /* Configure as RC */
 *(unsigned int *)(0x48140480) = 0x000002;
  *(unsigned int *)(0x5100180C) = 0x00010F;
  temp = RD_MEM_32(0x51001710);
  temp1 = temp & 0xFFF1FFFF;
  WR_MEM_32(0x51001710, temp1);
 GEL_TextOut("\tMode configured to RC \n","Output",1,1,1);

}

configure_rc()
{
  unsigned int temp = 0;
  
  GEL_TextOut("\tEntering configure RC \n","Output",1,1,1);
  

  GEL_TextOut("\tSetting up OB_SIZE \n","Output",1,1,1);

  /* configuring outbound size to be 8MB each */
  WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_OB_SIZE, OB_SIZE);


  GEL_TextOut("\tSetting up OB_OFFSET... \n","Output",1,1,1);

  /* Configuring OB registers */
  for(temp=0;temp<32;temp++)
  {
	WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_OB_OFFSET_INDEX(temp), 0x80000000 + (0x100000 << OB_SIZE) * temp + 0x1);
	WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_OB_OFFSET_HI(temp), 0x0);
  }
  
    GEL_TextOut("\tSetting up OB_OFFSET done\n","Output",1,1,1);
} 
 
rc_start_link_train()
{
    unsigned int temp = 0;
    
     GEL_TextOut("\tlink training start RC \n","Output",1,1,1);
    
       /* Set PCS_CFG0*/
       *(unsigned int *)(0x51000710) = *(unsigned int *)(0x51000710) & 0xFFC1FFFF ;
       *(unsigned int *)(0x51000380) = 0x2110;
   
      /* Start link training */
        temp = RD_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS) | 0x1; 
        WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS, temp);  
		
        while((RD_MEM_32(PCIE_REGISTER_BASE + RC_PL_DEBUG0) & 0x1F) != 0x11);	
        
}

 hotmenu PCIE_rc_data_transfer()
{
   unsigned int *p_pcie_target_base, temp;

  /*(80800000(Base address) - IB_OFFSET0(0x40400000) | Bit (27:23) = 1 to select OB_OFFSET 1 register ) + 0x20000000
     OR with 0x00800000 is to select OB_OFFSET REGISTER 1 */
     
       GEL_TextOut("\tEntering data transfer \n","Output",1,1,1);
       
    /* WR_MEM_32(PCIE_REGISTER_BASE + RC_TYP1_STAT_CMD, 0x546);*/
    WR_MEM_32(PCIE_REGISTER_BASE+ RC_TYP1_STAT_CMD, 0x6);   
       
    GEL_TextOut("\tSetting APPL_CMD... \n","Output",1,1,1);    
       
    temp = RD_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS) | 0x02; 
    WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS, temp);       

	 p_pcie_target_base = (unsigned int *)0x20000000;

       GEL_TextOut("\tStarting data transfer... \n","Output",1,1,1);

         *p_pcie_target_base++ = 0x00000020;
	 *p_pcie_target_base++ = 0x404001A0;

	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;

	 *p_pcie_target_base++ = 0xEAFFFFFE;
	 *p_pcie_target_base++ = 0xDEADBABE;

  GEL_TextOut("\tData transfer done  \n","Output",1,1,1);	 
  
/*  p_pcie_target_base = (unsigned int *)(0x20000000 + (0x100000 << OB_SIZE) * 1);
  *p_pcie_target_base = 0x12345678;
  
  GEL_TextOut("\tFlag written...Done  \n","Output",1,1,1);	*/  
   
}

rc_data_transfer_dummy()
{
   unsigned int *p_pcie_target_base, temp;

  /*(80800000(Base address) - IB_OFFSET0(0x40400000) | Bit (27:23) = 1 to select OB_OFFSET 1 register ) + 0x20000000
     OR with 0x00800000 is to select OB_OFFSET REGISTER 1 */
     
       GEL_TextOut("\tEntering data transfer \n","Output",1,1,1);
       
    /* WR_MEM_32(PCIE_REGISTER_BASE + RC_TYP1_STAT_CMD, 0x546);*/
    WR_MEM_32(PCIE_REGISTER_BASE+ RC_TYP1_STAT_CMD, 0x6);   
       
    GEL_TextOut("\tSetting APPL_CMD... \n","Output",1,1,1);    
       
    temp = RD_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS) | 0x02; 
    WR_MEM_32(PCIE_REGISTER_BASE + RC_APPL_CMD_STATUS, temp);       

	 p_pcie_target_base = (unsigned int *)0x20C00000;

       GEL_TextOut("\tStarting data transfer... \n","Output",1,1,1);

         *p_pcie_target_base++ = 0x00000020;
	 *p_pcie_target_base++ = 0x404001A0;

	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;
	 *p_pcie_target_base++ = 0xE1A00000;

	 *p_pcie_target_base++ = 0xEAFFFFFE;
	 *p_pcie_target_base++ = 0xDEADBABE;

  GEL_TextOut("\tData transfer done  \n","Output",1,1,1);	 
  
/*  p_pcie_target_base = (unsigned int *)(0x20000000 + (0x100000 << OB_SIZE) * 1);
  *p_pcie_target_base = 0x12345678;
  
  GEL_TextOut("\tFlag written...Done  \n","Output",1,1,1);	*/  
   
}


menuitem "Video Security Board Initialization"
hotmenu VSEC_Uart2 ()
{
    //PLL_CLOCKS_Config();
    UARTClkEnable();
    WR_MEM_32(PINCNTL68, 0x00020002);  
    WR_MEM_32(PINCNTL69, 0x00060002);  
}


hotmenu VS_TVP5158Audio()
{
    GEL_TextOut("Starting the TVP5158 Audio-Video Configuration...\r\n");
    Aic3106_BaseBoard_Setup();
    I2C2Enable ();
    
    WR_MEM_32(PINCNTL17, 0x00060001);  /* MCA0-ACLKX */
    WR_MEM_32(PINCNTL18, 0x00060001);  /* MCA0- FSX*/
    WR_MEM_32(PINCNTL19, 0x00060001);  /* MCA0- CLKR */
    WR_MEM_32(PINCNTL20, 0x00060001);  /* MCA0- FSR */
    WR_MEM_32(PINCNTL21, 0x00060001);  /* MCA0- AXR0  */
    WR_MEM_32(PINCNTL22, 0x00060001);  /* MCA0- AXR1 */
    WR_MEM_32(PINCNTL23, 0x00060001);  /* MCA0- AXR2 */
    WR_MEM_32(PINCNTL24, 0x00060001);  /* MCA0- AXR3 */
    WR_MEM_32(PINCNTL25, 0x00060001);  /* MCA0- AXR4 */
    WR_MEM_32(PINCNTL26, 0x00060001);  /* MCA0- AXR5 */
    WR_MEM_32(PINCNTL27, 0x00060001);  /* MCA0- AXR6 */
    WR_MEM_32(PINCNTL28, 0x00060001);  /* MCA0- AXR7 */
    WR_MEM_32(PINCNTL29, 0x00060001);  /* MCA0- AXR8 */
    WR_MEM_32(PINCNTL30, 0x00060001);  /* MCA0- AXR9 */
    
    
	WR_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL,    0x2); /*Enable McASP0 Clock*/
	while(RD_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
    
    GEL_TextOut("Completed the TVP5158 Audio-Video Configuration...\r\n");
}


hotmenu Tvp5158VideoConfig()
{
	GEL_TextOut("\t ============================================= \n");
	GEL_TextOut("\t PinMux Settings for TVP5158 capture Test.... \n");
	GEL_TextOut("\t ============================================= \n");
    IVAHD0ClkEnable();    
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
	//DDR2_Initialization();
	I2C0Enable();
	I2C2Enable();
    Vid0CapturePinMuxConfig();
    HdvpssClkEnable();
    Enable_dvo_hdmi_clk_dss_level();
	GEL_TextOut("\t ========================================================= \n");
	GEL_TextOut("\t ***** PinMux Done for Tvp5158 Video capture Test....***** \n");
	GEL_TextOut("\t ========================================================= \n");
}

hotmenu VS_Sil9022aConfig ()
{
	GEL_TextOut("\t ============================================= \n");
    GEL_TextOut("\tConfiguring the Pin-Mux for Sil9022A output.\n");
	GEL_TextOut("\t ============================================= \n");
    IVAHD0ClkEnable();
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
    //DDR2_Initialization();
    I2C0Enable ();
    I2C2Enable ();
    VidOut0PinConfig();
    HdvpssClkEnable();
    Enable_dvo_hdmi_clk_dss_level();
        
	GEL_TextOut("\t ============================================= \n");
    GEL_TextOut("\t ***** Successfully concluded the Initialization....***** \n");
	GEL_TextOut("\t ============================================= \n");
   
}
hotmenu VS_NOR_flash()
{

    GEL_TextOut("\t ***** Initialising  NOR flash....***** \n");	 	
		 	   
	//PLL_CLOCKS_Config();
	//DDR2_Initialization();
	GPMC_ClkEnable();
	  
    WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		
    while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);

    WR_MEM_32(PINCNTL117, 0x00010002); //GPMC_A[1]
    WR_MEM_32(PINCNTL118, 0x00010002); //GPMC_A[2]
    WR_MEM_32(PINCNTL119, 0x00010002); //GPMC_A[3] 
    WR_MEM_32(PINCNTL120, 0x00010002); //GPMC_A[4]
    WR_MEM_32(PINCNTL168, 0x00010010); //GPMC_A[5]
    WR_MEM_32(PINCNTL169, 0x00010010); //GPMC_A[6]
    WR_MEM_32(PINCNTL170, 0x00010010); //GPMC_A[7]
    WR_MEM_32(PINCNTL171, 0x00010010); //GPMC_A[8]
    WR_MEM_32(PINCNTL172, 0x00010010); //GPMC_A[9]
    WR_MEM_32(PINCNTL173, 0x00010010); //GPMC_A[10]
    WR_MEM_32(PINCNTL174, 0x00010010); //GPMC_A[11]
    WR_MEM_32(PINCNTL175, 0x00010010); //GPMC_A[12]
    WR_MEM_32(PINCNTL228, 0x00010002); //GPMC_A[13]
    WR_MEM_32(PINCNTL229, 0x00010002); //GPMC_A[14]
    WR_MEM_32(PINCNTL230, 0x00010002); //GPMC_A[15]
	WR_MEM_32(PINCNTL105, 0x00010001); //GPMC_A[16]
	WR_MEM_32(PINCNTL106, 0x00010001); //GPMC_A[17]
	WR_MEM_32(PINCNTL107, 0x00010001); //GPMC_A[18]
	WR_MEM_32(PINCNTL108, 0x00010001); //GPMC_A[19]
	WR_MEM_32(PINCNTL109, 0x00010001); //GPMC_A[20]
	WR_MEM_32(PINCNTL110, 0x00010001); //GPMC_A[21]
	WR_MEM_32(PINCNTL115, 0x00010004); //GPMC_A[22]
	WR_MEM_32(PINCNTL116, 0x00010004); //GPMC_A[23]
	WR_MEM_32(PINCNTL113, 0x00010002); //GPMC_A[24]
	WR_MEM_32(PINCNTL54,  0x00010080); //GPMC_A[25],gpo[24]
		             
    GEL_TextOut("\t ***** GPMC initialised for Nor flash....***** \n");	 		
} 

menuitem "Video Conference Board Initialization"
hotmenu VCONF_Sil9022a90 ()
{
    GEL_TextOut("\tConfiguring the Pin-Mux for Sil9022A output.\n");
    
    IVAHD0ClkEnable();
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
    //DDR2_Initialization();
    I2C0Enable ();
    I2C2Enable ();
    VidOut0PinConfig();
    HdvpssClkEnable();
    Enable_dvo_hdmi_clk_dss_level();
        
    GEL_TextOut("\t ***** Successfully concluded the Initialization....***** \n");
   
}

hotmenu VCONF_AIC3101_Config ()
{
    GEL_TextOut("Started the VCONF AIC3101 configuration ...\r\n");
    Aic3106_BaseBoard_Setup();
    I2C2Enable ();
    GEL_TextOut("Setting the McASP1 Pin mux control ...\r\n");
    WR_MEM_32(PINCNTL31, 0x00060001);  /* MCA1-ACLKX */
    WR_MEM_32(PINCNTL32, 0x00060001);  /* MCA1- FSX*/
    WR_MEM_32(PINCNTL33, 0x00060001);  /* MCA1- CLKR */
    WR_MEM_32(PINCNTL34, 0x00060001);  /* MCA1- FSR */
    WR_MEM_32(PINCNTL35, 0x00060001);  /* MCA1- AXR0  */
    WR_MEM_32(PINCNTL36, 0x00060001);  /* MCA1- AXR1 */
    WR_MEM_32(PINCNTL37, 0x00060001);  /* MCA1- AXR2 */
    WR_MEM_32(PINCNTL38, 0x00060001);  /* MCA1- AXR3 */
    
    GEL_TextOut("Enabling the Always on Clock...\r\n");
	WR_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL,    0x2); /*Enable McASP1 Clock*/
	while(RD_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
    
    GEL_TextOut("Completed the VCONF AIC3101 Configuration...\r\n");
}
hotmenu VCONF_Uart0()
{
    //PLL_CLOCKS_Config();
    I2C0Enable();
    UARTClkEnable();
    WR_MEM_32(PINCNTL124, 0x00040080);  /* GPI1 25 */
    WR_MEM_32(PINCNTL125, 0x00060080);  /* GPI1 26 */
}

hotmenu VCONF_HDMIRXConfig()
{
	GEL_TextOut("\t ============================================= \n");
	GEL_TextOut("\t HDMI RX: PinMux Settings for Sil9135 Test.... \n");
	GEL_TextOut("\t ============================================= \n");
    IVAHD0ClkEnable();
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
	//DDR2_Initialization();
	I2C0Enable();
	I2C2Enable();
	
	GEL_TextOut("\t HDMI RX: MCASP0 PinMux.... \n");
	WR_MEM_32(PINCNTL19, 0x00060001);  /* MCA0_ACLKR */
	WR_MEM_32(PINCNTL20, 0x00060001);  /* MCA0_AFSR */
	WR_MEM_32(PINCNTL21, 0x00060001);  /* MCA0_AXR0 */
	WR_MEM_32(PINCNTL22, 0x00060001);  /* MCA0_AXR1 */
	WR_MEM_32(PINCNTL23, 0x00060001);  /* MCA0_AXR2 */
	WR_MEM_32(PINCNTL24, 0x00060001);  /* MCA0_AXR3 */
	WR_MEM_32(PINCNTL25, 0x00060001);  /* MCA0_AXR4 */
	
	GEL_TextOut("\t HDMI RX: INTR PinMux.... \n");
	WR_MEM_32(PINCNTL173, 0x00040008);  /* HDMI_RCV_INT */
	
	GEL_TextOut("\t HDMI RX: SYNC and CLK PinMux.... \n");
	WR_MEM_32(PINCNTL204, 0x00060004);  /* VIN1_A_HSYNC */
	WR_MEM_32(PINCNTL205, 0x00060004);  /* VIN1_A_VSYNC */
	WR_MEM_32(PINCNTL206, 0x00060004);  /* VIN1_A_FLD */
	WR_MEM_32(PINCNTL207, 0x00060004);  /* VIN1_A_CLK */
	
	GEL_TextOut("\t HDMI RX: Data Line PinMux.... \n");
	WR_MEM_32(PINCNTL208, 0x00060004);  /* HDRX_B0 - VIN1_A_D0 */
	WR_MEM_32(PINCNTL209, 0x00060004);  /* HDRX_B1 - VIN1_A_D1 */
	WR_MEM_32(PINCNTL210, 0x00060004);  /* HDRX_B2 - VIN1_A_D2 */
	WR_MEM_32(PINCNTL211, 0x00060004);  /* HDRX_B3 - VIN1_A_D3 */
	WR_MEM_32(PINCNTL212, 0x00060004);  /* HDRX_B4 - VIN1_A_D4 */
	WR_MEM_32(PINCNTL213, 0x00060004);  /* HDRX_B5 - VIN1_A_D5 */
	WR_MEM_32(PINCNTL214, 0x00060004);  /* HDRX_B6 - VIN1_A_D6 */
	WR_MEM_32(PINCNTL231, 0x00060004);  /* HDRX_B7 - VIN1_A_D7 */
	WR_MEM_32(PINCNTL215, 0x00060004);  /* HDRX_G0 - VIN1_A_D8  */
	WR_MEM_32(PINCNTL216, 0x00060004);  /* HDRX_G1 - VIN1_A_D9  */
	WR_MEM_32(PINCNTL217, 0x00060004);  /* HDRX_G2 - VIN1_A_D10 */
	WR_MEM_32(PINCNTL218, 0x00060004);  /* HDRX_G3 - VIN1_A_D11 */
	WR_MEM_32(PINCNTL219, 0x00060004);  /* HDRX_G4 - VIN1_A_D12 */
	WR_MEM_32(PINCNTL220, 0x00060004);  /* HDRX_G5 - VIN1_A_D13 */
	WR_MEM_32(PINCNTL221, 0x00060004);  /* HDRX_G6 - VIN1_A_D14 */
	WR_MEM_32(PINCNTL222, 0x00060004);  /* HDRX_G7 - VIN1_A_D15 */
	WR_MEM_32(PINCNTL223, 0x00060004);  /* HDRX_R0 - VIN1_A_D16 */
	WR_MEM_32(PINCNTL224, 0x00060004);  /* HDRX_R0 - VIN1_A_D17 */
	WR_MEM_32(PINCNTL225, 0x00060004);  /* HDRX_R0 - VIN1_A_D18 */
	WR_MEM_32(PINCNTL226, 0x00060004);  /* HDRX_R0 - VIN1_A_D19 */
	WR_MEM_32(PINCNTL227, 0x00060004);  /* HDRX_R0 - VIN1_A_D20 */
	WR_MEM_32(PINCNTL228, 0x00060004);  /* HDRX_R0 - VIN1_A_D21 */
	WR_MEM_32(PINCNTL229, 0x00060004);  /* HDRX_R0 - VIN1_A_D22 */
	WR_MEM_32(PINCNTL230, 0x00060004);  /* HDRX_R0 - VIN1_A_D23 */
    VidOut0PinConfig();
    Vid0CapturePinMuxConfig();    
    HdvpssClkEnable();
    Enable_dvo_hdmi_clk_dss_level();
	
	GEL_TextOut("\t ============================================= \n");
	GEL_TextOut("\t HDMI RX: PinMux Done....... \n");
	GEL_TextOut("\t ============================================= \n");
}


hotmenu VCONF_TVP7002Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for TVP7002 test...***** \n");
	
	// Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	HdvpssClkEnable();
	
    // Configure the I2C0 module to use the IOEXP_SEL_TVP_S0 & IOEXP_SEL_TVP_S1 lines
	I2C0Enable();
    
	// Configure the I2C2 module
	I2C2Enable();
    
	// Configure the IOMUX for VIN0 lines
	Vid0CapturePinMuxConfig();
	
	Enable_dvo_hdmi_clk_dss_level();
	
	GEL_TextOut("\t ***** TVP7002 configured....***** \n");
}


menuitem "Video Camera Application Board Initialization"
hotmenu VCAM_AIC3106 ()
{
    GEL_TextOut("Starting the AIC3106 configuration for Video Camera...\r\n");
    Aic3106_BaseBoard_Setup();
    I2C2Enable ();
    
    WR_MEM_32(PINCNTL55, 0x00060001);  /* MCA5_ACLKX */
    WR_MEM_32(PINCNTL56, 0x00060001);  /* MCA5_AFSX */
    WR_MEM_32(PINCNTL57, 0x00020001);  /* MCA5_AXR0 */
    WR_MEM_32(PINCNTL58, 0x00060001);  /* MCA5_AXR1 */

 //   WR_MEM_32(CM_ALWON_MCA_345_CLKSTCTL, 0x02);	//writing this memory creates a problem in PG2.1 
	GEL_TextOut("\t ***** CM_ALWON_MCA_345_CLKSTCTL....***** \n");
	while(RD_MEM_32(CM_ALWON_MCA_345_CLKSTCTL)!=0x2);
    GEL_TextOut("******Completed VCAM_AIC3106 Initialization ********* \n");
}

hotmenu VCAM_KeypadPinConf()
{
	//PLL_CLOCKS_Config();
	GEL_TextOut("\t ***** Now Enable the PinMux Settings for Keypad Test....***** \n");
	
	GEL_TextOut("\t Settings the PinMux for GPIO.....\n");
	WR_MEM_32(PINCNTL39, 0x00000080);  /* GPI0 10 */
	WR_MEM_32(PINCNTL40, 0x00000080);  /* GPI0 11 */
	WR_MEM_32(PINCNTL41, 0x00000080);  /* GPI0 12 */
	WR_MEM_32(PINCNTL42, 0x00000080);  /* GPI0 13 */
	
	WR_MEM_32(PINCNTL45, 0x00040080);  /* GPI0 16 */
	WR_MEM_32(PINCNTL46, 0x00040080);  /* GPI0 17 */
	WR_MEM_32(PINCNTL47, 0x00040080);  /* GPI0 18 */
	WR_MEM_32(PINCNTL48, 0x00040080);  /* GPI0 19 */
	WR_MEM_32(PINCNTL49, 0x00040080);  /* GPI0 20 */
	
	WR_MEM_32(PINCNTL62, 0x00040080);  /* GPI1 07 */
	WR_MEM_32(PINCNTL63, 0x00040080);  /* GPI1 08 */
	WR_MEM_32(PINCNTL64, 0x00040080);  /* GPI1 09 */

	WR_MEM_32(PINCNTL109, 0x00040080);  /* GPI1 15 */
	WR_MEM_32(PINCNTL108, 0x00040080);  /* GPI1 14 */
	WR_MEM_32(PINCNTL107, 0x00040080);  /* GPI1 13 */

	WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		/* Enable GPI0 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);		/* Poll till Module is functional*/

	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/
	
	I2C0Enable();
	GEL_TextOut("\t ***** KeyPad GPIO Bank is initialized....***** \n");
}

hotmenu VCAM_Ethernet_Init()
{
    //PLL_CLOCKS_Config();
    I2C0Enable ();
    I2C2Enable ();
    Ethernet_PinMux_Setup();
}

hotmenu VCAM_AIC3101_Config ()
{
    GEL_TextOut("Started the VCAM AIC3101 configuration ...\r\n");
    Aic3106_BaseBoard_Setup();
    I2C2Enable ();
    GEL_TextOut("Setting the McASP1 Pin mux control ...\r\n");
    WR_MEM_32(PINCNTL31, 0x00060001);  /* MCA1-ACLKX */
    WR_MEM_32(PINCNTL32, 0x00060001);  /* MCA1- FSX*/
    WR_MEM_32(PINCNTL33, 0x00060001);  /* MCA1- CLKR */
    WR_MEM_32(PINCNTL34, 0x00060001);  /* MCA1- FSR */
    WR_MEM_32(PINCNTL35, 0x00060001);  /* MCA1- AXR0  */
    WR_MEM_32(PINCNTL36, 0x00060001);  /* MCA1- AXR1 */
    WR_MEM_32(PINCNTL37, 0x00060001);  /* MCA1- AXR2 */
    WR_MEM_32(PINCNTL38, 0x00060001);  /* MCA1- AXR3 */
    
    GEL_TextOut("Enabling the Always on Clock...\r\n");
	WR_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL,    0x2); /*Enable McASP1 Clock*/
	while(RD_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
    
    GEL_TextOut("Completed the VCAM AIC3101 Configuration...\r\n");
}

hotmenu VCAM_WLAN_Init()
{
	//PLL_CLOCKS_Config();

	GEL_TextOut("\t Setting Up Functional Clocks for wlan \n");	

	/* SD/SDIO Pins */
	WR_MEM_32(PINCNTL8,  0x00050001);  
	WR_MEM_32(PINCNTL9,  0x00060001);  
	WR_MEM_32(PINCNTL10, 0x00060001);  
	WR_MEM_32(PINCNTL11, 0x00060001);  
	WR_MEM_32(PINCNTL12, 0x00060001);  	
	WR_MEM_32(PINCNTL13, 0x00060001); 				

	WR_MEM_32(PINCNTL110, 0x00000080); /* WLAN Enable GPIO */


	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/

	WR_MEM_32(CM_ALWON_MMC_HS_0_CLKSTCTRL,    0x2); /* SD0 Functional Clock Enable */
	while(RD_MEM_32(CM_ALWON_MMC_HS_0_CLKSTCTRL)!=0x2);	/*Poll for Module is functional*/

	GEL_TextOut("\t Wlan Functional Clocks setup \n");

}

hotmenu VCAM_BT_Config()
{
	UWORD32 mcbsp_uart_clksrc;	

	//PLL_CLOCKS_Config();
	WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		/* Enable GPI0 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);		/* Poll till Module is functional*/

	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/
	
	I2C0Enable();
	I2C2Enable();
	
	UARTClkEnable();
	//DDR2_Initialization();

	GEL_TextOut("\t Setting Up Mux Pins... \n");	
	WR_MEM_32(PINCNTL74, 0x40002); /* Pulldown Rx */
	WR_MEM_32(PINCNTL75, 0x00002); /* Pulldown Tx */
	WR_MEM_32(PINCNTL76, 0x40002); /* CTS -- Input Pin - pulldown */
	WR_MEM_32(PINCNTL77, 0x00002); /* RTS -- Output Pin - pulldown*/

	WR_MEM_32(PINCNTL131, 0x20080); /* BT EN */

	GEL_TextOut("\t Finished Setting Up Mux Pins... \n");

	GEL_TextOut("\t Configuring UART3 Clock to run at 48MHZ \n");
	mcbsp_uart_clksrc = RD_MEM_32(0x481C52D8);
	mcbsp_uart_clksrc = mcbsp_uart_clksrc & ~0x18; 
	mcbsp_uart_clksrc = mcbsp_uart_clksrc | 0x08; /* uart3 = 48 MHZ */
	WR_MEM_32(0x481C52D8, mcbsp_uart_clksrc);
	

	GEL_TextOut("\t BT Configurations Complete \n");	
	
}

hotmenu C_VIDEO_1_PLL_Config_33_5()
{
	UWORD32 OSC_SOURCE = VIDE0_1_OSC_SRC;
	UWORD32 rd_osc_src;
	rd_osc_src = RD_MEM_32(OSC_SRC_CTRL);
	if(OSC_SOURCE == OSC_0){
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffdffff)|0x0);		// d was f gwc
	}
	else{
       WR_MEM_32(OSC_SRC_CTRL,(rd_osc_src & 0xfffdffff)|0x20000);
	}

    GEL_TextOut("\tDM814X VIDEO_1_PLL Init is in Progress, Please wait .....\n","Output",1,1,1);
    PLL_Clocks_Config(VIDEO_1_PLL_BASE,OSC_SOURCE,19,335,10,ADPLLJ_CLKCRTL_HS2);
    GEL_TextOut("\tDM814X VIDEO_1_PLL Init is Done \n","Output",1,1,1);
    GEL_TextOut("\tDM814X VIDEO1_PLL is initialized to 33.5MHz \n","Output",1,1,1); 
}

hotmenu VCAM_Lcd_Init()
{
	GEL_TextOut("\t Setting up configurations for LCD module\n");
    IVAHD0ClkEnable();
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
    //DDR2_Initialization();
    I2C0Enable ();
    I2C2Enable ();
    VidOut0PinConfig();
    HdvpssClkEnable();
    C_VIDEO_1_PLL_Config_33_5();
    Enable_dvo_hdmi_clk_dss_level();
    GEL_TextOut("\t Completed settings for LCD Module\n");
}

hotmenu VCAM_PCF8575_I2C0_Init()
{
    GEL_TextOut("\t Initialising I2C0 for PCF8575 on VCAM Board\n");
	//PLL_CLOCKS_Config();
	//DDR2_Initialization();
    I2C0Enable();
	GEL_TextOut("\t Completed initialisation of I2C0 for PCF8575 on VCAM Board\n");
}

hotmenu VCAM_PCA9518_I2C_Hub_Init()
{
    GEL_TextOut("\t Initialising configuration for PCA9518 I2C Hub test on VCAM Board\n");
	
	//PLL_CLOCKS_Config();
	//DDR2_Initialization();
    I2C0Enable();
    I2C2Enable();
	
	// Enable MCASP0 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL, 0x2);				// Enable MCASP0 Clock
    while(RD_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL) != 0x2);		// Poll for MCASP0 Module Clock is functional
	// Enable GPIO1 & GPIO2 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	// No register for GPIO2 clock in PRCM Module
	
	WR_MEM_32(PINCNTL30, 0x00010001);	/* MCA0_AXR9 */ 	// Receiver disabled, no pull up/down enabled, Function 1 selected
	WR_MEM_32(PINCNTL141, 0x00010080);	/* GP1[12] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	WR_MEM_32(PINCNTL105, 0x00010080);	/* GP2[5] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	WR_MEM_32(PINCNTL106, 0x00010080);	/* GP2[6] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	
	GEL_TextOut("\t Completed configuration for PCA9518 I2C Hub test on VCAM Board\n");
}

hotmenu VCAM_Ocular_Touch_Init()
{
	GEL_TextOut("\t Initialising configuration for Ocular TouchScreen test on VCAM Board\n");
	
	//PLL_CLOCKS_Config();
	//DDR2_Initialization();
	
	I2C0Enable();
    I2C2Enable();
	
	// Enable MCASP0 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL, 0x2);				// Enable MCASP0 Clock
    while(RD_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL) != 0x2);		// Poll for MCASP0 Module Clock is functional
	// Enable GPIO1 & GPIO2 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	// No register for GPIO2 clock in PRCM Module, It uses GPIO1 clock register
	
	WR_MEM_32(PINCNTL30, 0x00010001);	/* MCA0_AXR9 */ 	// Receiver disabled, no pull up/down enabled, Function 1 selected
	WR_MEM_32(PINCNTL141, 0x00010080);	/* GP1[12] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	WR_MEM_32(PINCNTL105, 0x00010080);	/* GP2[5] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	WR_MEM_32(PINCNTL106, 0x00010080);	/* GP2[6] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	
	GEL_TextOut("\t Completed configuration for Ocular TouchScreen test on VCAM Board\n");
}

hotmenu VCAM_SAMSUNG_LCD_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for SAMSUNG LCD Display test...***** \n");
    
    // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	HdvpssClkEnable();
	
	C_VIDEO_1_PLL_Config_33_5();
	
	Enable_dvo_hdmi_clk_dss_level();
	
	// Enable GPIO2 Clock in PRCM Module
	// No register for GPIO2 clock in PRCM Module, It uses GPIO1 clock register
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	
	// Configure LCD_BL_EN (GP2[9])
	WR_MEM_32(PINCNTL144, 0x00010080);	/* GP2[9] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	
	// Configure the IOMUX for VOUT0 lines
	VidOut0PinConfig();
	
    GEL_TextOut("\t ***** Initialisation for SAMSUNG LCD Display test is completed....***** \n");
}

hotmenu VCAM_SAMSUNG_LCD_Backlight_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for SAMSUNG LCD Backlight test...***** \n");
    
   // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	HdvpssClkEnable();
	
	C_VIDEO_1_PLL_Config_33_5();
	
	Enable_dvo_hdmi_clk_dss_level();
	
	WR_MEM_32(CM_TIMER7_CLKSEL, 0x1);	// Timer7 Clock: External 32 kHz clock
	
	// Enable GPIO2 Clock in PRCM Module
	// No register for GPIO2 clock in PRCM Module, It uses GPIO1 clock register
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	
	// Configure LCD_BL_EN (GP2[9])
	WR_MEM_32(PINCNTL144, 0x00010080);	/* GP2[9] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	
	// Enable Timer7 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_TIMER_7_CLKCTRL, 0x2);				// Enable Timer7 Clock
	while(RD_MEM_32(CM_ALWON_TIMER_7_CLKCTRL) != 0x2);		// Poll for Timer7 Module Clock is functional
	
	// Configure SAM_PWM_LCD (TIM7_IO)
	WR_MEM_32(PINCNTL116, 0x00010040);	/* Timer7_Mux2 */	// Receiver disabled, no pull up/down enabled, Function 7 selected
	
	// Configure the IOMUX for VOUT0 lines
	VidOut0PinConfig();
	
	GEL_TextOut("\t ***** Initialisation for SAMSUNG LCD Backlight test is completed....***** \n");
}

menuitem "Video Vision Application Board Initialization"

hotmenu VV_DCAN_Init ()
{
    /* Initialize the Base board Processor */
    //PLL_CLOCKS_Config();
    
    /* Setup the pin mux for DCAN0 */
    WR_MEM_32(PINCNTL68, 0x00060001);  /* DCAN0-TX */
    WR_MEM_32(PINCNTL69, 0x00060001);  /* DCAN0-RX */
    WR_MEM_32(PINCNTL72, 0x00060008);  /* DCAN1-TX */
    WR_MEM_32(PINCNTL73, 0x00060008);  /* DCAN1-RX */
    
    /* Enable the Always on clock for DCAN */
	WR_MEM_32(CM_ALWON_DCAN_0_CLKCTRL,    0x2); 		/* Enable GPI0 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_DCAN_0_CLKCTRL)!=0x2);		/* Poll till Module is functional*/
    GEL_TextOut("\t ***** DCAN Initialization done on Video Vision board....***** \n");
}

hotmenu VV_NOR_flash()
{

    GEL_TextOut("\t ***** Initialising  NOR flash....***** \n");	 	
		 	   
    //PLL_CLOCKS_Config();
    //DDR2_Initialization();
    I2C2Enable();
    GEL_TextOut("\tEnabling Clock for GPMC is in Progress, Please wait.....  \n","Output",1,1,1);
    WR_MEM_32(CM_ALWON_GPMC_CLKCTRL,    0x2); //Enable GPMC Clock
    while(RD_MEM_32(CM_ALWON_GPMC_CLKCTRL)!=0x2);
    GEL_TextOut("\tGPMC Clock is Active\n","Output",1,1,1);
	  
    WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		
    while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);
    
    WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		// Enable GPI1 System and Functional Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		// Poll till Module is functional
    

    WR_MEM_32(PINCNTL89, 0x00010001); //GPMC_D[0]
    WR_MEM_32(PINCNTL90, 0x00010001); //GPMC_D[1]
    WR_MEM_32(PINCNTL91, 0x00010001); //GPMC_D[2]
    WR_MEM_32(PINCNTL92, 0x00010001); //GPMC_D[3]
    WR_MEM_32(PINCNTL93, 0x00010001); //GPMC_D[4]
    WR_MEM_32(PINCNTL94, 0x00010001); //GPMC_D[5]
    WR_MEM_32(PINCNTL95, 0x00010001); //GPMC_D[6]
    WR_MEM_32(PINCNTL96, 0x00010001); //GPMC_D[7]
    WR_MEM_32(PINCNTL97, 0x00010001); //GPMC_D[8]
    WR_MEM_32(PINCNTL98, 0x00010001); //GPMC_D[9]
    WR_MEM_32(PINCNTL99, 0x00010001); //GPMC_D[10]
    WR_MEM_32(PINCNTL100, 0x00010001); //GPMC_D[11]
    WR_MEM_32(PINCNTL102, 0x00010001); //GPMC_D[12]
    WR_MEM_32(PINCNTL102, 0x00010001); //GPMC_D[13]
    WR_MEM_32(PINCNTL103, 0x00010001); //GPMC_D[14]
    WR_MEM_32(PINCNTL104, 0x00010001); //GPMC_D[15]
     
    WR_MEM_32(PINCNTL235,    RD_MEM_32(PINCNTL235) | 0x1);     
    WR_MEM_32(PINCNTL117, 0x00010002); //GPMC_A[1]
    WR_MEM_32(PINCNTL118, 0x00010002); //GPMC_A[2]
    WR_MEM_32(PINCNTL119, 0x00010002); //GPMC_A[3] 
    WR_MEM_32(PINCNTL120, 0x00010002); //GPMC_A[4]
    WR_MEM_32(PINCNTL168, 0x00010010); //GPMC_A[5]
    WR_MEM_32(PINCNTL169, 0x00010010); //GPMC_A[6]
    WR_MEM_32(PINCNTL170, 0x00010010); //GPMC_A[7]
    WR_MEM_32(PINCNTL171, 0x00010010); //GPMC_A[8]
    WR_MEM_32(PINCNTL172, 0x00010010); //GPMC_A[9]
    WR_MEM_32(PINCNTL173, 0x00010010); //GPMC_A[10]
    WR_MEM_32(PINCNTL174, 0x00010010); //GPMC_A[11]
    WR_MEM_32(PINCNTL175, 0x00010010); //GPMC_A[12]
    WR_MEM_32(PINCNTL228, 0x00010002); //GPMC_A[13]
    WR_MEM_32(PINCNTL229, 0x00010002); //GPMC_A[14]
    WR_MEM_32(PINCNTL230, 0x00010002); //GPMC_A[15]
    
    WR_MEM_32(PINCNTL105, 0x00010001); //GPMC_A[16]
    WR_MEM_32(PINCNTL106, 0x00010001); //GPMC_A[17]
    WR_MEM_32(PINCNTL107, 0x00010001); //GPMC_A[18]
    WR_MEM_32(PINCNTL108, 0x00010001); //GPMC_A[19]
    WR_MEM_32(PINCNTL109, 0x00010001); //GPMC_A[20]
    WR_MEM_32(PINCNTL110, 0x00010001); //GPMC_A[21]
    WR_MEM_32(PINCNTL111, 0x00010001); //GPMC_A[22] 
    WR_MEM_32(PINCNTL112, 0x00010001); //GPMC_A[23] 
	
    WR_MEM_32(PINCNTL124, 0x00010002); //GPMC_A[24]
    WR_MEM_32(PINCNTL123,  0x00010002); //GPMC_A[25]
    WR_MEM_32(PINCNTL116,  0x00000080); //GPMC_A[27]

    WR_MEM_32(PINCNTL122,    RD_MEM_32(PINCNTL122) | 0x01);                      //gpmc_CS0
    WR_MEM_32(PINCNTL125,    RD_MEM_32(PINCNTL125) | 0x01);                      //gpmc_CS3
    WR_MEM_32(PINCNTL126,    RD_MEM_32(PINCNTL126) | 0x01);                      //gpmc_CS4
    WR_MEM_32(PINCNTL127,    RD_MEM_32(PINCNTL127) | 0x01);                      //gpmc_clk
    WR_MEM_32(PINCNTL128,    RD_MEM_32(PINCNTL128) | 0x01);                      //gpmc_advn_ale
    WR_MEM_32(PINCNTL129,    RD_MEM_32(PINCNTL129) | 0x01);                      //gpmc_oen_ren
    WR_MEM_32(PINCNTL130,    RD_MEM_32(PINCNTL130) | 0x01);                      //gpmc_wen
    WR_MEM_32(PINCNTL131,    RD_MEM_32(PINCNTL131) | 0x01);                      //gpmc_ben[0]
    WR_MEM_32(PINCNTL132,    RD_MEM_32(PINCNTL132) | 0x01);                      //gpmc_ben[1]
    WR_MEM_32(PINCNTL133,    RD_MEM_32(PINCNTL133) | 0x01);                      //gpmc_wait0
    
    WR_MEM_32(PINCNTL115,  0x00020080); //NOR_EN
	             
    GEL_TextOut("\t ***** GPMC initialised for Nor flash....***** \n");	 		
} 

hotmenu VV_TVP5158Audio()
{
    GEL_TextOut("Starting the TVP5158 Audio Configuration...\r\n");
    Aic3106_BaseBoard_Setup();
    I2C2Enable ();
    
    WR_MEM_32(PINCNTL17, 0x00060001);  /* MCA0-ACLKX */
    WR_MEM_32(PINCNTL18, 0x00060001);  /* MCA0- FSX*/
    WR_MEM_32(PINCNTL19, 0x00060001);  /* MCA0- CLKR */
    WR_MEM_32(PINCNTL20, 0x00060001);  /* MCA0- FSR */
    WR_MEM_32(PINCNTL21, 0x00060001);  /* MCA0- AXR0  */
    WR_MEM_32(PINCNTL22, 0x00060001);  /* MCA0- AXR1 */
    WR_MEM_32(PINCNTL23, 0x00060001);  /* MCA0- AXR2 */
    WR_MEM_32(PINCNTL24, 0x00060001);  /* MCA0- AXR3 */
    WR_MEM_32(PINCNTL25, 0x00060001);  /* MCA0- AXR4 */
    WR_MEM_32(PINCNTL26, 0x00060001);  /* MCA0- AXR5 */
    WR_MEM_32(PINCNTL27, 0x00060001);  /* MCA0- AXR6 */
    WR_MEM_32(PINCNTL28, 0x00060001);  /* MCA0- AXR7 */
    WR_MEM_32(PINCNTL29, 0x00060001);  /* MCA0- AXR8 */
    WR_MEM_32(PINCNTL30, 0x00060001);  /* MCA0- AXR9 */
    
    
	WR_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL,    0x2); /*Enable McASP0 Clock*/
	while(RD_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
    
    GEL_TextOut("Completed the TVP5158 Audio Configuration...\r\n");
}

hotmenu VV_Tvp5158VideoConfig()
{
    Tvp5158VideoConfig();
}

menuitem "IO Expansion Application Board Initialization"

hotmenu IOEXP_SPDIF_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for S/PDIF test...***** \n");
    
    // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	// Enable MCASP1 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL, 0x2);				// Enable MCASP1 Clock
    while(RD_MEM_32(CM_ALWON_MCA_1_CLKSTCTRL) != 0x2);		// Poll for MCASP1 Module Clock is functional
	
    // Configure the I2C2 module to use the IOEXP_SPDIF_SEL line
	I2C2Enable();
    
	// Configure the MCA1_AXR2 pin - Receiver disabled, no pull up/down enabled, Function 1(MCASP1 AXR[2]) selected
	WR_MEM_32(PINCNTL37, 0x00010001);	/* MCA1 - AXR2 */
	
	GEL_TextOut("\t ***** S/PDIF is initialized....***** \n");
}

hotmenu IOEXP_DCAN_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for DCAN0 and DCAN1 test...***** \n");
    
    // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	// Enable DCAN Clock in PRCM Module
	WR_MEM_32(CM_ALWON_DCAN_0_1_CLKCTRL, 0x2);				// Enable DCAN0 and DCAN1 Clock
	while(RD_MEM_32(CM_ALWON_DCAN_0_1_CLKCTRL) != 0x2);		// Poll for DCAN0 and DCAN1 Module Clock is functional
	
	// Enable GPIO1 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	
	// Configure the DCAN pins
	WR_MEM_32(PINCNTL68, 0x00010001);	/*DCAN0_TX */ 	// Receiver disabled, no pull up/down enabled, Function 1 selected	// Try 0x00060001
	WR_MEM_32(PINCNTL69, 0x00050001);	/*DCAN0_RX */ 	// Receiver enabled, no pull up/down enabled, Function 1 selected	// Try 0x00060001
	
	WR_MEM_32(PINCNTL72, 0x00010008);	/*DCAN1_TX */ 	// Receiver disabled, no pull up/down enabled, Function 4 selected	// Try 0x00060008
	WR_MEM_32(PINCNTL73, 0x00050008);	/*DCAN1_RX */ 	// Receiver enabled, no pull up/down enabled, Function 4 selected	// Try 0x00060008
	
	WR_MEM_32(PINCNTL126, 0x00010080);	/* GP1[8] */ 	// Receiver disabled, no pull up/down enabled, Function 8 selected
	
    GEL_TextOut("\t ***** DCAN0 and DCAN1 are initialized....***** \n");
}

hotmenu IOEXP_NOR_Flash_Setup()
{
    GEL_TextOut("\t ***** Initialising  NOR flash....***** \n");	 	
		 	   
    //PLL_CLOCKS_Config();
    //DDR2_Initialization();
    I2C2Enable();

	I2C0Enable();
    GEL_TextOut("\tEnabling Clock for GPMC is in Progress, Please wait.....  \n","Output",1,1,1);
    WR_MEM_32(CM_ALWON_GPMC_CLKCTRL,    0x2); //Enable GPMC Clock
    while(RD_MEM_32(CM_ALWON_GPMC_CLKCTRL)!=0x2);
    GEL_TextOut("\tGPMC Clock is Active\n","Output",1,1,1);
	  
    WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		
    while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);
    
    WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		// Enable GPI1 System and Functional Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		// Poll till Module is functional
    

    WR_MEM_32(PINCNTL89, 0x00010001); //GPMC_D[0]
    WR_MEM_32(PINCNTL90, 0x00010001); //GPMC_D[1]
    WR_MEM_32(PINCNTL91, 0x00010001); //GPMC_D[2]
    WR_MEM_32(PINCNTL92, 0x00010001); //GPMC_D[3]
    WR_MEM_32(PINCNTL93, 0x00010001); //GPMC_D[4]
    WR_MEM_32(PINCNTL94, 0x00010001); //GPMC_D[5]
    WR_MEM_32(PINCNTL95, 0x00010001); //GPMC_D[6]
    WR_MEM_32(PINCNTL96, 0x00010001); //GPMC_D[7]
    WR_MEM_32(PINCNTL97, 0x00010001); //GPMC_D[8]
    WR_MEM_32(PINCNTL98, 0x00010001); //GPMC_D[9]
    WR_MEM_32(PINCNTL99, 0x00010001); //GPMC_D[10]
    WR_MEM_32(PINCNTL100, 0x00010001); //GPMC_D[11]
    WR_MEM_32(PINCNTL102, 0x00010001); //GPMC_D[12]
    WR_MEM_32(PINCNTL102, 0x00010001); //GPMC_D[13]
    WR_MEM_32(PINCNTL103, 0x00010001); //GPMC_D[14]
    WR_MEM_32(PINCNTL104, 0x00010001); //GPMC_D[15]
     
	WR_MEM_32(PINCNTL235, RD_MEM_32(PINCNTL235) | 0x1);     
    WR_MEM_32(PINCNTL117, 0x00010002); //GPMC_A[1]
    WR_MEM_32(PINCNTL118, 0x00010002); //GPMC_A[2]
    WR_MEM_32(PINCNTL119, 0x00010002); //GPMC_A[3] 
    WR_MEM_32(PINCNTL120, 0x00010002); //GPMC_A[4]
    WR_MEM_32(PINCNTL168, 0x00010010); //GPMC_A[5]
    WR_MEM_32(PINCNTL169, 0x00010010); //GPMC_A[6]
    WR_MEM_32(PINCNTL170, 0x00010010); //GPMC_A[7]
    WR_MEM_32(PINCNTL171, 0x00010010); //GPMC_A[8]
    WR_MEM_32(PINCNTL172, 0x00010010); //GPMC_A[9]
    WR_MEM_32(PINCNTL173, 0x00010010); //GPMC_A[10]
    WR_MEM_32(PINCNTL174, 0x00010010); //GPMC_A[11]
    WR_MEM_32(PINCNTL175, 0x00010010); //GPMC_A[12]
    WR_MEM_32(PINCNTL228, 0x00010002); //GPMC_A[13]
    WR_MEM_32(PINCNTL229, 0x00010002); //GPMC_A[14]
    WR_MEM_32(PINCNTL230, 0x00010002); //GPMC_A[15]
    
    WR_MEM_32(PINCNTL105, 0x00010001); //GPMC_A[16]
    WR_MEM_32(PINCNTL106, 0x00010001); //GPMC_A[17]
    WR_MEM_32(PINCNTL107, 0x00010001); //GPMC_A[18]
    WR_MEM_32(PINCNTL108, 0x00010001); //GPMC_A[19]
    WR_MEM_32(PINCNTL109, 0x00010001); //GPMC_A[20]
    WR_MEM_32(PINCNTL110, 0x00010001); //GPMC_A[21]
    WR_MEM_32(PINCNTL111, 0x00010001); //GPMC_A[22] 
    WR_MEM_32(PINCNTL112, 0x00010001); //GPMC_A[23] 
	
    WR_MEM_32(PINCNTL124, 0x00010002); //GPMC_A[24]
    WR_MEM_32(PINCNTL123,  0x00010002); //GPMC_A[25]
    WR_MEM_32(PINCNTL116,  0x00000080); //GPMC_A[27]

    WR_MEM_32(PINCNTL122,    RD_MEM_32(PINCNTL122) | 0x01);                      //gpmc_CS0
    WR_MEM_32(PINCNTL125,    RD_MEM_32(PINCNTL125) | 0x01);                      //gpmc_CS3
    WR_MEM_32(PINCNTL126,    RD_MEM_32(PINCNTL126) | 0x01);                      //gpmc_CS4
    WR_MEM_32(PINCNTL127,    RD_MEM_32(PINCNTL127) | 0x01);                      //gpmc_clk
    WR_MEM_32(PINCNTL128,    RD_MEM_32(PINCNTL128) | 0x01);                      //gpmc_advn_ale
    WR_MEM_32(PINCNTL129,    RD_MEM_32(PINCNTL129) | 0x01);                      //gpmc_oen_ren
    WR_MEM_32(PINCNTL130,    RD_MEM_32(PINCNTL130) | 0x01);                      //gpmc_wen
    WR_MEM_32(PINCNTL131,    RD_MEM_32(PINCNTL131) | 0x01);                      //gpmc_ben[0]
    WR_MEM_32(PINCNTL132,    RD_MEM_32(PINCNTL132) | 0x01);                      //gpmc_ben[1]
    WR_MEM_32(PINCNTL133,    RD_MEM_32(PINCNTL133) | 0x01);                      //gpmc_wait0

	             
    GEL_TextOut("\t ***** GPMC initialised for Nor flash....***** \n");	 
}

hotmenu IOEXP_Accelerometer_Setup()
{
    GEL_TextOut("\t ***** Gel initialization for Accelerometer....***** \n");
	
	//PLL_CLOCKS_Config();	
    WR_MEM_32(PINCNTL85, 0x00040001);     //SPI_CS CS=0 -->SPI Enabled so SPI_CS pulled low
    WR_MEM_32(PINCNTL86, 0x00060001);     //SPI_CLK
    WR_MEM_32(PINCNTL87, 0x00020001);     //SPI_D1
    WR_MEM_32(PINCNTL88, 0x00060001);     //SPI_DO
    
    WR_MEM_32(CM_ALWON_SPI_0_CLKSTCTRL,    0x2); /*Enable SPI_1 Clock*/
	while(RD_MEM_32(CM_ALWON_SPI_0_CLKSTCTRL)!=0x2);		/*Poll for Module is functional*/
	
    GEL_TextOut("\t ***** Gel initialization completed ....***** \n"); 
}

hotmenu IOEXP_UART0_Setup()
{
	GEL_TextOut("\t ***** Initialising UART for IO Expansion....***** \n");
	//PLL_CLOCKS_Config();
	I2C0Enable();
	UARTClkEnable();
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/
	WR_MEM_32(PINCNTL126, 0x00040080);  /* GPI1 8 */                
	WR_MEM_32(PINCNTL125, 0x00060080);  /* GPI1 26 */
	GEL_TextOut("\t ***** Completed UART Intialisation...***** \n");
}

hotmenu IOEXP_TVP5147_VideoConfig()
{
	GEL_TextOut("\t ============================================= \n");
	GEL_TextOut("\t PinMux Settings for TVP5147 capture Test.... \n");
	GEL_TextOut("\t ============================================= \n");
    IVAHD0ClkEnable();    
	//PLL_CLOCKS_Config();
    DucatiClkEnable();
	//DDR2_Initialization();
	I2C0Enable();
	I2C2Enable();

	GEL_TextOut("\t tvp5147: SYNC and CLK PinMux.... \n");
	WR_MEM_32(PINCNTL204, 0x00060004);  /* VIN1_A_HSYNC */
	WR_MEM_32(PINCNTL205, 0x00060004);  /* VIN1_A_VSYNC */
	WR_MEM_32(PINCNTL206, 0x00060008);  /* VIN1_A_FLD */
	WR_MEM_32(PINCNTL207, 0x00060004);  /* VIN1_A_CLK */
	
	GEL_TextOut("\t tvp5147: Data Line PinMux.... \n");
	WR_MEM_32(PINCNTL208, 0x00060004);  /* tvp5147_C0 - VIN1_A_D0 */
	WR_MEM_32(PINCNTL209, 0x00060004);  /* tvp5147_C1 - VIN1_A_D1 */
	WR_MEM_32(PINCNTL210, 0x00060004);  /* tvp5147_C2 - VIN1_A_D2 */
	WR_MEM_32(PINCNTL211, 0x00060004);  /* tvp5147_C3 - VIN1_A_D3 */
	WR_MEM_32(PINCNTL212, 0x00060004);  /* tvp5147_C4 - VIN1_A_D4 */
	WR_MEM_32(PINCNTL213, 0x00060004);  /* tvp5147_C5 - VIN1_A_D5 */
	WR_MEM_32(PINCNTL214, 0x00060004);  /* tvp5147_C6 - VIN1_A_D6 */
	WR_MEM_32(PINCNTL231, 0x00060004);  /* tvp5147_C7 - VIN1_A_D7 */
	WR_MEM_32(PINCNTL215, 0x00060004);  /* tvp5147_Y0 - VIN1_A_D8  */
	WR_MEM_32(PINCNTL216, 0x00060004);  /* tvp5147_Y1 - VIN1_A_D9  */
	WR_MEM_32(PINCNTL217, 0x00060004);  /* tvp5147_Y2 - VIN1_A_D10 */
	WR_MEM_32(PINCNTL218, 0x00060004);  /* tvp5147_Y3 - VIN1_A_D11 */
	WR_MEM_32(PINCNTL219, 0x00060004);  /* tvp5147_Y4 - VIN1_A_D12 */
	WR_MEM_32(PINCNTL220, 0x00060004);  /* tvp5147_Y5 - VIN1_A_D13 */
	WR_MEM_32(PINCNTL221, 0x00060004);  /* tvp5147_Y6 - VIN1_A_D14 */
	WR_MEM_32(PINCNTL222, 0x00060004);  /* tvp5147_Y7 - VIN1_A_D15 */
	WR_MEM_32(PINCNTL223, 0x00060004);  /* VIN1_A_D16 */
	WR_MEM_32(PINCNTL224, 0x00060004);  /* VIN1_A_D17 */
	WR_MEM_32(PINCNTL225, 0x00060004);  /* VIN1_A_D18 */
	WR_MEM_32(PINCNTL226, 0x00060004);  /* VIN1_A_D19 */
	WR_MEM_32(PINCNTL227, 0x00060004);  /* VIN1_A_D20 */
	WR_MEM_32(PINCNTL228, 0x00060004);  /* VIN1_A_D21 */
	WR_MEM_32(PINCNTL229, 0x00060004);  /* VIN1_A_D22 */
	WR_MEM_32(PINCNTL230, 0x00060004);  /* VIN1_A_D23 */

    HdvpssClkEnable();
    Enable_dvo_hdmi_clk_dss_level();
	GEL_TextOut("\t ========================================================= \n");
	GEL_TextOut("\t ***** PinMux Done for Tvp5147 Video capture Test....***** \n");
	GEL_TextOut("\t ========================================================= \n");
}

hotmenu IOEXP_TVP7002_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for TVP7002 test...***** \n");
	
	// Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	HdvpssClkEnable();
	
    // Configure the I2C0 module to use the IOEXP_SEL_TVP_S0 & IOEXP_SEL_TVP_S1 lines
	I2C0Enable();
    
	// Configure the I2C2 module
	I2C2Enable();
    
	// Configure the IOMUX for VIN0 lines
	Vid0CapturePinMuxConfig();
	
	Enable_dvo_hdmi_clk_dss_level();
	
	GEL_TextOut("\t ***** TVP7002 configured....***** \n");
}

hotmenu IOEXP_DVI_Receiver_Setup()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for DVI Receiver test...***** \n");
    
    // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	// Enable VIN0 module clock in PRCM
	HdvpssClkEnable();
	
	// Configure the I2C0 module to use the IOEXP_SEL_TVP_S0 & IOEXP_SEL_TVP_S1 lines
	I2C0Enable();
    
	// Configure the I2C2 module
	I2C2Enable();
	
	// Configure the IOMUX for VIN0 lines
	Vid0CapturePinMuxConfig();
	
	Enable_dvo_hdmi_clk_dss_level();
	
    GEL_TextOut("\t ***** DVI Receiver is initialized....***** \n");
}

hotmenu IOEXP_WLAN_Init()
{
	//PLL_CLOCKS_Config();

	GEL_TextOut("\t Setting Up Functional Clocks for wlan \n");	

	/* SD/SDIO Pins */
	WR_MEM_32(PINCNTL8,  0x00050001);
//	WR_MEM_32(PINCNTL8,  0x00020001);    
	WR_MEM_32(PINCNTL9,  0x00060001);  
	WR_MEM_32(PINCNTL10, 0x00060001);  
	WR_MEM_32(PINCNTL11, 0x00060001);  
	WR_MEM_32(PINCNTL12, 0x00060001);  	
	WR_MEM_32(PINCNTL13, 0x00060001); 				

	WR_MEM_32(PINCNTL121, 0x00000080); /* WLAN EN */


	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/

	WR_MEM_32(CM_ALWON_MMC_HS_0_CLKSTCTRL,    0x2); /* SD0 Functional Clock Enable */
	while(RD_MEM_32(CM_ALWON_MMC_HS_0_CLKSTCTRL)!=0x2);	/*Poll for Module is functional*/

	GEL_TextOut("\t Wlan Functional Clocks setup \n");

}

hotmenu IOEXP_BT_Config()
{
	UWORD32 mcbsp_uart_clksrc;	

	//PLL_CLOCKS_Config();
	WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL,    0x2); 		/* Enable GPI0 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2);		/* Poll till Module is functional*/

	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL,    0x2); 		/* Enable GPI1 System and Functional Clock*/
	while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2);		/* Poll till Module is functional*/
	
	I2C0Enable();
	I2C2Enable();
	UARTClkEnable();
	//DDR2_Initialization();

	GEL_TextOut("\t Setting Up Mux Pins... \n");	
	WR_MEM_32(PINCNTL74, 0x40002); /* Pulldown Rx */
	WR_MEM_32(PINCNTL75, 0x00002); /* Pulldown Tx */
	WR_MEM_32(PINCNTL76, 0x40002); /* CTS -- Input Pin - pulldown */
	WR_MEM_32(PINCNTL77, 0x00002); /* RTS -- Output Pin - pulldown*/

	WR_MEM_32(PINCNTL115, 0x20080); /* BT EN */

	GEL_TextOut("\t Finished Setting Up Mux Pins... \n");

	GEL_TextOut("\t Configuring UART3 Clock to run at 48MHZ \n");
	mcbsp_uart_clksrc = RD_MEM_32(0x481C52D8);
	mcbsp_uart_clksrc = mcbsp_uart_clksrc & ~0x18; 
	mcbsp_uart_clksrc = mcbsp_uart_clksrc | 0x08; /* uart3 = 48 MHZ */
	WR_MEM_32(0x481C52D8, mcbsp_uart_clksrc);
	

	GEL_TextOut("\t BT Configurations Complete \n");	
	
}

hotmenu IOEXP_LCD_interposer_Backlight()
{
	GEL_TextOut("\t ***** This GEL function Initializes the board for LCD Interposer backlight test...***** \n");
    
    // Configure PLL Clock
	//PLL_CLOCKS_Config();
	
	IVAHD0ClkEnable();
    DucatiClkEnable();
	//DDR2_Initialization();
	
	I2C2Enable();
	GEL_TextOut("\t I2C2 initialized.... \n");
	I2C0Enable();
	
	GEL_TextOut("\t I2C0 is Initialized.... \n");
	UARTClkEnable();
	
	HdvpssClkEnable();
	
	C_VIDEO_1_PLL_Config_33_5();
	
	Enable_dvo_hdmi_clk_dss_level();
	
	
	// Configure the IOMUX for VOUT0 lines
	VidOut0PinConfig();
	
    GEL_TextOut("\t ***** Initialisation for  LCD Interposer Backlight test is completed....***** \n");
}

hotmenu IOEXP_LCD_Interposer_Touch_Init()
{
	GEL_TextOut("\t Initialising configuration for Ocular TouchScreen test on VCAM Board\n");
	
	//PLL_CLOCKS_Config();
	//DDR2_Initialization();
	
	I2C0Enable();
    I2C2Enable();
	
	// Enable MCASP0 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL, 0x2);				// Enable MCASP0 Clock
    while(RD_MEM_32(CM_ALWON_MCA_0_CLKSTCTRL) != 0x2);		// Poll for MCASP0 Module Clock is functional
    
   	WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL, 0x2);				// Enable GP0 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL) != 0x2);		// Poll for GP0 Module Clock is functional
    
	// Enable GPIO1 & GPIO2 Clock in PRCM Module
	WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2);				// Enable GP1 Clock
    while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL) != 0x2);		// Poll for GP1 Module Clock is functional
	// No register for GPIO2 clock in PRCM Module, It uses GPIO1 clock register
	
	//WR_MEM_32(PINCNTL30, 0x00010001);	/* MCA0_AXR9 */ 	// Receiver disabled, no pull up/down enabled, Function 1 selected
	//WR_MEM_32(PINCNTL141, 0x00010080);	/* GP1[12] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	//WR_MEM_32(PINCNTL105, 0x00010080);	/* GP2[5] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected
	//WR_MEM_32(PINCNTL106, 0x00010080);	/* GP2[6] */ 		// Receiver disabled, no pull up/down enabled, Function 8 selected

	WR_MEM_32(PINCNTL61, 0x00070080);	/* GP0[31] */ 		// Receiver Enabled, no pull up/down enabled, Function 8 selected
	
	GEL_TextOut("\t Completed configuration for LCD_Interposer TouchScreen test on IOEXP Board\n");
}


menuitem "PG 2.x DM814X"

#define    DDR_FREQ		 666 // 333MHz

int CLKIN =	20; 
hotmenu ALL_ADPLL_CLOCKS_ENABLE_API()
{
        GEL_TextOut("\t ****  DM814X2 ALL ADPLL INIT IS In Progress ......... \n","Output",1,1,1);	
        PLL_SETUP();
        //DDR2_EMIF0_EMIF1_Config();	
        emac_clkenable();
        GEL_TextOut("\t ****  DM814X2 ALL ADPLL INIT IS  Done ************** \n","Output",1,1,1);	
}

int HSMODE,CLKOUT = 0;

DCOCLK_COMP(int CLKIN,int N, int M)
 {
	 	int DCOCLK;
		DCOCLK = (CLKIN/(N+1))*M;
		
		if(DCOCLK >= 500 && DCOCLK < 1000){
				HSMODE = 2;  //HS2 Mode 
		}
		else if(DCOCLK >= 1000 && DCOCLK < 2000){
				HSMODE = 1;  //HS1 Mode
		}
		else HSMODE = 0;  //wrong configuration
		
		//return HSMODE;
 }

PLL_SETUP()
{
    //pll_name (CLKINP,N , M, M2);
    cmdMPUPLL(CLKIN,1, 60 ,1);
    cmdL3PLL(CLKIN,19,800,4);
    cmdDSPPLL(CLKIN,19, 500, 1);
    cmdDSSPLL(CLKIN,19, 800, 4);
    cmdISSPLL(CLKIN,19, 800 ,4);
    cmdIVAPLL(CLKIN,19, 532, 2);
    cmdSGXPLL(CLKIN,19, 800, 4);
    cmdUSBPLL(CLKIN,19,960,5);
    cmdVIDEO0PLL(CLKIN,19, 1000,4);
    cmdVIDEO1PLL(CLKIN,19, 594,4);
    cmdHDMIPLL(CLKIN,19, 1485,10);

    cmdDDRPLL(CLKIN,19,DDR_FREQ, 2);

    cmdAUDIOPLL(CLKIN,19,800,4);

    cmdSATAPLL();

    //cmdPCIEPLL();
    GEL_TextOut("exiting pll setup \n\r");
}


PG2_PLL_Clocks_Config(UWORD32 Base_Address,UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2,UWORD32 CLKCTRL_VAL)
{
    UWORD32 m2nval,mn2val,read_clkctrl,clk_out,ref_clk,clkout_dco = 0;
    m2nval = (M2<<16) | N;
    mn2val =  M;
	ref_clk     = CLKIN/(N+1);
    clkout_dco  = ref_clk*M;
    clk_out     = clkout_dco/M2;
    WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)|0x00800000);
	while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000101) != 0x00000101);
    WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)& 0xfffffffe);
	wait_delay(3);
	WR_MEM_32((Base_Address+M2NDIV    ),m2nval);
	WR_MEM_32((Base_Address+MN2DIV    ),mn2val);
	wait_delay(3);
	WR_MEM_32((Base_Address+TENABLEDIV),0x1);
	wait_delay(3);
	WR_MEM_32((Base_Address+TENABLEDIV),0x0);
	wait_delay(3);
	WR_MEM_32((Base_Address+TENABLE   ),0x1);
	wait_delay(3);
	WR_MEM_32((Base_Address+TENABLE   ),0x0);
	wait_delay(3);
	read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
	//configure the TINITZ(bit0) and CLKDCO BITS IF REQUIRED
	WR_MEM_32(Base_Address+CLKCTRL,(read_clkctrl & 0xff7fe3ff) | CLKCTRL_VAL);
	read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
	// poll for the freq,phase lock to occur
	while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000600) != 0x00000600);
	//wait fot the clocks to get stabized
	wait_delay(10);
    CLKOUT    = clk_out;
}

PG2_MODENA_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
    UWORD32 rval_ctrl,ref_clk,clk_out = 0;
    UWORD32 m2nval,mn2val = 0;
	ref_clk     = CLKIN/(N+1);
    clk_out     = (ref_clk*M)/M2;

	m2nval = (M2<<16) | N; //need to check the bit position of M2
    mn2val =  M;
    WR_MEM_32(MODENAPLL_M2NDIV      ,m2nval);         
    WR_MEM_32(MODENAPLL_MN2DIV      ,mn2val);        
	WR_MEM_32(MODENAPLL_TENABLEDIV  ,0x1);  
	wait_delay(3);
    WR_MEM_32(MODENAPLL_TENABLEDIV  ,0x0);
	wait_delay(3);
    WR_MEM_32(MODENAPLL_TENABLE     ,0x1);
	wait_delay(3);
    WR_MEM_32(MODENAPLL_TENABLE     ,0x0);
	wait_delay(3);
    rval_ctrl = RD_MEM_32(MODENAPLL_CLKCTRL);
    WR_MEM_32(MODENAPLL_CLKCTRL,(rval_ctrl & 0xff7fffff) | 0x1);
    while (( (RD_MEM_32(MODENAPLL_STATUS)) & 0x00000600) != 0x00000600);
	wait_delay(10);
	CLKOUT = clk_out;
	
}
cmdMPUPLL(int CLKIN,int N, int M, int M2)
{
    PG2_MODENA_PLL_Config(CLKIN,N,M,M2);
      GEL_TextOut("\t MODENA ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
}
cmdL3PLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2)
        { 
        PG2_PLL_Clocks_Config(L3_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
        GEL_TextOut("\t L3  ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
    else if (HSMODE == 1)
        {
        PG2_PLL_Clocks_Config(L3_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
        GEL_TextOut("\t L3  ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
        }
    else 
        {
        GEL_TextOut("\t L3 PLL NOT Configured.Wrong DCOCLK Output\n");
        }
}
cmdDSPPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(DSP_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
           GEL_TextOut("\t DSP ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(DSP_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
          GEL_TextOut("\t DSP ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else{
              GEL_TextOut("\t DSP PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
cmdDSSPLL(int CLKIN, int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(DSS_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
           GEL_TextOut("\t DSS ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(DSS_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
           GEL_TextOut("\t DSS ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t DSS PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
	
cmdSGXPLL(int CLKIN, int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(SGX_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
           GEL_TextOut("\t SGX ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(SGX_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t SGX ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t SGX PLL NOT Configured.Wrong DCOCLK Output\n");
    }
	
}
cmdIVAPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(IVA_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t IVA ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(IVA_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t IVA ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t IVA PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
cmdISSPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(ISS_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t ISS ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(ISS_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t ISS ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t ISS PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
cmdUSBPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(USB_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2+ADPLLJ_CLKCRTL_CLKDCO); 
         GEL_TextOut("\t USB ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(USB_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1+ADPLLJ_CLKCRTL_CLKDCO); 
         GEL_TextOut("\t USB ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t USB PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
cmdVIDEO0PLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(VIDEO_0_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t VIDEO-0 ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(VIDEO_0_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t VIDEO-0 ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t VIDEO-0 PLL NOT Configured.Wrong DCOCLK Output\n");
    }
	
}
cmdVIDEO1PLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(VIDEO_1_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t VIDEO-1 ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(VIDEO_1_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t VIDEO-1 ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t VIDEO-1 PLL NOT Configured.Wrong DCOCLK Output\n");
    }
}

cmdHDMIPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(HDMI_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2+ADPLLJ_CLKCRTL_CLKDCO); 
         GEL_TextOut("\t VIDEO-2/HDMI ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(HDMI_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1+ADPLLJ_CLKCRTL_CLKDCO); 
         GEL_TextOut("\t VIDEO-2/HDMI ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t VIDEO-2/HDMI PLL NOT Configured.Wrong DCOCLK Output\n");
    }
}
cmdDDRPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(DDR_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t DDR ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(DDR_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t DDR ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t DDR PLL NOT Configured.Wrong DCOCLK Output\n");
    }
}
cmdAUDIOPLL(int CLKIN,int N, int M, int M2)
{
    DCOCLK_COMP(CLKIN,N,M);
    if(HSMODE == 2){  
        PG2_PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS2); 
         GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else if (HSMODE == 1){
        PG2_PLL_Clocks_Config(AUDIO_PLL_BASE,CLKIN,N,M,M2,ADPLLJ_CLKCRTL_HS1); 
         GEL_TextOut("\t AUDIO ADPLLJ CLKOUT  value is  = %d \n",,,,,CLKOUT);
    }
    else {
              GEL_TextOut("\t AUDIO PLL NOT Configured.Wrong DCOCLK Output\n");
    }

}
//PLL program sequence to get 125Mhz ethernet clockout.
cmdSATAPLL()
{
  GEL_TextOut("\t **** SATA PLL INIT IS In Progress Please wait ..... \n","Output",1,1,1);
  WR_MEM_32(SATA_PLLCFG0, 0x00000004);	//cfgpll0
  wait_delay(35);
  WR_MEM_32(SATA_PLLCFG1, 0xC12C003C);	//cfgpll1
  WR_MEM_32(SATA_PLLCFG3, 0x004008E0);	//cfgpll3
  wait_delay(850);
   //wait for bias to be stable --50us
  WR_MEM_32(SATA_PLLCFG0, 0x00000014);	//cfgpll0
  wait_delay(850);
  WR_MEM_32(SATA_PLLCFG0, 0x00000016);	//cfgpll0
  wait_delay(60);
  WR_MEM_32(SATA_PLLCFG0, 0xC0000016);	//cfgpll0 -----why 2 times???????
  wait_delay(2000);
  WR_MEM_32(SATA_PLLCFG0, 0xC0000017);	//cfgpll0
 //poll the status field to check if pll lock occured.
  while ((RD_MEM_32(SATA_PLLSTATUS) & 0x1) != 0x1);
  
  WR_MEM_32(CM_ALWON2_SATA_CLKCTRL,    0x2); /*Enable SATA Clock*/
  while((RD_MEM_32(CM_ALWON2_SATA_CLKCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
	
   WR_MEM_32(CM_ALWON2_L3_MED_CLKSTCTRL,    0x2); /*Enable SATA Clock*/
   while((RD_MEM_32(CM_ALWON2_L3_MED_CLKSTCTRL) & 0x103) != 0x102);		/*Poll for Module is functional*/
GEL_TextOut("\t **** SATA PLL INIT IS In DONE ***************** \n","Output",1,1,1);

}
//pci express pll sequence
cmdPCIEPLL(){
    GEL_TextOut("\t **** PCIE PLL INIT IS In Progress Please wait ..... \n","Output",1,1,1);
    WR_MEM_32(SERDES_REFCLK_CTL,0x00000002); //PowerDown 0x00000000-DM814X1
    WR_MEM_32(PCIE_PLLCFG0,0x00000000); //cfgpll0
    WR_MEM_32(PCIE_PLLCFG1,0x00640000); //cfgpll1
    WR_MEM_32(PCIE_PLLCFG2,0x00000000); //cfgpll2
    WR_MEM_32(PCIE_PLLCFG3,0x004008E0); //cfgpll3
    WR_MEM_32(PCIE_PLLCFG4,0x0000609C); //cfgpll4
    
	//WR_MEM_32(0x48141318,0x00000E7B); //pcie_serdes_cfg_misc DM814X2 commented
    wait_delay(3); // Wait 100 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000004); //Config PLL CFG0 bit [2] - ENBGSC_REF
    wait_delay(3); // Wait 250 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000014); //Config PLL CFG0 bit [4] - DIGLDO
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x00000016); //Config PLL CFG0 bit [1] - ENPLLLDO
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x30000016); // Configure proxy TXLDO and RXLDO enables (DM814X ECO 3/30/10)
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x70007016); // Configure multiplier
    wait_delay(3); // Wait 200 ns
    WR_MEM_32(PCIE_PLLCFG0,0x70007017);  // Enable PLL
	wait_delay(3); // Wait 200 ns
     //poll the status field to check if pll lock occured.
    while ((RD_MEM_32(PCIE_PLLSTATUS) & 0x1 )!= 0x1);
    GEL_TextOut("\t **** PCIE PLL INIT IS In DONE ***************** \n","Output",1,1,1);
}



emac_clkenable()
{
   GEL_TextOut("CONFIGURE PRCM CLOCKS of EMAC in progress \n\r");
   *((unsigned int*)(0x48181404)) = 0x2;
   *((unsigned int*)(0x481815d4)) = 0x2;
     while(RD_MEM_32(0x48181404)!=0x0302);
     while(RD_MEM_32(0x481815d4)!=0x2);
   GEL_TextOut("PRCM CLOCKS of EMAC  is complete \n\r");

}

hotmenu RMII_PinMux_Setup()
{
    GEL_TextOut("\t ***** Configuring RGMII Clk and Mux....***** \n");	 									
    WR_MEM_32(GMII_SELECT, 0x0000030A);
	/* PIN MUX for EMAC0 */
	
	WR_MEM_32(PINCNTL232, 0x00040001);  
	WR_MEM_32(PINCNTL233, 0x000A0001);  
	WR_MEM_32(PINCNTL234, 0x000E0001);   
	
	WR_MEM_32(PINCNTL235, 0x000C0001);  
	WR_MEM_32(PINCNTL236, 0x000C0001);  
	WR_MEM_32(PINCNTL237, 0x000C0001); 
	WR_MEM_32(PINCNTL238, 0x000C0001);  
	WR_MEM_32(PINCNTL239, 0x00040001);  
	WR_MEM_32(PINCNTL240, 0x00040001); 
	WR_MEM_32(PINCNTL241, 0x00040001);  
	WR_MEM_32(PINCNTL242, 0x00040001);  
	WR_MEM_32(PINCNTL243, 0x00040001); 
	WR_MEM_32(PINCNTL244, 0x00040001);  
	WR_MEM_32(PINCNTL245, 0x00040001);  
	WR_MEM_32(PINCNTL246, 0x00040001); 
    WR_MEM_32(PINCNTL247, 0x00040001); 
	WR_MEM_32(PINCNTL248, 0x00040001);
	WR_MEM_32(PINCNTL249, 0x00000001);
	WR_MEM_32(PINCNTL250, 0x00000001);
	WR_MEM_32(PINCNTL251, 0x00000001);
	WR_MEM_32(PINCNTL252, 0x00000001);  	
	WR_MEM_32(PINCNTL253, 0x00000001);  	
	WR_MEM_32(PINCNTL254, 0x00000001);  	
	WR_MEM_32(PINCNTL255, 0x00000001); 
	WR_MEM_32(PINCNTL256, 0x00000001);  	
	WR_MEM_32(PINCNTL257, 0x00000001);  	
	WR_MEM_32(PINCNTL258, 0x00000001); 
	GEL_TextOut("\t ***** Configuring RGMII Clk and Mux complete....***** \n");
  
}

PADCFG_Enable_GMII()
{
       GEL_TextOut("****** PADCFG IS IN PROGRESS ........ \n\r");
	WR_MEM_32(GMII_SELECT, 0x0000030A);

 
      WR_MEM_DATA(PINCNTL204, ( RD_MEM_DATA(PINCNTL204) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL205,   ( RD_MEM_DATA(PINCNTL205) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL206, ( RD_MEM_DATA(PINCNTL206) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL207,   ( RD_MEM_DATA(PINCNTL207) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL208, ( RD_MEM_DATA(PINCNTL208) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL209,   ( RD_MEM_DATA(PINCNTL209) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL210, ( RD_MEM_DATA(PINCNTL210) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL211,   ( RD_MEM_DATA(PINCNTL211) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL212, ( RD_MEM_DATA(PINCNTL212) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL213,   ( RD_MEM_DATA(PINCNTL213) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL214, ( RD_MEM_DATA(PINCNTL214) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL215,   ( RD_MEM_DATA(PINCNTL215) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL216, ( RD_MEM_DATA(PINCNTL216) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL217,   ( RD_MEM_DATA(PINCNTL217) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL218, ( RD_MEM_DATA(PINCNTL218) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL219,   ( RD_MEM_DATA(PINCNTL219) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL220, ( RD_MEM_DATA(PINCNTL220) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL221,   ( RD_MEM_DATA(PINCNTL221) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL222, ( RD_MEM_DATA(PINCNTL222) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL223,   ( RD_MEM_DATA(PINCNTL223) &0xffffff00 ) | 0x2); 
      WR_MEM_DATA(PINCNTL224, ( RD_MEM_DATA(PINCNTL224) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL225,   ( RD_MEM_DATA(PINCNTL225) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL226,   ( RD_MEM_DATA(PINCNTL226) &0xffffff00 ) | 0x2); 
	WR_MEM_DATA(PINCNTL227,   ( RD_MEM_DATA(PINCNTL227) &0xffffff00 ) | 0x2); 


  WR_MEM_DATA(PINCNTL232, ( RD_MEM_DATA(PINCNTL232) &0xffffff00)| 0x1); 
  WR_MEM_DATA(PINCNTL233, ( RD_MEM_DATA(PINCNTL233) &0xffffff00)| 0x1); 
  WR_MEM_DATA(PINCNTL234, ( RD_MEM_DATA(PINCNTL234) &0xffffff00)| 0x1); 

      WR_MEM_DATA(PINCNTL235, ( RD_MEM_DATA(PINCNTL235) &0xffffff00)| 0x1); 
	WR_MEM_DATA(PINCNTL236,   ( RD_MEM_DATA(PINCNTL236)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL237, ( RD_MEM_DATA(PINCNTL237)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL238,   ( RD_MEM_DATA(PINCNTL238)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL239, ( RD_MEM_DATA(PINCNTL239)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL240,   ( RD_MEM_DATA(PINCNTL240)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL241, ( RD_MEM_DATA(PINCNTL241)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL242,   ( RD_MEM_DATA(PINCNTL242)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL243, ( RD_MEM_DATA(PINCNTL243)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL244,   ( RD_MEM_DATA(PINCNTL244)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL245, ( RD_MEM_DATA(PINCNTL245)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL246,   ( RD_MEM_DATA(PINCNTL246)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL247, ( RD_MEM_DATA(PINCNTL247)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL248,   ( RD_MEM_DATA(PINCNTL248)  & 0xffffff00) | 0x1); 
     /*
      WR_MEM_DATA(PINCNTL249, ( RD_MEM_DATA(PINCNTL249)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL250,   ( RD_MEM_DATA(PINCNTL250)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL251, ( RD_MEM_DATA(PINCNTL251)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL252,   ( RD_MEM_DATA(PINCNTL252)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL253, ( RD_MEM_DATA(PINCNTL253)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL254,   ( RD_MEM_DATA(PINCNTL254)  & 0xffffff00) | 0x1); 
      WR_MEM_DATA(PINCNTL255, ( RD_MEM_DATA(PINCNTL255)& 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL256,   ( RD_MEM_DATA(PINCNTL256)  & 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL257,   ( RD_MEM_DATA(PINCNTL257)  & 0xffffff00) | 0x1); 
	WR_MEM_DATA(PINCNTL258,   ( RD_MEM_DATA(PINCNTL258)  & 0xffffff00) | 0x1); 
     */
    WR_MEM_DATA(PINCNTL249, ( RD_MEM_DATA(PINCNTL249)& 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL250,   ( RD_MEM_DATA(PINCNTL250)  & 0xfff00000) | 0x1); 
      WR_MEM_DATA(PINCNTL251, ( RD_MEM_DATA(PINCNTL251)& 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL252,   ( RD_MEM_DATA(PINCNTL252)  & 0xfff00000) | 0x1); 
      WR_MEM_DATA(PINCNTL253, ( RD_MEM_DATA(PINCNTL253)& 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL254,   ( RD_MEM_DATA(PINCNTL254)  & 0xfff00000) | 0x1); 
      WR_MEM_DATA(PINCNTL255, ( RD_MEM_DATA(PINCNTL255)& 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL256,   ( RD_MEM_DATA(PINCNTL256)  & 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL257,   ( RD_MEM_DATA(PINCNTL257)  & 0xfff00000) | 0x1); 
	WR_MEM_DATA(PINCNTL258,   ( RD_MEM_DATA(PINCNTL258)  & 0xfff00000) | 0x1); 
     
     GEL_TextOut("****** PADCFG IS  COMPLETED  ******** \n\r");
     
     
     GEL_TextOut("CONFIGURE PRCM CLOCKS of EMAC in progress \n\r");
   *((unsigned int*)(0x48181404)) = 0x2;
   *((unsigned int*)(0x481815d4)) = 0x2;
WR_MEM_32(MC_ALWON_ETH_1_CLKSTCTRL,    0x2); /*Enable Ethernet Clock*/
	while((RD_MEM_32(MC_ALWON_ETH_1_CLKSTCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/

   while(RD_MEM_32(0x48181404)!=0x0302);
   while(RD_MEM_32(0x481815d4)!=0x2);
   GEL_TextOut("PRCM CLOCKS of EMAC  is complete \n\r");

}

Emif_PRCM_Clk_Enable()
{
	WR_MEM_32(CM_DEFAULT_FW_CLKCTRL, 0x2); 		  /*Enable the EMIF FireWall Clocks*/
	WR_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL, 0x2); /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
	WR_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL,    0x2); /*Enable EMIF0 Clock*/
	WR_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL,    0x2); /*Enable EMIF1 Clock*/
	WR_MEM_32(CM_DEFAULT_DMM_CLKCTRL,       0x2); /*Enable EMIF1 Clock*/
	while((RD_MEM_32(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300)!=0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_0_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_EMIF_1_CLKCTRL)!=0x2);		/*Poll for Module is functional*/
	while(RD_MEM_32(CM_DEFAULT_DMM_CLKCTRL)!=0x2);			/*Poll for Module is functional*/
}

Vtp_Enable()
{
	// Write 1 to ENABLE bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000040 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000040 ); 

	// Write 0 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) & 0xfffffffe ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) & 0xfffffffe ); 
	
	// Write 1 to CLRZ bit
	WR_MEM_32(VTP0_CTRL_REG, RD_MEM_32(VTP0_CTRL_REG) | 0x00000001 ); 
	WR_MEM_32(VTP1_CTRL_REG, RD_MEM_32(VTP1_CTRL_REG) | 0x00000001 ); 

	// Read VTP control registers & check READY bits
	while( (RD_MEM_32(VTP0_CTRL_REG) & 0x00000020) != 0x20);
	while( (RD_MEM_32(VTP1_CTRL_REG) & 0x00000020) != 0x20);
}

Emif0_MMR_Config(UWORD32 read_latency,UWORD32 tim1,UWORD32 tim2,UWORD32 tim3,UWORD32 ref_ctrl,UWORD32 sdram_config)
{
	/*Program EMIF0 CFG Registers*/
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, read_latency);//RL =11 
	WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, read_latency);//RL =11

	WR_MEM_32(EMIF4_0_SDRAM_TIM_1, tim1);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, tim1);

	WR_MEM_32(EMIF4_0_SDRAM_TIM_2, tim2);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, tim2);

	WR_MEM_32(EMIF4_0_SDRAM_TIM_3, tim3);
	WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, tim3);

	WR_MEM_32(EMIF4_0_SDRAM_CONFIG, sdram_config);// CL = 11, row size= 13 ODT 75 Ohms  0x62833AB2

	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, ref_ctrl); 
	WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, ref_ctrl);
}

Emif1_MMR_Config(UWORD32 read_latency,UWORD32 tim1,UWORD32 tim2,UWORD32 tim3,UWORD32 ref_ctrl,UWORD32 sdram_config)
{
	/*Program EMIF0 CFG Registers*/
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, read_latency);//RL =11 
	WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, read_latency);//RL =11

	WR_MEM_32(EMIF4_1_SDRAM_TIM_1, tim1);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, tim1);

	WR_MEM_32(EMIF4_1_SDRAM_TIM_2, tim2);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, tim2);

	WR_MEM_32(EMIF4_1_SDRAM_TIM_3, tim3);
	WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, tim3);

	WR_MEM_32(EMIF4_1_SDRAM_CONFIG, sdram_config);// CL = 11, row size= 13 ODT 75 Ohms  0x62833AB2

	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, ref_ctrl); 
	WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, ref_ctrl);
}

cmd_DDR3_EMIF0_EMIF1_Config_Full_leveling(UWORD32 ddr3_emif_read_latency_arg,UWORD32 ddr3_emif_tim1_arg,UWORD32 ddr3_emif_tim2_arg,UWORD32 ddr3_emif_tim3_arg,UWORD32 ddr3_emif_ref_ctrl_arg,UWORD32 ddr3_emif_sdram_config_arg)
{
UWORD32 i;

	Emif_PRCM_Clk_Enable();

	//- DDR3_PHY_INVERT_CLKOUT_DEFINE is 1
	WR_MEM_32(CMD0_REG_PHY0_INVERT_CLKOUT_0, DDR3_PHY_INVERT_CLKOUT_DEFINE);
	WR_MEM_32(CMD1_REG_PHY0_INVERT_CLKOUT_0, DDR3_PHY_INVERT_CLKOUT_DEFINE);
	WR_MEM_32(CMD2_REG_PHY0_INVERT_CLKOUT_0, DDR3_PHY_INVERT_CLKOUT_DEFINE);

	Vtp_Enable();

	/*Program the DMM to Access EMIF0 and EMIF1*/
	WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
	WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
	WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
		
	GEL_TextOut("\tBusy reading back DMM registers Please wait ...\n","Output",1,1,1);
	while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
	while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
	while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);
	GEL_TextOut("\tDMM register read successfully  \n","Output",1,1,1);

	WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

	Emif0_MMR_Config(ddr3_emif_read_latency_arg,ddr3_emif_tim1_arg,ddr3_emif_tim2_arg,ddr3_emif_tim3_arg,ddr3_emif_ref_ctrl_arg,ddr3_emif_sdram_config_arg);

	WR_MEM_32(EMIF4_0_RDWR_LVL_RMP_CTRL, 0x80000000); //- Bit 31 = 1;
	WR_MEM_32(EMIF4_0_RDWR_LVL_CTRL, 0x80000000); //- Bit 31 = 1;

	for(i=0;i<50000;i++)
	{
	}

	Emif1_MMR_Config(ddr3_emif_read_latency_arg,ddr3_emif_tim1_arg,ddr3_emif_tim2_arg,ddr3_emif_tim3_arg,ddr3_emif_ref_ctrl_arg,ddr3_emif_sdram_config_arg);

	WR_MEM_32(EMIF4_1_RDWR_LVL_RMP_CTRL, 0x80000000); //- Bit 31 = 1;
	WR_MEM_32(EMIF4_1_RDWR_LVL_CTRL, 0x80000000); //- Bit 31 = 1;

	for(i=0;i<50000;i++)
	{
	}

}

hotmenu DDR3_EMIF0_EMIF1_Config_Full_leveling()
	{
		GEL_TextOut("\t ****  DM814X2 DDR3 Full_leveling EMIF0 and EMIF1 configuration in progress......... \n","Output",1,1,1);		
		cmd_DDR3_EMIF0_EMIF1_Config_Full_leveling(DDR3_EMIF_READ_LATENCY_DEFINE,DDR3_EMIF_TIM1_DEFINE,DDR3_EMIF_TIM2_DEFINE,DDR3_EMIF_TIM3_DEFINE,DDR3_EMIF_REF_CTRL_DEFINE,DDR3_EMIF_SDRAM_CONFIG_DEFINE);
		GEL_TextOut("\t ****  DM814X2 DDR3 Full_leveling EMIF0 and EMIF1 configuration is DONE **** \n","Output",1,1,1);				
	}

hotmenu USB_CLOCK_ENABLE()
	{
		WR_MEM_32(CM_ALWON2_USB_CLKCTRL,    0x2); /*Enable USB Clock*/
		//while((RD_MEM_32(CM_ALWON2_USB_CLKCTRL) & 0x0F) !=0x2);		/*Poll for Module is functional*/
		
		/* USB_PINMUX_Config */ 
		//WR_MEM_32(PINCNTL258, 0x00010001);
		WR_MEM_32(PINCNTL270, 0x00060001);
		WR_MEM_32(PINCNTL14, 0x00060080);
		
		WR_MEM_32(RM_ALWON2_RSTCTRL, 0x9F); /* Disable local reset */
		//while((RD_MEM_32(RM_ALWON2_RSTST) & 0x60) != 0x60);		/*Poll for Module is functional*/
		//WR_MEM_32(RM_ALWON2_RSTST, 0x60); /* Write 1 to Clear */
		
		WR_MEM_32(0x48140620, 0x3C1E64F4); /* PHY INIT */
		WR_MEM_32(0x48140628, 0x3C1E64F4); /* PHY INIT */
		GEL_TextOut("\t*** DM814X USB_PLL Init is Done ***\n ","Output",1,1,1);
	}

