Introduction
-------------
This text document accompanies the DDR3 CCS test case for DM814X EVM. It 
provides a brief of the methodology of the test and the procedure for executing 
the same.

Overview
---------
This CCS test application validates the DDR memory for its ability to perform
write access; read access and data storing ability. The test application writes
a known pattern into the entire memory and then reads back the same. The known
pattern written into the memory is the incremental hexadecimal numbers. After 
writing to the entire memory area, this application reads them back and validates
the data read. If the data read does not match the expected pattern, this test
is declared failed. It is declared pass otherwise.

This test carries out the test on both DDR3[0] as well as DDR3[1] instances of 
memory controller. This test takes 13 to 15 minutes to complete.

Procudure
----------
This test application assumes the DDR controller initialization as well as all
the PLL initialization is already carried out by the GEL scripts. 
	              1. PG 2.x DM814X --> ALL_ADPLL_CLOCKS_ENABLE_API 
				  2. PG 2.x DM814X --> DDR3_EMIF0_EMIF1_Config_Full_leveling

load "BB_021_DDR3_TEST.out" file and run.

	
