/*****************************************************************************/
/* stdlib.h   v16.9.0                                                        */
/*                                                                           */
/* Copyright (c) 1993-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/



#pragma diag_push
#pragma CHECK_MISRA("-6.3") /* standard types required for standard headers */
#pragma CHECK_MISRA("-8.5") /* need to define inline function */
#pragma CHECK_MISRA("-19.1") /* #includes required for implementation */
#pragma CHECK_MISRA("-19.7") /* need function-like macros */
#pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */
#pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */

/*---------------------------------------------------------------------------*/
/* Attributes are only available in relaxed ANSI mode.                       */
/*---------------------------------------------------------------------------*/


/*---------------------------------------------------------------------------*/
/* <cstdlib> IS RECOMMENDED OVER <stdlib.h>.  <stdlib.h> IS PROVIDED FOR     */
/* COMPATIBILITY WITH C AND THIS USAGE IS DEPRECATED IN C++                  */
/*---------------------------------------------------------------------------*/
extern "C" namespace std {

#pragma diag_push
#pragma CHECK_MISRA("-5.7") /* keep names intact */

typedef struct { int quot, rem; } div_t;

typedef struct { long quot, rem; } ldiv_t;

typedef struct { long long quot, rem; } lldiv_t;

#pragma diag_pop



typedef unsigned long size_t;




/*****************************************************************************/
/* linkage.h   v16.9.0                                                        */
/*                                                                           */
/* Copyright (c) 1998-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


#pragma diag_push
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */

/* No modifiers needed to access code */


/*--------------------------------------------------------------------------*/
/* Define _DATA_ACCESS ==> how to access RTS global or static data          */
/*--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------*/
/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space.                */
/*--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------*/
/* Define _IDECL ==> how inline functions are declared                      */
/*--------------------------------------------------------------------------*/

#pragma diag_pop


/*---------------------------------------------------------------*/
/* NOTE - Normally, abs, labs, and fabs are expanded inline, so  */
/*        no formal definition is really required. However, ANSI */
/*        requires that they exist as separate functions, so     */
/*        they are supplied in the library.  The prototype is    */
/*        here mainly for documentation.                         */
/*---------------------------------------------------------------*/
#pragma diag_push
#pragma CHECK_MISRA("-16.4") /* false positives due to builtin declarations */
      int       abs(int _val); 
      long      labs(long _val);
      long long llabs(long long _val);
#pragma diag_pop

     int       atoi(const char *_st);
     long      atol(const char *_st);
     long long atoll(const char *_st);
     int       ltoa(long val, char *buffer);
          static __inline double    atof(const char *_st);

     long      strtol(const char *_st, char **_endptr, int _base);
     unsigned long strtoul(const char *_st, char **_endptr,
    					  int _base);
     long long strtoll(const char *_st, char **_endptr, int _base);
     unsigned long long strtoull(const char *_st, char **_endptr,
					     int _base);
     float     strtof(const char * _st, 
                                  char ** _endptr);
     double    strtod(const char * _st, 
                                  char ** _endptr);
     long double strtold(const char * _st, 
                                     char ** _endptr);
    
     int    rand(void);
     void   srand(unsigned _seed);
    
     void  *calloc(size_t _num, size_t _size)
               __attribute__((malloc));
     void  *malloc(size_t _size)
               __attribute__((malloc));
     void  *realloc(void *_ptr, size_t _size)
               __attribute__((malloc));
     void   free(void *_ptr);
     void  *memalign(size_t _aln, size_t _size)
               __attribute__((malloc));
    
     void   abort(void); 

    typedef void (*__TI_atexit_fn)(void);
     int    atexit(__TI_atexit_fn _func);

    typedef int (*__TI_compar_fn)(const void *_a,const void *_b);
     void  *bsearch(const void *_key, const void *_base,
                                size_t _nmemb, size_t _size, 
                                __TI_compar_fn compar);
     void   qsort(void *_base, size_t _nmemb, size_t _size, 
                              __TI_compar_fn compar);

     void   exit(int _status);
    
     div_t  div(int _numer, int _denom);
     ldiv_t ldiv(long _numer, long _denom);
     lldiv_t lldiv(long long _numer, long long _denom);

     char  *getenv(const char *_string);
     int    system(const char *_name);

     int    mblen(const char *_s, size_t _n);
     size_t mbstowcs(wchar_t *_dest, const char *_src, size_t _n);
     int    mbtowc(wchar_t *_dest, const char *_src, size_t _n);

     size_t wcstombs(char *_dest, const wchar_t *_src, size_t _n);
     int    wctomb(char *_s, wchar_t _wc);

} /* extern "C" namespace std */



namespace std {

static __inline double atof(const char *_st) 
{
  return strtod(_st, (char **)0); 
}

} /* namespace std */



#pragma diag_pop


#pragma diag_push

/* using declarations must occur outside header guard to support including both
   C and C++-wrapped version of header; see _CPP_STYLE_HEADER check */
/* this code is for C++ mode only and thus also not relevant for MISRA */
#pragma CHECK_MISRA("-19.15")

using std::div_t;
using std::ldiv_t;
using std::lldiv_t;
using std::size_t;
using std::abs;
using std::labs;
using std::atoi;
using std::atol;
using std::llabs;
using std::atoll;
using std::atof;
using std::strtol;
using std::strtoul;
using std::strtoll;
using std::strtoull;
using std::strtof;
using std::strtod;
using std::strtold;
using std::rand;
using std::srand;
using std::calloc;
using std::malloc;
using std::realloc;
using std::free;
using std::memalign;
using std::abort;
using std::atexit;
using std::bsearch;
using std::qsort;
using std::exit;
using std::div;
using std::ldiv;
using std::lldiv;
using std::getenv;
using std::system;
using std::mblen;
using std::mbtowc;
using std::wctomb;
using std::mbstowcs;
using std::wcstombs;

#pragma diag_pop

#pragma diag_push

/* C2000-specific additions to header implemented with #include */
#pragma CHECK_MISRA("-19.1")
#pragma CHECK_MISRA("-19.15")

/*****************************************************************************/
/* stdlibf.h   v16.9.0                                                       */
/*     far versions of stdlib.h functions                                    */
/*                                                                           */
/* Copyright (c) 1996-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/

#pragma diag_push
#pragma CHECK_MISRA("-6.3")


namespace std {

extern "C" int	       free_memory(void);
extern "C" int         max_free(void);
extern "C" void        *chkheap(void);
}

#pragma diag_pop


#pragma diag_push

/* using declarations must occur outside header guard to support including both
   C and C++-wrapped version of header; see _CPP_STYLE_HEADER check */
/* this code is for C++ mode only and thus also not relevant for MISRA */
#pragma CHECK_MISRA("-19.15")

using std::free_memory; 
using std::max_free;
using std::chkheap;

#pragma diag_pop

#pragma diag_pop


/*==========================================================*/
/* Title		:	Types.h									*/
/* Description	: 	Data types definition					*/
/* Date			:	Oct.2007								*/
/*==========================================================*/

typedef		signed int			int16;							//变量名加前缀i16_
	typedef		unsigned int		Uint16;							//变量名加前缀u16_
	typedef		signed long			int32;							//变量名加前缀i32_
	typedef		unsigned long		Uint32;							//变量名加前缀u32_



	typedef		signed int			INT16;							//变量名加前缀i16_
	typedef		unsigned int		UINT16;							//变量名加前缀u16_
	typedef		signed long			INT32;							//变量名加前缀i32_
	typedef		unsigned long		UINT32;							//变量名加前缀u32_
	typedef     signed long long    INT64;
	typedef     unsigned long   long    UINT64;
	typedef         float                   FLOAT32;
	typedef         long double         FLOAT64;

	// The following data types are included for compatibility with legacy code,
	// they are not recommended for use in new software.  Please use the C99
	// types included above
	//



	typedef long long			int64;


	typedef unsigned long long	Uint64;
	typedef float           	float32;
	typedef long double     	float64;


	typedef union
	{
		INT32		dword;
		struct
		{
			UINT16 	lword;
			INT16 	hword;
		}			half;
	}UNLONG;														//变量名加前缀un_


																	//;struct的变量名前加st_
																	//;class的变量名前加obj_
																	//;class的内部变量名前加m_

																	//;驱动层的函数名前加Drv_
																	//;数据层的函数名前加Dat_
																	//;算法层的函数名前加Alg_
																	//;应用层的函数名前加App_

typedef struct
{
    int num ;
    int half_gap ;
    int range[10+1];
    int flags[10];
} FLAG_TABLE;



//###########################################################################
//
// FILE:   F2807x_device.h
//
// TITLE:  F2807x Device Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// User To Select Target Device:
//




//---------------------------------------------------------------------------
// Common CPU Definitions:
//
extern __cregister volatile unsigned int IFR;
extern __cregister volatile unsigned int IER;




//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use the C99 Standard integer types
//
/*****************************************************************************/
/* assert.h   v16.9.0                                                        */
/*                                                                           */
/* Copyright (c) 1993-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/




#pragma diag_push
#pragma CHECK_MISRA("-6.3") /* standard types required for standard headers */
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */
#pragma CHECK_MISRA("-19.7") /* macros required for implementation */
#pragma CHECK_MISRA("-19.13") /* # and ## required for implementation */


/*---------------------------------------------------------------------------*/
/* <cassert> IS RECOMMENDED OVER <assert.h>.  <assert.h> IS PROVIDED FOR     */
/* COMPATIBILITY WITH C AND THIS USAGE IS DEPRECATED IN C++                  */
/*---------------------------------------------------------------------------*/


extern "C" namespace std
{

/* this #ifndef can go away when C2000 uses extern C builtins */

extern  void _abort_msg(const char *msg);



} /* extern "C" namespace std */

#pragma diag_pop


#pragma diag_push

/* using declarations must occur outside header guard to support including both
   C and C++-wrapped version of header; see _CPP_STYLE_HEADER check */
/* this code is for C++ mode only and thus also not relevant for MISRA */
#pragma CHECK_MISRA("-19.15")

using std::_nassert;



#pragma diag_pop
/*****************************************************************************/
/* stdarg.h   v16.9.0                                                        */
/*                                                                           */
/* Copyright (c) 1996-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/




#pragma diag_push
#pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */
#pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */
#pragma CHECK_MISRA("-19.7") /* macros required for implementation */
#pragma CHECK_MISRA("-19.10") /* need types as macro arguments */

namespace std {

typedef char *va_list;

} /* namespace std */



/****************************************************************************/
/* RETURN THE NEXT VALUE ON THE STACK ...                                   */
/*                                                                          */
/* (<advance ap>, <access the value>) BECOMES ...                           */
/*                                                                          */
/* ap -= 1 (stack grows toward high addresses)                              */
/* ap -= 1 more if type is long or float                                    */
/* ap -= 1 more if type is long or float and to account for alignment       */
/*       if necessary                                                       */
/*                                                                          */
/* if      (<type is passed by address [struct or union]>) return **ap;     */
/* else if (<type is integer size>)                        return *ap;      */
/*                                                                          */
/* LONG/FLOATS ARE ALWAYS ALIGNED ON AN EVEN WORD BOUNDARY, EVEN WHEN       */
/* PASSED AS PARAMETERS, THUS ap MUST BE ALIGNED FOR THOSE ACCESSES.        */
/****************************************************************************/

#pragma diag_pop


#pragma diag_push

/* using declarations must occur outside header guard to support including both
   C and C++-wrapped version of header; see _CPP_STYLE_HEADER check */
/* this code is for C++ mode only and thus also not relevant for MISRA */
#pragma CHECK_MISRA("-19.15")

using std::va_list;

#pragma diag_pop
/*
 * Copyright (c) 2000 Jeroen Ruigrok van der Werven <asmodai@FreeBSD.org>
 * All rights reserved.
 *
 * Copyright (c) 2014-2014 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $
 */


/*****************************************************************************/
/* stddef.h   v16.9.0                                                        */
/*                                                                           */
/* Copyright (c) 1993-2016 Texas Instruments Incorporated                    */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


#pragma diag_push
#pragma CHECK_MISRA("-19.7") /* macros required for implementation */
#pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */
#pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */

extern "C" namespace std {


typedef long ptrdiff_t;



#pragma diag_push
#pragma CHECK_MISRA("-19.10") /* need types as macro arguments */


} /* extern "C" namespace std */

#pragma diag_pop


using std::ptrdiff_t;
using std::size_t;
/*using std::wchar_t;*/

#pragma diag_push
#pragma CHECK_MISRA("-19.15") /* code outside guard; see below comment */

/*-----------------------------------------------------------------------*/
/* Define _win_t, for compiling GCC libraries with the TI compiler.      */
/* GCC's library (newlib) expects wint_t to be defined here, in stddef.h,*/
/* which is arguably incorrect, but we go along for compatibility.       */
/* This is outside the _STDDEF guard in case this file has already       */
/* been included without __need_wint_t.                                  */
/*-----------------------------------------------------------------------*/

#pragma diag_pop
/*****************************************************************************/
/* STDINT.H v16.9.0                                                          */
/*                                                                           */
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/* 7.18.1.1 Exact-width integer types */

    typedef          int    int16_t;
    typedef unsigned int   uint16_t;
    typedef          long   int32_t;
    typedef unsigned long  uint32_t;


    typedef          long long  int64_t;
    typedef unsigned long long uint64_t;

/* 7.18.1.2 Minimum-width integer types */

    typedef  int16_t  int_least8_t;
    typedef uint16_t uint_least8_t;

    typedef  int16_t  int_least16_t;
    typedef uint16_t uint_least16_t;
    typedef  int32_t  int_least32_t;
    typedef uint32_t uint_least32_t;


    typedef  int64_t  int_least64_t;
    typedef uint64_t uint_least64_t;

/* 7.18.1.3 Fastest minimum-width integer types */

    typedef  int16_t  int_fast8_t;
    typedef uint16_t uint_fast8_t;
    typedef  int16_t  int_fast16_t;
    typedef uint16_t uint_fast16_t;

    typedef  int32_t  int_fast32_t;
    typedef uint32_t uint_fast32_t;


    typedef  int64_t  int_fast64_t;
    typedef uint64_t uint_fast64_t;

/* 7.18.1.4 Integer types capable of holding object pointers */
    typedef          long intptr_t;
    typedef unsigned long uintptr_t;

/* 7.18.1.5 Greatest-width integer types */
    typedef          long long intmax_t;
    typedef unsigned long long uintmax_t;

/* 
   According to footnotes in the 1999 C standard, "C++ implementations
   should define these macros only when __STDC_LIMIT_MACROS is defined
   before <stdint.h> is included." 
*/


// C99 defines boolean type to be _Bool, but this doesn't match the format of
// the other standard integer types.  bool_t has been defined to fill this gap.
//typedef _Bool bool_t;

//used for a bool function return status
//typedef _Bool status_t;



//---------------------------------------------------------------------------


//---------------------------------------------------------------------------
// Include All Peripheral Header Files:
//

//###########################################################################
//
// FILE:    F2807x_adc.h
//
// TITLE:   F2807x Device ADC Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// ADC Individual Register Bit Definitions:

struct ADCCTL1_BITS {                   // bits description
    Uint16 rsvd1:2;                     // 1:0 Reserved
    Uint16 INTPULSEPOS:1;               // 2 ADC Interrupt Pulse Position
    Uint16 rsvd2:4;                     // 6:3 Reserved
    Uint16 ADCPWDNZ:1;                  // 7 ADC Power Down
    Uint16 ADCBSYCHN:4;                 // 11:8 ADC Busy Channel
    Uint16 rsvd3:1;                     // 12 Reserved
    Uint16 ADCBSY:1;                    // 13 ADC Busy
    Uint16 rsvd4:2;                     // 15:14 Reserved
};

union ADCCTL1_REG {
    Uint16  all;
    struct  ADCCTL1_BITS  bit;
};

struct ADCCTL2_BITS {                   // bits description
    Uint16 PRESCALE:4;                  // 3:0 ADC Clock Prescaler
    Uint16 rsvd1:2;                     // 5:4 Reserved
    Uint16 RESOLUTION:1;                // 6 SOC Conversion Resolution
    Uint16 SIGNALMODE:1;                // 7 SOC Signaling Mode
    Uint16 rsvd2:5;                     // 12:8 Reserved
    Uint16 rsvd3:3;                     // 15:13 Reserved
};

union ADCCTL2_REG {
    Uint16  all;
    struct  ADCCTL2_BITS  bit;
};

struct ADCBURSTCTL_BITS {               // bits description
    Uint16 BURSTTRIGSEL:6;              // 5:0 SOC Burst Trigger Source Select
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 BURSTSIZE:4;                 // 11:8 SOC Burst Size Select
    Uint16 rsvd2:3;                     // 14:12 Reserved
    Uint16 BURSTEN:1;                   // 15 SOC Burst Mode Enable
};

union ADCBURSTCTL_REG {
    Uint16  all;
    struct  ADCBURSTCTL_BITS  bit;
};

struct ADCINTFLG_BITS {                 // bits description
    Uint16 ADCINT1:1;                   // 0 ADC Interrupt 1 Flag
    Uint16 ADCINT2:1;                   // 1 ADC Interrupt 2 Flag
    Uint16 ADCINT3:1;                   // 2 ADC Interrupt 3 Flag
    Uint16 ADCINT4:1;                   // 3 ADC Interrupt 4 Flag
    Uint16 rsvd1:12;                    // 15:4 Reserved
};

union ADCINTFLG_REG {
    Uint16  all;
    struct  ADCINTFLG_BITS  bit;
};

struct ADCINTFLGCLR_BITS {              // bits description
    Uint16 ADCINT1:1;                   // 0 ADC Interrupt 1 Flag Clear
    Uint16 ADCINT2:1;                   // 1 ADC Interrupt 2 Flag Clear
    Uint16 ADCINT3:1;                   // 2 ADC Interrupt 3 Flag Clear
    Uint16 ADCINT4:1;                   // 3 ADC Interrupt 4 Flag Clear
    Uint16 rsvd1:12;                    // 15:4 Reserved
};

union ADCINTFLGCLR_REG {
    Uint16  all;
    struct  ADCINTFLGCLR_BITS  bit;
};

struct ADCINTOVF_BITS {                 // bits description
    Uint16 ADCINT1:1;                   // 0 ADC Interrupt 1 Overflow Flags
    Uint16 ADCINT2:1;                   // 1 ADC Interrupt 2 Overflow Flags
    Uint16 ADCINT3:1;                   // 2 ADC Interrupt 3 Overflow Flags
    Uint16 ADCINT4:1;                   // 3 ADC Interrupt 4 Overflow Flags
    Uint16 rsvd1:12;                    // 15:4 Reserved
};

union ADCINTOVF_REG {
    Uint16  all;
    struct  ADCINTOVF_BITS  bit;
};

struct ADCINTOVFCLR_BITS {              // bits description
    Uint16 ADCINT1:1;                   // 0 ADC Interrupt 1 Overflow Clear Bits
    Uint16 ADCINT2:1;                   // 1 ADC Interrupt 2 Overflow Clear Bits
    Uint16 ADCINT3:1;                   // 2 ADC Interrupt 3 Overflow Clear Bits
    Uint16 ADCINT4:1;                   // 3 ADC Interrupt 4 Overflow Clear Bits
    Uint16 rsvd1:12;                    // 15:4 Reserved
};

union ADCINTOVFCLR_REG {
    Uint16  all;
    struct  ADCINTOVFCLR_BITS  bit;
};

struct ADCINTSEL1N2_BITS {              // bits description
    Uint16 INT1SEL:4;                   // 3:0 ADCINT1 EOC Source Select
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 INT1E:1;                     // 5 ADCINT1 Interrupt Enable
    Uint16 INT1CONT:1;                  // 6 ADCINT1 Continuous Mode Enable
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 INT2SEL:4;                   // 11:8 ADCINT2 EOC Source Select
    Uint16 rsvd3:1;                     // 12 Reserved
    Uint16 INT2E:1;                     // 13 ADCINT2 Interrupt Enable
    Uint16 INT2CONT:1;                  // 14 ADCINT2 Continuous Mode Enable
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCINTSEL1N2_REG {
    Uint16  all;
    struct  ADCINTSEL1N2_BITS  bit;
};

struct ADCINTSEL3N4_BITS {              // bits description
    Uint16 INT3SEL:4;                   // 3:0 ADCINT3 EOC Source Select
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 INT3E:1;                     // 5 ADCINT3 Interrupt Enable
    Uint16 INT3CONT:1;                  // 6 ADCINT3 Continuous Mode Enable
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 INT4SEL:4;                   // 11:8 ADCINT4 EOC Source Select
    Uint16 rsvd3:1;                     // 12 Reserved
    Uint16 INT4E:1;                     // 13 ADCINT4 Interrupt Enable
    Uint16 INT4CONT:1;                  // 14 ADCINT4 Continuous Mode Enable
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCINTSEL3N4_REG {
    Uint16  all;
    struct  ADCINTSEL3N4_BITS  bit;
};

struct ADCSOCPRICTL_BITS {              // bits description
    Uint16 SOCPRIORITY:5;               // 4:0 SOC Priority
    Uint16 RRPOINTER:5;                 // 9:5 Round Robin Pointer
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union ADCSOCPRICTL_REG {
    Uint16  all;
    struct  ADCSOCPRICTL_BITS  bit;
};

struct ADCINTSOCSEL1_BITS {             // bits description
    Uint16 SOC0:2;                      // 1:0 SOC0 ADC Interrupt Trigger Select
    Uint16 SOC1:2;                      // 3:2 SOC1 ADC Interrupt Trigger Select
    Uint16 SOC2:2;                      // 5:4 SOC2 ADC Interrupt Trigger Select
    Uint16 SOC3:2;                      // 7:6 SOC3 ADC Interrupt Trigger Select
    Uint16 SOC4:2;                      // 9:8 SOC4 ADC Interrupt Trigger Select
    Uint16 SOC5:2;                      // 11:10 SOC5 ADC Interrupt Trigger Select
    Uint16 SOC6:2;                      // 13:12 SOC6 ADC Interrupt Trigger Select
    Uint16 SOC7:2;                      // 15:14 SOC7 ADC Interrupt Trigger Select
};

union ADCINTSOCSEL1_REG {
    Uint16  all;
    struct  ADCINTSOCSEL1_BITS  bit;
};

struct ADCINTSOCSEL2_BITS {             // bits description
    Uint16 SOC8:2;                      // 1:0 SOC8 ADC Interrupt Trigger Select
    Uint16 SOC9:2;                      // 3:2 SOC9 ADC Interrupt Trigger Select
    Uint16 SOC10:2;                     // 5:4 SOC10 ADC Interrupt Trigger Select
    Uint16 SOC11:2;                     // 7:6 SOC11 ADC Interrupt Trigger Select
    Uint16 SOC12:2;                     // 9:8 SOC12 ADC Interrupt Trigger Select
    Uint16 SOC13:2;                     // 11:10 SOC13 ADC Interrupt Trigger Select
    Uint16 SOC14:2;                     // 13:12 SOC14 ADC Interrupt Trigger Select
    Uint16 SOC15:2;                     // 15:14 SOC15 ADC Interrupt Trigger Select
};

union ADCINTSOCSEL2_REG {
    Uint16  all;
    struct  ADCINTSOCSEL2_BITS  bit;
};

struct ADCSOCFLG1_BITS {                // bits description
    Uint16 SOC0:1;                      // 0 SOC0 Start of Conversion Flag
    Uint16 SOC1:1;                      // 1 SOC1 Start of Conversion Flag
    Uint16 SOC2:1;                      // 2 SOC2 Start of Conversion Flag
    Uint16 SOC3:1;                      // 3 SOC3 Start of Conversion Flag
    Uint16 SOC4:1;                      // 4 SOC4 Start of Conversion Flag
    Uint16 SOC5:1;                      // 5 SOC5 Start of Conversion Flag
    Uint16 SOC6:1;                      // 6 SOC6 Start of Conversion Flag
    Uint16 SOC7:1;                      // 7 SOC7 Start of Conversion Flag
    Uint16 SOC8:1;                      // 8 SOC8 Start of Conversion Flag
    Uint16 SOC9:1;                      // 9 SOC9 Start of Conversion Flag
    Uint16 SOC10:1;                     // 10 SOC10 Start of Conversion Flag
    Uint16 SOC11:1;                     // 11 SOC11 Start of Conversion Flag
    Uint16 SOC12:1;                     // 12 SOC12 Start of Conversion Flag
    Uint16 SOC13:1;                     // 13 SOC13 Start of Conversion Flag
    Uint16 SOC14:1;                     // 14 SOC14 Start of Conversion Flag
    Uint16 SOC15:1;                     // 15 SOC15 Start of Conversion Flag
};

union ADCSOCFLG1_REG {
    Uint16  all;
    struct  ADCSOCFLG1_BITS  bit;
};

struct ADCSOCFRC1_BITS {                // bits description
    Uint16 SOC0:1;                      // 0 SOC0 Force Start of Conversion Bit
    Uint16 SOC1:1;                      // 1 SOC1 Force Start of Conversion Bit
    Uint16 SOC2:1;                      // 2 SOC2 Force Start of Conversion Bit
    Uint16 SOC3:1;                      // 3 SOC3 Force Start of Conversion Bit
    Uint16 SOC4:1;                      // 4 SOC4 Force Start of Conversion Bit
    Uint16 SOC5:1;                      // 5 SOC5 Force Start of Conversion Bit
    Uint16 SOC6:1;                      // 6 SOC6 Force Start of Conversion Bit
    Uint16 SOC7:1;                      // 7 SOC7 Force Start of Conversion Bit
    Uint16 SOC8:1;                      // 8 SOC8 Force Start of Conversion Bit
    Uint16 SOC9:1;                      // 9 SOC9 Force Start of Conversion Bit
    Uint16 SOC10:1;                     // 10 SOC10 Force Start of Conversion Bit
    Uint16 SOC11:1;                     // 11 SOC11 Force Start of Conversion Bit
    Uint16 SOC12:1;                     // 12 SOC12 Force Start of Conversion Bit
    Uint16 SOC13:1;                     // 13 SOC13 Force Start of Conversion Bit
    Uint16 SOC14:1;                     // 14 SOC14 Force Start of Conversion Bit
    Uint16 SOC15:1;                     // 15 SOC15 Force Start of Conversion Bit
};

union ADCSOCFRC1_REG {
    Uint16  all;
    struct  ADCSOCFRC1_BITS  bit;
};

struct ADCSOCOVF1_BITS {                // bits description
    Uint16 SOC0:1;                      // 0 SOC0 Start of Conversion Overflow Flag
    Uint16 SOC1:1;                      // 1 SOC1 Start of Conversion Overflow Flag
    Uint16 SOC2:1;                      // 2 SOC2 Start of Conversion Overflow Flag
    Uint16 SOC3:1;                      // 3 SOC3 Start of Conversion Overflow Flag
    Uint16 SOC4:1;                      // 4 SOC4 Start of Conversion Overflow Flag
    Uint16 SOC5:1;                      // 5 SOC5 Start of Conversion Overflow Flag
    Uint16 SOC6:1;                      // 6 SOC6 Start of Conversion Overflow Flag
    Uint16 SOC7:1;                      // 7 SOC7 Start of Conversion Overflow Flag
    Uint16 SOC8:1;                      // 8 SOC8 Start of Conversion Overflow Flag
    Uint16 SOC9:1;                      // 9 SOC9 Start of Conversion Overflow Flag
    Uint16 SOC10:1;                     // 10 SOC10 Start of Conversion Overflow Flag
    Uint16 SOC11:1;                     // 11 SOC11 Start of Conversion Overflow Flag
    Uint16 SOC12:1;                     // 12 SOC12 Start of Conversion Overflow Flag
    Uint16 SOC13:1;                     // 13 SOC13 Start of Conversion Overflow Flag
    Uint16 SOC14:1;                     // 14 SOC14 Start of Conversion Overflow Flag
    Uint16 SOC15:1;                     // 15 SOC15 Start of Conversion Overflow Flag
};

union ADCSOCOVF1_REG {
    Uint16  all;
    struct  ADCSOCOVF1_BITS  bit;
};

struct ADCSOCOVFCLR1_BITS {             // bits description
    Uint16 SOC0:1;                      // 0 SOC0 Clear Start of Conversion Overflow Bit
    Uint16 SOC1:1;                      // 1 SOC1 Clear Start of Conversion Overflow Bit
    Uint16 SOC2:1;                      // 2 SOC2 Clear Start of Conversion Overflow Bit
    Uint16 SOC3:1;                      // 3 SOC3 Clear Start of Conversion Overflow Bit
    Uint16 SOC4:1;                      // 4 SOC4 Clear Start of Conversion Overflow Bit
    Uint16 SOC5:1;                      // 5 SOC5 Clear Start of Conversion Overflow Bit
    Uint16 SOC6:1;                      // 6 SOC6 Clear Start of Conversion Overflow Bit
    Uint16 SOC7:1;                      // 7 SOC7 Clear Start of Conversion Overflow Bit
    Uint16 SOC8:1;                      // 8 SOC8 Clear Start of Conversion Overflow Bit
    Uint16 SOC9:1;                      // 9 SOC9 Clear Start of Conversion Overflow Bit
    Uint16 SOC10:1;                     // 10 SOC10 Clear Start of Conversion Overflow Bit
    Uint16 SOC11:1;                     // 11 SOC11 Clear Start of Conversion Overflow Bit
    Uint16 SOC12:1;                     // 12 SOC12 Clear Start of Conversion Overflow Bit
    Uint16 SOC13:1;                     // 13 SOC13 Clear Start of Conversion Overflow Bit
    Uint16 SOC14:1;                     // 14 SOC14 Clear Start of Conversion Overflow Bit
    Uint16 SOC15:1;                     // 15 SOC15 Clear Start of Conversion Overflow Bit
};

union ADCSOCOVFCLR1_REG {
    Uint16  all;
    struct  ADCSOCOVFCLR1_BITS  bit;
};

struct ADCSOC0CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC0CTL_REG {
    Uint32  all;
    struct  ADCSOC0CTL_BITS  bit;
};

struct ADCSOC1CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC1CTL_REG {
    Uint32  all;
    struct  ADCSOC1CTL_BITS  bit;
};

struct ADCSOC2CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC2CTL_REG {
    Uint32  all;
    struct  ADCSOC2CTL_BITS  bit;
};

struct ADCSOC3CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC3CTL_REG {
    Uint32  all;
    struct  ADCSOC3CTL_BITS  bit;
};

struct ADCSOC4CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC4CTL_REG {
    Uint32  all;
    struct  ADCSOC4CTL_BITS  bit;
};

struct ADCSOC5CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC5CTL_REG {
    Uint32  all;
    struct  ADCSOC5CTL_BITS  bit;
};

struct ADCSOC6CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC6CTL_REG {
    Uint32  all;
    struct  ADCSOC6CTL_BITS  bit;
};

struct ADCSOC7CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC7CTL_REG {
    Uint32  all;
    struct  ADCSOC7CTL_BITS  bit;
};

struct ADCSOC8CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC8CTL_REG {
    Uint32  all;
    struct  ADCSOC8CTL_BITS  bit;
};

struct ADCSOC9CTL_BITS {                // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC9CTL_REG {
    Uint32  all;
    struct  ADCSOC9CTL_BITS  bit;
};

struct ADCSOC10CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC10CTL_REG {
    Uint32  all;
    struct  ADCSOC10CTL_BITS  bit;
};

struct ADCSOC11CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC11CTL_REG {
    Uint32  all;
    struct  ADCSOC11CTL_BITS  bit;
};

struct ADCSOC12CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC12CTL_REG {
    Uint32  all;
    struct  ADCSOC12CTL_BITS  bit;
};

struct ADCSOC13CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC13CTL_REG {
    Uint32  all;
    struct  ADCSOC13CTL_BITS  bit;
};

struct ADCSOC14CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC14CTL_REG {
    Uint32  all;
    struct  ADCSOC14CTL_BITS  bit;
};

struct ADCSOC15CTL_BITS {               // bits description
    Uint16 ACQPS:9;                     // 8:0 SOC Acquisition Prescale
    Uint16 rsvd1:6;                     // 14:9 Reserved
    Uint32 CHSEL:4;                     // 18:15 SOC Channel Select
    Uint16 rsvd2:1;                     // 19 Reserved
    Uint16 TRIGSEL:5;                   // 24:20 SOC Trigger Source Select
    Uint16 rsvd3:7;                     // 31:25 Reserved
};

union ADCSOC15CTL_REG {
    Uint32  all;
    struct  ADCSOC15CTL_BITS  bit;
};

struct ADCEVTSTAT_BITS {                // bits description
    Uint16 PPB1TRIPHI:1;                // 0 Post Processing Block 1 Trip High Flag
    Uint16 PPB1TRIPLO:1;                // 1 Post Processing Block 1 Trip Low Flag
    Uint16 PPB1ZERO:1;                  // 2 Post Processing Block 1 Zero Crossing Flag
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 PPB2TRIPHI:1;                // 4 Post Processing Block 2 Trip High Flag
    Uint16 PPB2TRIPLO:1;                // 5 Post Processing Block 2 Trip Low Flag
    Uint16 PPB2ZERO:1;                  // 6 Post Processing Block 2 Zero Crossing Flag
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 PPB3TRIPHI:1;                // 8 Post Processing Block 3 Trip High Flag
    Uint16 PPB3TRIPLO:1;                // 9 Post Processing Block 3 Trip Low Flag
    Uint16 PPB3ZERO:1;                  // 10 Post Processing Block 3 Zero Crossing Flag
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 PPB4TRIPHI:1;                // 12 Post Processing Block 4 Trip High Flag
    Uint16 PPB4TRIPLO:1;                // 13 Post Processing Block 4 Trip Low Flag
    Uint16 PPB4ZERO:1;                  // 14 Post Processing Block 4 Zero Crossing Flag
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCEVTSTAT_REG {
    Uint16  all;
    struct  ADCEVTSTAT_BITS  bit;
};

struct ADCEVTCLR_BITS {                 // bits description
    Uint16 PPB1TRIPHI:1;                // 0 Post Processing Block 1 Trip High Clear
    Uint16 PPB1TRIPLO:1;                // 1 Post Processing Block 1 Trip Low Clear
    Uint16 PPB1ZERO:1;                  // 2 Post Processing Block 1 Zero Crossing Clear
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 PPB2TRIPHI:1;                // 4 Post Processing Block 2 Trip High Clear
    Uint16 PPB2TRIPLO:1;                // 5 Post Processing Block 2 Trip Low Clear
    Uint16 PPB2ZERO:1;                  // 6 Post Processing Block 2 Zero Crossing Clear
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 PPB3TRIPHI:1;                // 8 Post Processing Block 3 Trip High Clear
    Uint16 PPB3TRIPLO:1;                // 9 Post Processing Block 3 Trip Low Clear
    Uint16 PPB3ZERO:1;                  // 10 Post Processing Block 3 Zero Crossing Clear
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 PPB4TRIPHI:1;                // 12 Post Processing Block 4 Trip High Clear
    Uint16 PPB4TRIPLO:1;                // 13 Post Processing Block 4 Trip Low Clear
    Uint16 PPB4ZERO:1;                  // 14 Post Processing Block 4 Zero Crossing Clear
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCEVTCLR_REG {
    Uint16  all;
    struct  ADCEVTCLR_BITS  bit;
};

struct ADCEVTSEL_BITS {                 // bits description
    Uint16 PPB1TRIPHI:1;                // 0 Post Processing Block 1 Trip High Event Enable
    Uint16 PPB1TRIPLO:1;                // 1 Post Processing Block 1 Trip Low Event Enable
    Uint16 PPB1ZERO:1;                  // 2 Post Processing Block 1 Zero Crossing Event Enable
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 PPB2TRIPHI:1;                // 4 Post Processing Block 2 Trip High Event Enable
    Uint16 PPB2TRIPLO:1;                // 5 Post Processing Block 2 Trip Low Event Enable
    Uint16 PPB2ZERO:1;                  // 6 Post Processing Block 2 Zero Crossing Event Enable
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 PPB3TRIPHI:1;                // 8 Post Processing Block 3 Trip High Event Enable
    Uint16 PPB3TRIPLO:1;                // 9 Post Processing Block 3 Trip Low Event Enable
    Uint16 PPB3ZERO:1;                  // 10 Post Processing Block 3 Zero Crossing Event Enable
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 PPB4TRIPHI:1;                // 12 Post Processing Block 4 Trip High Event Enable
    Uint16 PPB4TRIPLO:1;                // 13 Post Processing Block 4 Trip Low Event Enable
    Uint16 PPB4ZERO:1;                  // 14 Post Processing Block 4 Zero Crossing Event Enable
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCEVTSEL_REG {
    Uint16  all;
    struct  ADCEVTSEL_BITS  bit;
};

struct ADCEVTINTSEL_BITS {              // bits description
    Uint16 PPB1TRIPHI:1;                // 0 Post Processing Block 1 Trip High Interrupt Enable
    Uint16 PPB1TRIPLO:1;                // 1 Post Processing Block 1 Trip Low Interrupt Enable
    Uint16 PPB1ZERO:1;                  // 2 Post Processing Block 1 Zero Crossing Interrupt Enable
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 PPB2TRIPHI:1;                // 4 Post Processing Block 2 Trip High Interrupt Enable
    Uint16 PPB2TRIPLO:1;                // 5 Post Processing Block 2 Trip Low Interrupt Enable
    Uint16 PPB2ZERO:1;                  // 6 Post Processing Block 2 Zero Crossing Interrupt Enable
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 PPB3TRIPHI:1;                // 8 Post Processing Block 3 Trip High Interrupt Enable
    Uint16 PPB3TRIPLO:1;                // 9 Post Processing Block 3 Trip Low Interrupt Enable
    Uint16 PPB3ZERO:1;                  // 10 Post Processing Block 3 Zero Crossing Interrupt Enable
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 PPB4TRIPHI:1;                // 12 Post Processing Block 4 Trip High Interrupt Enable
    Uint16 PPB4TRIPLO:1;                // 13 Post Processing Block 4 Trip Low Interrupt Enable
    Uint16 PPB4ZERO:1;                  // 14 Post Processing Block 4 Zero Crossing Interrupt Enable
    Uint16 rsvd4:1;                     // 15 Reserved
};

union ADCEVTINTSEL_REG {
    Uint16  all;
    struct  ADCEVTINTSEL_BITS  bit;
};

struct ADCCOUNTER_BITS {                // bits description
    Uint16 FREECOUNT:12;                // 11:0 ADC Free Running Counter Value
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ADCCOUNTER_REG {
    Uint16  all;
    struct  ADCCOUNTER_BITS  bit;
};

struct ADCREV_BITS {                    // bits description
    Uint16 TYPE:8;                      // 7:0 ADC Type
    Uint16 REV:8;                       // 15:8 ADC Revision
};

union ADCREV_REG {
    Uint16  all;
    struct  ADCREV_BITS  bit;
};

struct ADCOFFTRIM_BITS {                // bits description
    Uint16 OFFTRIM:8;                   // 7:0 ADC Offset Trim
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union ADCOFFTRIM_REG {
    Uint16  all;
    struct  ADCOFFTRIM_BITS  bit;
};

struct ADCPPB1CONFIG_BITS {             // bits description
    Uint16 CONFIG:4;                    // 3:0 ADC Post Processing Block Configuration
    Uint16 TWOSCOMPEN:1;                // 4 ADC Post Processing Block Two's Complement Enable
    Uint16 rsvd1:11;                    // 15:5 Reserved
};

union ADCPPB1CONFIG_REG {
    Uint16  all;
    struct  ADCPPB1CONFIG_BITS  bit;
};

struct ADCPPB1STAMP_BITS {              // bits description
    Uint16 DLYSTAMP:12;                 // 11:0 ADC Post Processing Block Delay Time Stamp
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ADCPPB1STAMP_REG {
    Uint16  all;
    struct  ADCPPB1STAMP_BITS  bit;
};

struct ADCPPB1OFFCAL_BITS {             // bits description
    Uint16 OFFCAL:10;                   // 9:0 ADC Post Processing Block Offset Correction
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union ADCPPB1OFFCAL_REG {
    Uint16  all;
    struct  ADCPPB1OFFCAL_BITS  bit;
};

struct ADCPPB1TRIPHI_BITS {             // bits description
    Uint16 LIMITHI:16;                  // 15:0 ADC Post Processing Block Trip High Limit
    Uint16 HSIGN:1;                     // 16 High Limit Sign Bit
    Uint16 rsvd1:15;                    // 31:17 Reserved
};

union ADCPPB1TRIPHI_REG {
    Uint32  all;
    struct  ADCPPB1TRIPHI_BITS  bit;
};

struct ADCPPB1TRIPLO_BITS {             // bits description
    Uint16 LIMITLO:16;                  // 15:0 ADC Post Processing Block Trip Low Limit
    Uint16 LSIGN:1;                     // 16 Low Limit Sign Bit
    Uint16 rsvd1:3;                     // 19:17 Reserved
    Uint16 REQSTAMP:12;                 // 31:20 ADC Post Processing Block Request Time Stamp
};

union ADCPPB1TRIPLO_REG {
    Uint32  all;
    struct  ADCPPB1TRIPLO_BITS  bit;
};

struct ADCPPB2CONFIG_BITS {             // bits description
    Uint16 CONFIG:4;                    // 3:0 ADC Post Processing Block Configuration
    Uint16 TWOSCOMPEN:1;                // 4 ADC Post Processing Block Two's Complement Enable
    Uint16 rsvd1:11;                    // 15:5 Reserved
};

union ADCPPB2CONFIG_REG {
    Uint16  all;
    struct  ADCPPB2CONFIG_BITS  bit;
};

struct ADCPPB2STAMP_BITS {              // bits description
    Uint16 DLYSTAMP:12;                 // 11:0 ADC Post Processing Block Delay Time Stamp
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ADCPPB2STAMP_REG {
    Uint16  all;
    struct  ADCPPB2STAMP_BITS  bit;
};

struct ADCPPB2OFFCAL_BITS {             // bits description
    Uint16 OFFCAL:10;                   // 9:0 ADC Post Processing Block Offset Correction
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union ADCPPB2OFFCAL_REG {
    Uint16  all;
    struct  ADCPPB2OFFCAL_BITS  bit;
};

struct ADCPPB2TRIPHI_BITS {             // bits description
    Uint16 LIMITHI:16;                  // 15:0 ADC Post Processing Block Trip High Limit
    Uint16 HSIGN:1;                     // 16 High Limit Sign Bit
    Uint16 rsvd1:15;                    // 31:17 Reserved
};

union ADCPPB2TRIPHI_REG {
    Uint32  all;
    struct  ADCPPB2TRIPHI_BITS  bit;
};

struct ADCPPB2TRIPLO_BITS {             // bits description
    Uint16 LIMITLO:16;                  // 15:0 ADC Post Processing Block Trip Low Limit
    Uint16 LSIGN:1;                     // 16 Low Limit Sign Bit
    Uint16 rsvd1:3;                     // 19:17 Reserved
    Uint16 REQSTAMP:12;                 // 31:20 ADC Post Processing Block Request Time Stamp
};

union ADCPPB2TRIPLO_REG {
    Uint32  all;
    struct  ADCPPB2TRIPLO_BITS  bit;
};

struct ADCPPB3CONFIG_BITS {             // bits description
    Uint16 CONFIG:4;                    // 3:0 ADC Post Processing Block Configuration
    Uint16 TWOSCOMPEN:1;                // 4 ADC Post Processing Block Two's Complement Enable
    Uint16 rsvd1:11;                    // 15:5 Reserved
};

union ADCPPB3CONFIG_REG {
    Uint16  all;
    struct  ADCPPB3CONFIG_BITS  bit;
};

struct ADCPPB3STAMP_BITS {              // bits description
    Uint16 DLYSTAMP:12;                 // 11:0 ADC Post Processing Block Delay Time Stamp
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ADCPPB3STAMP_REG {
    Uint16  all;
    struct  ADCPPB3STAMP_BITS  bit;
};

struct ADCPPB3OFFCAL_BITS {             // bits description
    Uint16 OFFCAL:10;                   // 9:0 ADC Post Processing Block Offset Correction
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union ADCPPB3OFFCAL_REG {
    Uint16  all;
    struct  ADCPPB3OFFCAL_BITS  bit;
};

struct ADCPPB3TRIPHI_BITS {             // bits description
    Uint16 LIMITHI:16;                  // 15:0 ADC Post Processing Block Trip High Limit
    Uint16 HSIGN:1;                     // 16 High Limit Sign Bit
    Uint16 rsvd1:15;                    // 31:17 Reserved
};

union ADCPPB3TRIPHI_REG {
    Uint32  all;
    struct  ADCPPB3TRIPHI_BITS  bit;
};

struct ADCPPB3TRIPLO_BITS {             // bits description
    Uint16 LIMITLO:16;                  // 15:0 ADC Post Processing Block Trip Low Limit
    Uint16 LSIGN:1;                     // 16 Low Limit Sign Bit
    Uint16 rsvd1:3;                     // 19:17 Reserved
    Uint16 REQSTAMP:12;                 // 31:20 ADC Post Processing Block Request Time Stamp
};

union ADCPPB3TRIPLO_REG {
    Uint32  all;
    struct  ADCPPB3TRIPLO_BITS  bit;
};

struct ADCPPB4CONFIG_BITS {             // bits description
    Uint16 CONFIG:4;                    // 3:0 ADC Post Processing Block Configuration
    Uint16 TWOSCOMPEN:1;                // 4 ADC Post Processing Block Two's Complement Enable
    Uint16 rsvd1:11;                    // 15:5 Reserved
};

union ADCPPB4CONFIG_REG {
    Uint16  all;
    struct  ADCPPB4CONFIG_BITS  bit;
};

struct ADCPPB4STAMP_BITS {              // bits description
    Uint16 DLYSTAMP:12;                 // 11:0 ADC Post Processing Block Delay Time Stamp
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ADCPPB4STAMP_REG {
    Uint16  all;
    struct  ADCPPB4STAMP_BITS  bit;
};

struct ADCPPB4OFFCAL_BITS {             // bits description
    Uint16 OFFCAL:10;                   // 9:0 ADC Post Processing Block Offset Correction
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union ADCPPB4OFFCAL_REG {
    Uint16  all;
    struct  ADCPPB4OFFCAL_BITS  bit;
};

struct ADCPPB4TRIPHI_BITS {             // bits description
    Uint16 LIMITHI:16;                  // 15:0 ADC Post Processing Block Trip High Limit
    Uint16 HSIGN:1;                     // 16 High Limit Sign Bit
    Uint16 rsvd1:15;                    // 31:17 Reserved
};

union ADCPPB4TRIPHI_REG {
    Uint32  all;
    struct  ADCPPB4TRIPHI_BITS  bit;
};

struct ADCPPB4TRIPLO_BITS {             // bits description
    Uint16 LIMITLO:16;                  // 15:0 ADC Post Processing Block Trip Low Limit
    Uint16 LSIGN:1;                     // 16 Low Limit Sign Bit
    Uint16 rsvd1:3;                     // 19:17 Reserved
    Uint16 REQSTAMP:12;                 // 31:20 ADC Post Processing Block Request Time Stamp
};

union ADCPPB4TRIPLO_REG {
    Uint32  all;
    struct  ADCPPB4TRIPLO_BITS  bit;
};

struct ADC_REGS {
    union   ADCCTL1_REG                      ADCCTL1;                      // ADC Control 1 Register
    union   ADCCTL2_REG                      ADCCTL2;                      // ADC Control 2 Register
    union   ADCBURSTCTL_REG                  ADCBURSTCTL;                  // ADC Burst Control Register
    union   ADCINTFLG_REG                    ADCINTFLG;                    // ADC Interrupt Flag Register
    union   ADCINTFLGCLR_REG                 ADCINTFLGCLR;                 // ADC Interrupt Flag Clear Register
    union   ADCINTOVF_REG                    ADCINTOVF;                    // ADC Interrupt Overflow Register
    union   ADCINTOVFCLR_REG                 ADCINTOVFCLR;                 // ADC Interrupt Overflow Clear Register
    union   ADCINTSEL1N2_REG                 ADCINTSEL1N2;                 // ADC Interrupt 1 and 2 Selection Register
    union   ADCINTSEL3N4_REG                 ADCINTSEL3N4;                 // ADC Interrupt 3 and 4 Selection Register
    union   ADCSOCPRICTL_REG                 ADCSOCPRICTL;                 // ADC SOC Priority Control Register
    union   ADCINTSOCSEL1_REG                ADCINTSOCSEL1;                // ADC Interrupt SOC Selection 1 Register
    union   ADCINTSOCSEL2_REG                ADCINTSOCSEL2;                // ADC Interrupt SOC Selection 2 Register
    union   ADCSOCFLG1_REG                   ADCSOCFLG1;                   // ADC SOC Flag 1 Register
    union   ADCSOCFRC1_REG                   ADCSOCFRC1;                   // ADC SOC Force 1 Register
    union   ADCSOCOVF1_REG                   ADCSOCOVF1;                   // ADC SOC Overflow 1 Register
    union   ADCSOCOVFCLR1_REG                ADCSOCOVFCLR1;                // ADC SOC Overflow Clear 1 Register
    union   ADCSOC0CTL_REG                   ADCSOC0CTL;                   // ADC SOC0 Control Register
    union   ADCSOC1CTL_REG                   ADCSOC1CTL;                   // ADC SOC1 Control Register
    union   ADCSOC2CTL_REG                   ADCSOC2CTL;                   // ADC SOC2 Control Register
    union   ADCSOC3CTL_REG                   ADCSOC3CTL;                   // ADC SOC3 Control Register
    union   ADCSOC4CTL_REG                   ADCSOC4CTL;                   // ADC SOC4 Control Register
    union   ADCSOC5CTL_REG                   ADCSOC5CTL;                   // ADC SOC5 Control Register
    union   ADCSOC6CTL_REG                   ADCSOC6CTL;                   // ADC SOC6 Control Register
    union   ADCSOC7CTL_REG                   ADCSOC7CTL;                   // ADC SOC7 Control Register
    union   ADCSOC8CTL_REG                   ADCSOC8CTL;                   // ADC SOC8 Control Register
    union   ADCSOC9CTL_REG                   ADCSOC9CTL;                   // ADC SOC9 Control Register
    union   ADCSOC10CTL_REG                  ADCSOC10CTL;                  // ADC SOC10 Control Register
    union   ADCSOC11CTL_REG                  ADCSOC11CTL;                  // ADC SOC11 Control Register
    union   ADCSOC12CTL_REG                  ADCSOC12CTL;                  // ADC SOC12 Control Register
    union   ADCSOC13CTL_REG                  ADCSOC13CTL;                  // ADC SOC13 Control Register
    union   ADCSOC14CTL_REG                  ADCSOC14CTL;                  // ADC SOC14 Control Register
    union   ADCSOC15CTL_REG                  ADCSOC15CTL;                  // ADC SOC15 Control Register
    union   ADCEVTSTAT_REG                   ADCEVTSTAT;                   // ADC Event Status Register
    Uint16                                   rsvd1;                        // Reserved
    union   ADCEVTCLR_REG                    ADCEVTCLR;                    // ADC Event Clear Register
    Uint16                                   rsvd2;                        // Reserved
    union   ADCEVTSEL_REG                    ADCEVTSEL;                    // ADC Event Selection Register
    Uint16                                   rsvd3;                        // Reserved
    union   ADCEVTINTSEL_REG                 ADCEVTINTSEL;                 // ADC Event Interrupt Selection Register
    Uint16                                   rsvd4[2];                     // Reserved
    union   ADCCOUNTER_REG                   ADCCOUNTER;                   // ADC Counter Register
    union   ADCREV_REG                       ADCREV;                       // ADC Revision Register
    union   ADCOFFTRIM_REG                   ADCOFFTRIM;                   // ADC Offset Trim Register
    Uint16                                   rsvd5[4];                     // Reserved
    union   ADCPPB1CONFIG_REG                ADCPPB1CONFIG;                // ADC PPB1 Config Register
    union   ADCPPB1STAMP_REG                 ADCPPB1STAMP;                 // ADC PPB1 Sample Delay Time Stamp Register
    union   ADCPPB1OFFCAL_REG                ADCPPB1OFFCAL;                // ADC PPB1 Offset Calibration Register
    Uint16                                   ADCPPB1OFFREF;                // ADC PPB1 Offset Reference Register
    union   ADCPPB1TRIPHI_REG                ADCPPB1TRIPHI;                // ADC PPB1 Trip High Register
    union   ADCPPB1TRIPLO_REG                ADCPPB1TRIPLO;                // ADC PPB1 Trip Low/Trigger Time Stamp Register
    union   ADCPPB2CONFIG_REG                ADCPPB2CONFIG;                // ADC PPB2 Config Register
    union   ADCPPB2STAMP_REG                 ADCPPB2STAMP;                 // ADC PPB2 Sample Delay Time Stamp Register
    union   ADCPPB2OFFCAL_REG                ADCPPB2OFFCAL;                // ADC PPB2 Offset Calibration Register
    Uint16                                   ADCPPB2OFFREF;                // ADC PPB2 Offset Reference Register
    union   ADCPPB2TRIPHI_REG                ADCPPB2TRIPHI;                // ADC PPB2 Trip High Register
    union   ADCPPB2TRIPLO_REG                ADCPPB2TRIPLO;                // ADC PPB2 Trip Low/Trigger Time Stamp Register
    union   ADCPPB3CONFIG_REG                ADCPPB3CONFIG;                // ADC PPB3 Config Register
    union   ADCPPB3STAMP_REG                 ADCPPB3STAMP;                 // ADC PPB3 Sample Delay Time Stamp Register
    union   ADCPPB3OFFCAL_REG                ADCPPB3OFFCAL;                // ADC PPB3 Offset Calibration Register
    Uint16                                   ADCPPB3OFFREF;                // ADC PPB3 Offset Reference Register
    union   ADCPPB3TRIPHI_REG                ADCPPB3TRIPHI;                // ADC PPB3 Trip High Register
    union   ADCPPB3TRIPLO_REG                ADCPPB3TRIPLO;                // ADC PPB3 Trip Low/Trigger Time Stamp Register
    union   ADCPPB4CONFIG_REG                ADCPPB4CONFIG;                // ADC PPB4 Config Register
    union   ADCPPB4STAMP_REG                 ADCPPB4STAMP;                 // ADC PPB4 Sample Delay Time Stamp Register
    union   ADCPPB4OFFCAL_REG                ADCPPB4OFFCAL;                // ADC PPB4 Offset Calibration Register
    Uint16                                   ADCPPB4OFFREF;                // ADC PPB4 Offset Reference Register
    union   ADCPPB4TRIPHI_REG                ADCPPB4TRIPHI;                // ADC PPB4 Trip High Register
    union   ADCPPB4TRIPLO_REG                ADCPPB4TRIPLO;                // ADC PPB4 Trip Low/Trigger Time Stamp Register
    Uint16                                   rsvd6[16];                    // Reserved
    Uint32                                   ADCINLTRIM1;                  // ADC Linearity Trim 1 Register
    Uint32                                   ADCINLTRIM2;                  // ADC Linearity Trim 2 Register
    Uint32                                   ADCINLTRIM3;                  // ADC Linearity Trim 3 Register
    Uint32                                   ADCINLTRIM4;                  // ADC Linearity Trim 4 Register
    Uint32                                   ADCINLTRIM5;                  // ADC Linearity Trim 5 Register
    Uint32                                   ADCINLTRIM6;                  // ADC Linearity Trim 6 Register
    Uint16                                   rsvd7[4];                     // Reserved
};

struct ADCPPB1RESULT_BITS {             // bits description
    Uint16 PPBRESULT:16;                // 15:0 ADC Post Processing Block Result
    Uint16 SIGN:16;                     // 31:16 Sign Extended Bits
};

union ADCPPB1RESULT_REG {
    Uint32  all;
    struct  ADCPPB1RESULT_BITS  bit;
};

struct ADCPPB2RESULT_BITS {             // bits description
    Uint16 PPBRESULT:16;                // 15:0 ADC Post Processing Block Result
    Uint16 SIGN:16;                     // 31:16 Sign Extended Bits
};

union ADCPPB2RESULT_REG {
    Uint32  all;
    struct  ADCPPB2RESULT_BITS  bit;
};

struct ADCPPB3RESULT_BITS {             // bits description
    Uint16 PPBRESULT:16;                // 15:0 ADC Post Processing Block Result
    Uint16 SIGN:16;                     // 31:16 Sign Extended Bits
};

union ADCPPB3RESULT_REG {
    Uint32  all;
    struct  ADCPPB3RESULT_BITS  bit;
};

struct ADCPPB4RESULT_BITS {             // bits description
    Uint16 PPBRESULT:16;                // 15:0 ADC Post Processing Block Result
    Uint16 SIGN:16;                     // 31:16 Sign Extended Bits
};

union ADCPPB4RESULT_REG {
    Uint32  all;
    struct  ADCPPB4RESULT_BITS  bit;
};

struct ADC_RESULT_REGS {
    Uint16                                   ADCRESULT0;                   // ADC Result 0 Register
    Uint16                                   ADCRESULT1;                   // ADC Result 1 Register
    Uint16                                   ADCRESULT2;                   // ADC Result 2 Register
    Uint16                                   ADCRESULT3;                   // ADC Result 3 Register
    Uint16                                   ADCRESULT4;                   // ADC Result 4 Register
    Uint16                                   ADCRESULT5;                   // ADC Result 5 Register
    Uint16                                   ADCRESULT6;                   // ADC Result 6 Register
    Uint16                                   ADCRESULT7;                   // ADC Result 7 Register
    Uint16                                   ADCRESULT8;                   // ADC Result 8 Register
    Uint16                                   ADCRESULT9;                   // ADC Result 9 Register
    Uint16                                   ADCRESULT10;                  // ADC Result 10 Register
    Uint16                                   ADCRESULT11;                  // ADC Result 11 Register
    Uint16                                   ADCRESULT12;                  // ADC Result 12 Register
    Uint16                                   ADCRESULT13;                  // ADC Result 13 Register
    Uint16                                   ADCRESULT14;                  // ADC Result 14 Register
    Uint16                                   ADCRESULT15;                  // ADC Result 15 Register
    union   ADCPPB1RESULT_REG                ADCPPB1RESULT;                // ADC Post Processing Block 1 Result Register
    union   ADCPPB2RESULT_REG                ADCPPB2RESULT;                // ADC Post Processing Block 2 Result Register
    union   ADCPPB3RESULT_REG                ADCPPB3RESULT;                // ADC Post Processing Block 3 Result Register
    union   ADCPPB4RESULT_REG                ADCPPB4RESULT;                // ADC Post Processing Block 4 Result Register
};

//---------------------------------------------------------------------------
// ADC External References & Function Declarations:
//
extern volatile struct ADC_RESULT_REGS AdcaResultRegs;
extern volatile struct ADC_RESULT_REGS AdcbResultRegs;
extern volatile struct ADC_RESULT_REGS AdcdResultRegs;
extern volatile struct ADC_REGS AdcaRegs;
extern volatile struct ADC_REGS AdcbRegs;
extern volatile struct ADC_REGS AdcdRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_analogsubsys.h
//
// TITLE:   F2807x Device ANALOGSUBSYS Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// ANALOGSUBSYS Individual Register Bit Definitions:

struct INTOSC1TRIM_BITS {               // bits description
    Uint16 VALFINETRIM:12;              // 11:0 Oscillator Value Fine Trim Bits
    Uint16 rsvd1:4;                     // 15:12 Reserved
    Uint16 rsvd2:8;                     // 23:16 Reserved
    Uint16 rsvd3:8;                     // 31:24 Reserved
};

union INTOSC1TRIM_REG {
    Uint32  all;
    struct  INTOSC1TRIM_BITS  bit;
};

struct INTOSC2TRIM_BITS {               // bits description
    Uint16 VALFINETRIM:12;              // 11:0 Oscillator Value Fine Trim Bits
    Uint16 rsvd1:4;                     // 15:12 Reserved
    Uint16 rsvd2:8;                     // 23:16 Reserved
    Uint16 rsvd3:8;                     // 31:24 Reserved
};

union INTOSC2TRIM_REG {
    Uint32  all;
    struct  INTOSC2TRIM_BITS  bit;
};

struct TSNSCTL_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 Temperature Sensor Enable
    Uint16 rsvd1:15;                    // 15:1 Reserved
};

union TSNSCTL_REG {
    Uint16  all;
    struct  TSNSCTL_BITS  bit;
};

struct LOCK_BITS {                      // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 TSNSCTL:1;                   // 3 Temperature Sensor Control Register Lock
    Uint16 rsvd4:1;                     // 4 Reserved
    Uint16 rsvd5:1;                     // 5 Reserved
    Uint16 rsvd6:1;                     // 6 Reserved
    Uint32 rsvd7:12;                    // 18:7 Reserved
    Uint16 rsvd8:1;                     // 19 Reserved
    Uint16 rsvd9:1;                     // 20 Reserved
    Uint16 rsvd10:1;                    // 21 Reserved
    Uint16 rsvd11:1;                    // 22 Reserved
    Uint16 rsvd12:1;                    // 23 Reserved
    Uint16 rsvd13:1;                    // 24 Reserved
    Uint16 rsvd14:1;                    // 25 Reserved
    Uint16 rsvd15:1;                    // 26 Reserved
    Uint16 rsvd16:1;                    // 27 Reserved
    Uint16 rsvd17:1;                    // 28 Reserved
    Uint16 rsvd18:1;                    // 29 Reserved
    Uint16 rsvd19:1;                    // 30 Reserved
    Uint16 rsvd20:1;                    // 31 Reserved
};

union LOCK_REG {
    Uint32  all;
    struct  LOCK_BITS  bit;
};

struct ANAREFTRIMA_BITS {               // bits description
    Uint16 BGVALTRIM:6;                 // 5:0 Bandgap Value Trim
    Uint16 BGSLOPETRIM:5;               // 10:6 Bandgap Slope Trim
    Uint16 IREFTRIM:5;                  // 15:11 Reference Current Trim
    Uint16 rsvd1:8;                     // 23:16 Reserved
    Uint16 rsvd2:8;                     // 31:24 Reserved
};

union ANAREFTRIMA_REG {
    Uint32  all;
    struct  ANAREFTRIMA_BITS  bit;
};

struct ANAREFTRIMB_BITS {               // bits description
    Uint16 BGVALTRIM:6;                 // 5:0 Bandgap Value Trim
    Uint16 BGSLOPETRIM:5;               // 10:6 Bandgap Slope Trim
    Uint16 IREFTRIM:5;                  // 15:11 Reference Current Trim
    Uint16 rsvd1:8;                     // 23:16 Reserved
    Uint16 rsvd2:8;                     // 31:24 Reserved
};

union ANAREFTRIMB_REG {
    Uint32  all;
    struct  ANAREFTRIMB_BITS  bit;
};

struct ANAREFTRIMD_BITS {               // bits description
    Uint16 BGVALTRIM:6;                 // 5:0 Bandgap Value Trim
    Uint16 BGSLOPETRIM:5;               // 10:6 Bandgap Slope Trim
    Uint16 IREFTRIM:5;                  // 15:11 Reference Current Trim
    Uint16 rsvd1:8;                     // 23:16 Reserved
    Uint16 rsvd2:8;                     // 31:24 Reserved
};

union ANAREFTRIMD_REG {
    Uint32  all;
    struct  ANAREFTRIMD_BITS  bit;
};

struct ANALOG_SUBSYS_REGS {
    Uint16                                   rsvd1[32];                    // Reserved
    union   INTOSC1TRIM_REG                  INTOSC1TRIM;                  // Internal Oscillator 1 Trim Register
    union   INTOSC2TRIM_REG                  INTOSC2TRIM;                  // Internal Oscillator 2 Trim Register
    Uint16                                   rsvd2[2];                     // Reserved
    union   TSNSCTL_REG                      TSNSCTL;                      // Temperature Sensor Control Register
    Uint16                                   rsvd3[7];                     // Reserved
    union   LOCK_REG                         LOCK;                         // Lock Register
    Uint16                                   rsvd4[6];                     // Reserved
    union   ANAREFTRIMA_REG                  ANAREFTRIMA;                  // Analog Reference Trim A Register
    union   ANAREFTRIMB_REG                  ANAREFTRIMB;                  // Analog Reference Trim B Register
    Uint16                                   rsvd5[2];                     // Reserved
    union   ANAREFTRIMD_REG                  ANAREFTRIMD;                  // Analog Reference Trim D Register
    Uint16                                   rsvd6[10];                    // Reserved
};

//---------------------------------------------------------------------------
// ANALOGSUBSYS External References & Function Declarations:
//
extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_cla.h
//
// TITLE:   F2807x Device CLA Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// CLA Individual Register Bit Definitions:

struct MCTL_BITS {                      // bits description
    Uint16 HARDRESET:1;                 // 0 Hard Reset
    Uint16 SOFTRESET:1;                 // 1 Soft Reset
    Uint16 IACKE:1;                     // 2 IACK enable
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union MCTL_REG {
    Uint16  all;
    struct  MCTL_BITS  bit;
};

struct MIFR_BITS {                      // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Flag
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Flag
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Flag
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Flag
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Flag
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Flag
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Flag
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Flag
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MIFR_REG {
    Uint16  all;
    struct  MIFR_BITS  bit;
};

struct MIOVF_BITS {                     // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Overflow Flag
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Overflow Flag
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Overflow Flag
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Overflow Flag
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Overflow Flag
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Overflow Flag
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Overflow Flag
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Overflow Flag
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MIOVF_REG {
    Uint16  all;
    struct  MIOVF_BITS  bit;
};

struct MIFRC_BITS {                     // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Force
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Force
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Force
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Force
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Force
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Force
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Force
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Force
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MIFRC_REG {
    Uint16  all;
    struct  MIFRC_BITS  bit;
};

struct MICLR_BITS {                     // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Flag Clear
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Flag Clear
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Flag Clear
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Flag Clear
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Flag Clear
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Flag Clear
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Flag Clear
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Flag Clear
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MICLR_REG {
    Uint16  all;
    struct  MICLR_BITS  bit;
};

struct MICLROVF_BITS {                  // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Overflow Flag Clear
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Overflow Flag Clear
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Overflow Flag Clear
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Overflow Flag Clear
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Overflow Flag Clear
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Overflow Flag Clear
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Overflow Flag Clear
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Overflow Flag Clear
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MICLROVF_REG {
    Uint16  all;
    struct  MICLROVF_BITS  bit;
};

struct MIER_BITS {                      // bits description
    Uint16 INT1:1;                      // 0 Task 1 Interrupt Enable
    Uint16 INT2:1;                      // 1 Task 2 Interrupt Enable
    Uint16 INT3:1;                      // 2 Task 3 Interrupt Enable
    Uint16 INT4:1;                      // 3 Task 4 Interrupt Enable
    Uint16 INT5:1;                      // 4 Task 5 Interrupt Enable
    Uint16 INT6:1;                      // 5 Task 6 Interrupt Enable
    Uint16 INT7:1;                      // 6 Task 7 Interrupt Enable
    Uint16 INT8:1;                      // 7 Task 8 Interrupt Enable
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MIER_REG {
    Uint16  all;
    struct  MIER_BITS  bit;
};

struct MIRUN_BITS {                     // bits description
    Uint16 INT1:1;                      // 0 Task 1 Run Status
    Uint16 INT2:1;                      // 1 Task 2 Run Status
    Uint16 INT3:1;                      // 2 Task 3 Run Status
    Uint16 INT4:1;                      // 3 Task 4 Run Status
    Uint16 INT5:1;                      // 4 Task 5 Run Status
    Uint16 INT6:1;                      // 5 Task 6 Run Status
    Uint16 INT7:1;                      // 6 Task 7 Run Status
    Uint16 INT8:1;                      // 7 Task 8 Run Status
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union MIRUN_REG {
    Uint16  all;
    struct  MIRUN_BITS  bit;
};

struct _MSTF_BITS {                     // bits description
    Uint16 LVF:1;                       // 0 Latched Overflow Flag 
    Uint16 LUF:1;                       // 1 Latched Underflow Flag 
    Uint16 NF:1;                        // 2 Negative Float Flag 
    Uint16 ZF:1;                        // 3 Zero Float Flag
    Uint16 rsvd1:2;                     // 5:4 Reserved
    Uint16 TF:1;                        // 6 Test Flag 
    Uint16 rsvd2:2;                     // 8:7 Reserved
    Uint16 RNDF32:1;                    // 9 Round 32-bit Floating-Point Mode
    Uint16 rsvd3:1;                     // 10 Reserved
    Uint16 MEALLOW:1;                   // 11 MEALLOW Status
    Uint32 _RPC:16;                     // 27:12 Return PC
    Uint16 rsvd4:4;                     // 31:28 Reserved
};

union _MSTF_REG {
    Uint32  all;
    struct  _MSTF_BITS  bit;
};

union MR_REG {
    Uint32              i32;
    float               f32;
};

struct CLA_REGS {
    Uint16                                   MVECT1;                       // Task Interrupt Vector
    Uint16                                   MVECT2;                       // Task Interrupt Vector
    Uint16                                   MVECT3;                       // Task Interrupt Vector
    Uint16                                   MVECT4;                       // Task Interrupt Vector
    Uint16                                   MVECT5;                       // Task Interrupt Vector
    Uint16                                   MVECT6;                       // Task Interrupt Vector
    Uint16                                   MVECT7;                       // Task Interrupt Vector
    Uint16                                   MVECT8;                       // Task Interrupt Vector
    Uint16                                   rsvd1[8];                     // Reserved
    union   MCTL_REG                         MCTL;                         // Control Register
    Uint16                                   rsvd2[15];                    // Reserved
    union   MIFR_REG                         MIFR;                         // Interrupt Flag Register
    union   MIOVF_REG                        MIOVF;                        // Interrupt Overflow Flag Register
    union   MIFRC_REG                        MIFRC;                        // Interrupt Force Register
    union   MICLR_REG                        MICLR;                        // Interrupt Flag Clear Register
    union   MICLROVF_REG                     MICLROVF;                     // Interrupt Overflow Flag Clear Register
    union   MIER_REG                         MIER;                         // Interrupt Enable Register
    union   MIRUN_REG                        MIRUN;                        // Interrupt Run Status Register
    Uint16                                   rsvd3;                        // Reserved
    Uint16                                   _MPC;                         // CLA Program Counter
    Uint16                                   rsvd4;                        // Reserved
    Uint16                                   _MAR0;                        // CLA Auxiliary Register 0
    Uint16                                   _MAR1;                        // CLA Auxiliary Register 1
    Uint16                                   rsvd5[2];                     // Reserved
    union   _MSTF_REG                        _MSTF;                        // CLA Floating-Point Status Register
    union   MR_REG                           _MR0;                         // CLA Floating-Point Result Register 0
    Uint16                                   rsvd6[2];                     // Reserved
    union   MR_REG                           _MR1;                         // CLA Floating-Point Result Register 1
    Uint16                                   rsvd7[2];                     // Reserved
    union   MR_REG                           _MR2;                         // CLA Floating-Point Result Register 2
    Uint16                                   rsvd8[2];                     // Reserved
    union   MR_REG                           _MR3;                         // CLA Floating-Point Result Register 3
};

struct SOFTINTEN_BITS {                 // bits description
    Uint16 TASK1:1;                     // 0 Task 1 Software Interrupt Enable
    Uint16 TASK2:1;                     // 1 Task 2 Software Interrupt Enable
    Uint16 TASK3:1;                     // 2 Task 3 Software Interrupt Enable
    Uint16 TASK4:1;                     // 3 Task 4 Software Interrupt Enable
    Uint16 TASK5:1;                     // 4 Task 5 Software Interrupt Enable
    Uint16 TASK6:1;                     // 5 Task 6 Software Interrupt Enable
    Uint16 TASK7:1;                     // 6 Task 7 Software Interrupt Enable
    Uint16 TASK8:1;                     // 7 Task 8 Software Interrupt Enable
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SOFTINTEN_REG {
    Uint32  all;
    struct  SOFTINTEN_BITS  bit;
};

struct SOFTINTFRC_BITS {                // bits description
    Uint16 TASK1:1;                     // 0 Task 1 Software Interrupt Force
    Uint16 TASK2:1;                     // 1 Task 2 Software Interrupt Force
    Uint16 TASK3:1;                     // 2 Task 3 Software Interrupt Force
    Uint16 TASK4:1;                     // 3 Task 4 Software Interrupt Force
    Uint16 TASK5:1;                     // 4 Task 5 Software Interrupt Force
    Uint16 TASK6:1;                     // 5 Task 6 Software Interrupt Force
    Uint16 TASK7:1;                     // 6 Task 7 Software Interrupt Force
    Uint16 TASK8:1;                     // 7 Task 8 Software Interrupt Force
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SOFTINTFRC_REG {
    Uint32  all;
    struct  SOFTINTFRC_BITS  bit;
};

struct CLA_SOFTINT_REGS {
    union   SOFTINTEN_REG                    SOFTINTEN;                    // Task Software Interrupt Enable
    union   SOFTINTFRC_REG                   SOFTINTFRC;                   // Task Software Interrupt Force
};

//---------------------------------------------------------------------------
// CLA External References & Function Declarations:
//
extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs;
extern volatile struct CLA_REGS Cla1Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_cmpss.h
//
// TITLE:   F2807x Device CMPSS Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// CMPSS Individual Register Bit Definitions:

struct COMPCTL_BITS {                   // bits description
    Uint16 COMPHSOURCE:1;               // 0 High Comparator Source Select
    Uint16 COMPHINV:1;                  // 1 High Comparator Invert Select
    Uint16 CTRIPHSEL:2;                 // 3:2 High Comparator Trip Select
    Uint16 CTRIPOUTHSEL:2;              // 5:4 High Comparator Trip Output Select
    Uint16 ASYNCHEN:1;                  // 6 High Comparator Asynchronous Path Enable
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 COMPLSOURCE:1;               // 8 Low Comparator Source Select
    Uint16 COMPLINV:1;                  // 9 Low Comparator Invert Select
    Uint16 CTRIPLSEL:2;                 // 11:10 Low Comparator Trip Select
    Uint16 CTRIPOUTLSEL:2;              // 13:12 Low Comparator Trip Output Select
    Uint16 ASYNCLEN:1;                  // 14 Low Comparator Asynchronous Path Enable
    Uint16 COMPDACE:1;                  // 15 Comparator/DAC Enable
};

union COMPCTL_REG {
    Uint16  all;
    struct  COMPCTL_BITS  bit;
};

struct COMPHYSCTL_BITS {                // bits description
    Uint16 COMPHYS:3;                   // 2:0 Comparator Hysteresis Trim
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union COMPHYSCTL_REG {
    Uint16  all;
    struct  COMPHYSCTL_BITS  bit;
};

struct COMPSTS_BITS {                   // bits description
    Uint16 COMPHSTS:1;                  // 0 High Comparator Status
    Uint16 COMPHLATCH:1;                // 1 High Comparator Latched Status
    Uint16 rsvd1:6;                     // 7:2 Reserved
    Uint16 COMPLSTS:1;                  // 8 Low Comparator Status
    Uint16 COMPLLATCH:1;                // 9 Low Comparator Latched Status
    Uint16 rsvd2:6;                     // 15:10 Reserved
};

union COMPSTS_REG {
    Uint16  all;
    struct  COMPSTS_BITS  bit;
};

struct COMPSTSCLR_BITS {                // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 HLATCHCLR:1;                 // 1 High Comparator Latched Status Clear
    Uint16 HSYNCCLREN:1;                // 2 High Comparator PWMSYNC Clear Enable
    Uint16 rsvd2:6;                     // 8:3 Reserved
    Uint16 LLATCHCLR:1;                 // 9 Low Comparator Latched Status Clear
    Uint16 LSYNCCLREN:1;                // 10 Low Comparator PWMSYNC Clear Enable
    Uint16 rsvd3:5;                     // 15:11 Reserved
};

union COMPSTSCLR_REG {
    Uint16  all;
    struct  COMPSTSCLR_BITS  bit;
};

struct COMPDACCTL_BITS {                // bits description
    Uint16 DACSOURCE:1;                 // 0 DAC Source Control
    Uint16 RAMPSOURCE:4;                // 4:1 Ramp Generator Source Control
    Uint16 SELREF:1;                    // 5 DAC Reference Select
    Uint16 RAMPLOADSEL:1;               // 6 Ramp Load Select
    Uint16 SWLOADSEL:1;                 // 7 Software Load Select
    Uint16 rsvd1:6;                     // 13:8 Reserved
    Uint16 FREESOFT:2;                  // 15:14 Free/Soft Emulation Bits
};

union COMPDACCTL_REG {
    Uint16  all;
    struct  COMPDACCTL_BITS  bit;
};

struct DACHVALS_BITS {                  // bits description
    Uint16 DACVAL:12;                   // 11:0 DAC Value Control
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACHVALS_REG {
    Uint16  all;
    struct  DACHVALS_BITS  bit;
};

struct DACHVALA_BITS {                  // bits description
    Uint16 DACVAL:12;                   // 11:0 DAC Value Control
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACHVALA_REG {
    Uint16  all;
    struct  DACHVALA_BITS  bit;
};

struct DACLVALS_BITS {                  // bits description
    Uint16 DACVAL:12;                   // 11:0 DAC Value Control
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACLVALS_REG {
    Uint16  all;
    struct  DACLVALS_BITS  bit;
};

struct DACLVALA_BITS {                  // bits description
    Uint16 DACVAL:12;                   // 11:0 DAC Value Control
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACLVALA_REG {
    Uint16  all;
    struct  DACLVALA_BITS  bit;
};

struct RAMPDLYA_BITS {                  // bits description
    Uint16 DELAY:13;                    // 12:0 Ramp Delay Value
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union RAMPDLYA_REG {
    Uint16  all;
    struct  RAMPDLYA_BITS  bit;
};

struct RAMPDLYS_BITS {                  // bits description
    Uint16 DELAY:13;                    // 12:0 Ramp Delay Value
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union RAMPDLYS_REG {
    Uint16  all;
    struct  RAMPDLYS_BITS  bit;
};

struct CTRIPLFILCTL_BITS {              // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 SAMPWIN:5;                   // 8:4 Sample Window
    Uint16 THRESH:5;                    // 13:9 Majority Voting Threshold
    Uint16 rsvd2:1;                     // 14 Reserved
    Uint16 FILINIT:1;                   // 15 Filter Initialization Bit
};

union CTRIPLFILCTL_REG {
    Uint16  all;
    struct  CTRIPLFILCTL_BITS  bit;
};

struct CTRIPLFILCLKCTL_BITS {           // bits description
    Uint16 CLKPRESCALE:10;              // 9:0 Sample Clock Prescale
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union CTRIPLFILCLKCTL_REG {
    Uint16  all;
    struct  CTRIPLFILCLKCTL_BITS  bit;
};

struct CTRIPHFILCTL_BITS {              // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 SAMPWIN:5;                   // 8:4 Sample Window
    Uint16 THRESH:5;                    // 13:9 Majority Voting Threshold
    Uint16 rsvd2:1;                     // 14 Reserved
    Uint16 FILINIT:1;                   // 15 Filter Initialization Bit
};

union CTRIPHFILCTL_REG {
    Uint16  all;
    struct  CTRIPHFILCTL_BITS  bit;
};

struct CTRIPHFILCLKCTL_BITS {           // bits description
    Uint16 CLKPRESCALE:10;              // 9:0 Sample Clock Prescale
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union CTRIPHFILCLKCTL_REG {
    Uint16  all;
    struct  CTRIPHFILCLKCTL_BITS  bit;
};

struct COMPLOCK_BITS {                  // bits description
    Uint16 COMPCTL:1;                   // 0 COMPCTL Lock
    Uint16 COMPHYSCTL:1;                // 1 COMPHYSCTL Lock
    Uint16 DACCTL:1;                    // 2 DACCTL Lock
    Uint16 CTRIP:1;                     // 3 CTRIP Lock
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 rsvd2:11;                    // 15:5 Reserved
};

union COMPLOCK_REG {
    Uint16  all;
    struct  COMPLOCK_BITS  bit;
};

struct CMPSS_REGS {
    union   COMPCTL_REG                      COMPCTL;                      // CMPSS Comparator Control Register
    union   COMPHYSCTL_REG                   COMPHYSCTL;                   // CMPSS Comparator Hysteresis Control Register
    union   COMPSTS_REG                      COMPSTS;                      // CMPSS Comparator Status Register
    union   COMPSTSCLR_REG                   COMPSTSCLR;                   // CMPSS Comparator Status Clear Register
    union   COMPDACCTL_REG                   COMPDACCTL;                   // CMPSS DAC Control Register
    Uint16                                   rsvd1;                        // Reserved
    union   DACHVALS_REG                     DACHVALS;                     // CMPSS High DAC Value Shadow Register
    union   DACHVALA_REG                     DACHVALA;                     // CMPSS High DAC Value Active Register
    Uint16                                   RAMPMAXREFA;                  // CMPSS Ramp Max Reference Active Register
    Uint16                                   rsvd2;                        // Reserved
    Uint16                                   RAMPMAXREFS;                  // CMPSS Ramp Max Reference Shadow Register
    Uint16                                   rsvd3;                        // Reserved
    Uint16                                   RAMPDECVALA;                  // CMPSS Ramp Decrement Value Active Register
    Uint16                                   rsvd4;                        // Reserved
    Uint16                                   RAMPDECVALS;                  // CMPSS Ramp Decrement Value Shadow Register
    Uint16                                   rsvd5;                        // Reserved
    Uint16                                   RAMPSTS;                      // CMPSS Ramp Status Register
    Uint16                                   rsvd6;                        // Reserved
    union   DACLVALS_REG                     DACLVALS;                     // CMPSS Low DAC Value Shadow Register
    union   DACLVALA_REG                     DACLVALA;                     // CMPSS Low DAC Value Active Register
    union   RAMPDLYA_REG                     RAMPDLYA;                     // CMPSS Ramp Delay Active Register
    union   RAMPDLYS_REG                     RAMPDLYS;                     // CMPSS Ramp Delay Shadow Register
    union   CTRIPLFILCTL_REG                 CTRIPLFILCTL;                 // CTRIPL Filter Control Register
    union   CTRIPLFILCLKCTL_REG              CTRIPLFILCLKCTL;              // CTRIPL Filter Clock Control Register
    union   CTRIPHFILCTL_REG                 CTRIPHFILCTL;                 // CTRIPH Filter Control Register
    union   CTRIPHFILCLKCTL_REG              CTRIPHFILCLKCTL;              // CTRIPH Filter Clock Control Register
    union   COMPLOCK_REG                     COMPLOCK;                     // CMPSS Lock Register
    Uint16                                   rsvd7[5];                     // Reserved
};

//---------------------------------------------------------------------------
// CMPSS External References & Function Declarations:
//
extern volatile struct CMPSS_REGS Cmpss1Regs;
extern volatile struct CMPSS_REGS Cmpss2Regs;
extern volatile struct CMPSS_REGS Cmpss3Regs;
extern volatile struct CMPSS_REGS Cmpss4Regs;
extern volatile struct CMPSS_REGS Cmpss5Regs;
extern volatile struct CMPSS_REGS Cmpss6Regs;
extern volatile struct CMPSS_REGS Cmpss7Regs;
extern volatile struct CMPSS_REGS Cmpss8Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_cputimer.h
//
// TITLE:   F2807x Device CPUTIMER Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// CPUTIMER Individual Register Bit Definitions:

struct TIM_BITS {                       // bits description
    Uint16 LSW:16;                      // 15:0 CPU-Timer Counter Registers
    Uint16 MSW:16;                      // 31:16 CPU-Timer Counter Registers High
};

union TIM_REG {
    Uint32  all;
    struct  TIM_BITS  bit;
};

struct PRD_BITS {                       // bits description
    Uint16 LSW:16;                      // 15:0 CPU-Timer Period Registers
    Uint16 MSW:16;                      // 31:16 CPU-Timer Period Registers High
};

union PRD_REG {
    Uint32  all;
    struct  PRD_BITS  bit;
};

struct TCR_BITS {                       // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 TSS:1;                       // 4 CPU-Timer stop status bit.
    Uint16 TRB:1;                       // 5 Timer reload 
    Uint16 rsvd2:4;                     // 9:6 Reserved
    Uint16 SOFT:1;                      // 10 Emulation modes 
    Uint16 FREE:1;                      // 11 Emulation modes 
    Uint16 rsvd3:2;                     // 13:12 Reserved
    Uint16 TIE:1;                       // 14 CPU-Timer Interrupt Enable.
    Uint16 TIF:1;                       // 15 CPU-Timer Interrupt Flag. 
};

union TCR_REG {
    Uint16  all;
    struct  TCR_BITS  bit;
};

struct TPR_BITS {                       // bits description
    Uint16 TDDR:8;                      // 7:0 CPU-Timer Divide-Down.
    Uint16 PSC:8;                       // 15:8 CPU-Timer Prescale Counter.
};

union TPR_REG {
    Uint16  all;
    struct  TPR_BITS  bit;
};

struct TPRH_BITS {                      // bits description
    Uint16 TDDRH:8;                     // 7:0 CPU-Timer Divide-Down.
    Uint16 PSCH:8;                      // 15:8 CPU-Timer Prescale Counter.
};

union TPRH_REG {
    Uint16  all;
    struct  TPRH_BITS  bit;
};

struct CPUTIMER_REGS {
    union   TIM_REG                          TIM;                          // CPU-Timer, Counter Register
    union   PRD_REG                          PRD;                          // CPU-Timer, Period Register
    union   TCR_REG                          TCR;                          // CPU-Timer, Control Register
    Uint16                                   rsvd1;                        // Reserved
    union   TPR_REG                          TPR;                          // CPU-Timer, Prescale Register
    union   TPRH_REG                         TPRH;                         // CPU-Timer, Prescale Register High
};

//---------------------------------------------------------------------------
// CPUTIMER External References & Function Declarations:
//
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_dac.h
//
// TITLE:   F2807x Device DAC Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// DAC Individual Register Bit Definitions:

struct DACREV_BITS {                    // bits description
    Uint16 REV:8;                       // 7:0 DAC Revision Register
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union DACREV_REG {
    Uint16  all;
    struct  DACREV_BITS  bit;
};

struct DACCTL_BITS {                    // bits description
    Uint16 DACREFSEL:1;                 // 0 DAC Reference Select
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 LOADMODE:1;                  // 2 DACVALA Load Mode
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 SYNCSEL:4;                   // 7:4 DAC PWMSYNC Select
    Uint16 rsvd3:8;                     // 15:8 Reserved
};

union DACCTL_REG {
    Uint16  all;
    struct  DACCTL_BITS  bit;
};

struct DACVALA_BITS {                   // bits description
    Uint16 DACVALA:12;                  // 11:0 DAC Active Output Code
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACVALA_REG {
    Uint16  all;
    struct  DACVALA_BITS  bit;
};

struct DACVALS_BITS {                   // bits description
    Uint16 DACVALS:12;                  // 11:0 DAC Shadow Output Code
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union DACVALS_REG {
    Uint16  all;
    struct  DACVALS_BITS  bit;
};

struct DACOUTEN_BITS {                  // bits description
    Uint16 DACOUTEN:1;                  // 0 DAC Output Code
    Uint16 rsvd1:15;                    // 15:1 Reserved
};

union DACOUTEN_REG {
    Uint16  all;
    struct  DACOUTEN_BITS  bit;
};

struct DACLOCK_BITS {                   // bits description
    Uint16 DACCTL:1;                    // 0 DAC Control Register Lock
    Uint16 DACVAL:1;                    // 1 DAC Value Register Lock
    Uint16 DACOUTEN:1;                  // 2 DAC Output Enable Register Lock
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union DACLOCK_REG {
    Uint16  all;
    struct  DACLOCK_BITS  bit;
};

struct DACTRIM_BITS {                   // bits description
    Uint16 OFFSET_TRIM:8;               // 7:0 DAC Offset Trim
    Uint16 rsvd1:4;                     // 11:8 Reserved
    Uint16 rsvd2:4;                     // 15:12 Reserved
};

union DACTRIM_REG {
    Uint16  all;
    struct  DACTRIM_BITS  bit;
};

struct DAC_REGS {
    union   DACREV_REG                       DACREV;                       // DAC Revision Register
    union   DACCTL_REG                       DACCTL;                       // DAC Control Register
    union   DACVALA_REG                      DACVALA;                      // DAC Value Register - Active
    union   DACVALS_REG                      DACVALS;                      // DAC Value Register - Shadow
    union   DACOUTEN_REG                     DACOUTEN;                     // DAC Output Enable Register
    union   DACLOCK_REG                      DACLOCK;                      // DAC Lock Register
    union   DACTRIM_REG                      DACTRIM;                      // DAC Trim Register
    Uint16                                   rsvd1;                        // Reserved
};

//---------------------------------------------------------------------------
// DAC External References & Function Declarations:
//
extern volatile struct DAC_REGS DacaRegs;
extern volatile struct DAC_REGS DacbRegs;
extern volatile struct DAC_REGS DaccRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_dcsm.h
//
// TITLE:   F2807x Device DCSM Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// DCSM Individual Register Bit Definitions:

struct DCSM_Z1_OTP {
    Uint32                                   Z1OTP_LINKPOINTER1;           // Zone 1 Link Pointer1 in Z1 OTP
    Uint16                                   rsvd1[2];                     // Reserved
    Uint32                                   Z1OTP_LINKPOINTER2;           // Zone 1 Link Pointer2 in Z1 OTP
    Uint16                                   rsvd2[2];                     // Reserved
    Uint32                                   Z1OTP_LINKPOINTER3;           // Zone 1 Link Pointer3 in Z1 OTP
    Uint16                                   rsvd3[6];                     // Reserved
    Uint32                                   Z1OTP_PSWDLOCK;               // Secure Password Lock in Z1 OTP
    Uint16                                   rsvd4[2];                     // Reserved
    Uint32                                   Z1OTP_CRCLOCK;                // Secure CRC Lock in Z1 OTP
    Uint16                                   rsvd5[8];                     // Reserved
    Uint32                                   Z1OTP_BOOTCTRL;               // Boot Mode in Z1 OTP
};

struct DCSM_Z2_OTP {
    Uint32                                   Z2OTP_LINKPOINTER1;           // Zone 2 Link Pointer1 in Z2 OTP
    Uint16                                   rsvd1[2];                     // Reserved
    Uint32                                   Z2OTP_LINKPOINTER2;           // Zone 2 Link Pointer2 in Z2 OTP
    Uint16                                   rsvd2[2];                     // Reserved
    Uint32                                   Z2OTP_LINKPOINTER3;           // Zone 2 Link Pointer3 in Z2 OTP
    Uint16                                   rsvd3[6];                     // Reserved
    Uint32                                   Z2OTP_PSWDLOCK;               // Secure Password Lock in Z2 OTP
    Uint16                                   rsvd4[2];                     // Reserved
    Uint32                                   Z2OTP_CRCLOCK;                // Secure CRC Lock in Z2 OTP
    Uint16                                   rsvd5[8];                     // Reserved
    Uint32                                   Z2OTP_BOOTCTRL;               // Boot Mode in Z2 OTP
};

struct Z1_LINKPOINTER_BITS {            // bits description
    Uint32 LINKPOINTER:29;              // 28:0 Zone1 LINK Pointer.
    Uint16 rsvd1:3;                     // 31:29 Reserved
};

union Z1_LINKPOINTER_REG {
    Uint32  all;
    struct  Z1_LINKPOINTER_BITS  bit;
};

struct Z1_OTPSECLOCK_BITS {             // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 PSWDLOCK:4;                  // 7:4 Zone1 Password Lock.
    Uint16 CRCLOCK:4;                   // 11:8 Zone1 CRC Lock.
    Uint16 rsvd2:4;                     // 15:12 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union Z1_OTPSECLOCK_REG {
    Uint32  all;
    struct  Z1_OTPSECLOCK_BITS  bit;
};

struct Z1_BOOTCTRL_BITS {               // bits description
    Uint16 KEY:8;                       // 7:0 OTP Boot Key
    Uint16 BMODE:8;                     // 15:8 OTP Boot Mode
    Uint16 BOOTPIN0:8;                  // 23:16 OTP Boot Pin 0 Mapping
    Uint16 BOOTPIN1:8;                  // 31:24 OTP Boot Pin 1 Mapping
};

union Z1_BOOTCTRL_REG {
    Uint32  all;
    struct  Z1_BOOTCTRL_BITS  bit;
};

struct Z1_CR_BITS {                     // bits description
    Uint16 rsvd1:3;                     // 2:0 Reserved
    Uint16 ALLZERO:1;                   // 3 CSMPSWD All Zeros
    Uint16 ALLONE:1;                    // 4 CSMPSWD All Ones
    Uint16 UNSECURE:1;                  // 5 CSMPSWD Match CSMKEY
    Uint16 ARMED:1;                     // 6 CSM Armed
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:7;                     // 14:8 Reserved
    Uint16 FORCESEC:1;                  // 15 Force Secure
};

union Z1_CR_REG {
    Uint16  all;
    struct  Z1_CR_BITS  bit;
};

struct Z1_GRABSECTR_BITS {              // bits description
    Uint16 GRAB_SECTA:2;                // 1:0 Grab Flash Sector A
    Uint16 GRAB_SECTB:2;                // 3:2 Grab Flash Sector B
    Uint16 GRAB_SECTC:2;                // 5:4 Grab Flash Sector C
    Uint16 GRAB_SECTD:2;                // 7:6 Grab Flash Sector D
    Uint16 GRAB_SECTE:2;                // 9:8 Grab Flash Sector E
    Uint16 GRAB_SECTF:2;                // 11:10 Grab Flash Sector F
    Uint16 GRAB_SECTG:2;                // 13:12 Grab Flash Sector G
    Uint16 GRAB_SECTH:2;                // 15:14 Grab Flash Sector H
    Uint16 GRAB_SECTI:2;                // 17:16 Grab Flash Sector I
    Uint16 GRAB_SECTJ:2;                // 19:18 Grab Flash Sector J
    Uint16 GRAB_SECTK:2;                // 21:20 Grab Flash Sector K
    Uint16 GRAB_SECTL:2;                // 23:22 Grab Flash Sector L
    Uint16 GRAB_SECTM:2;                // 25:24 Grab Flash Sector M
    Uint16 GRAB_SECTN:2;                // 27:26 Grab Flash Sector N
    Uint16 GRAB_BANK1:2;                // 29:28 Grab BANK1 (all sectors of bank 1)
    Uint16 rsvd1:2;                     // 31:30 Reserved
};

union Z1_GRABSECTR_REG {
    Uint32  all;
    struct  Z1_GRABSECTR_BITS  bit;
};

struct Z1_GRABRAMR_BITS {               // bits description
    Uint16 GRAB_RAM0:2;                 // 1:0 Grab RAM LS0
    Uint16 GRAB_RAM1:2;                 // 3:2 Grab RAM LS1
    Uint16 GRAB_RAM2:2;                 // 5:4 Grab RAM LS2
    Uint16 GRAB_RAM3:2;                 // 7:6 Grab RAM LS3
    Uint16 GRAB_RAM4:2;                 // 9:8 Grab RAM LS4
    Uint16 GRAB_RAM5:2;                 // 11:10 Grab RAM LS5
    Uint16 GRAB_RAM6:2;                 // 13:12 Grab RAM D0
    Uint16 GRAB_RAM7:2;                 // 15:14 Grab RAM D1
    Uint16 rsvd1:12;                    // 27:16 Reserved
    Uint16 GRAB_CLA1:2;                 // 29:28 Grab CLA1
    Uint16 rsvd2:2;                     // 31:30 Reserved
};

union Z1_GRABRAMR_REG {
    Uint32  all;
    struct  Z1_GRABRAMR_BITS  bit;
};

struct Z1_EXEONLYSECTR_BITS {           // bits description
    Uint16 EXEONLY_SECTA:1;             // 0 Execute-Only Flash Sector A
    Uint16 EXEONLY_SECTB:1;             // 1 Execute-Only Flash Sector B
    Uint16 EXEONLY_SECTC:1;             // 2 Execute-Only Flash Sector C
    Uint16 EXEONLY_SECTD:1;             // 3 Execute-Only Flash Sector D 
    Uint16 EXEONLY_SECTE:1;             // 4 Execute-Only Flash Sector E
    Uint16 EXEONLY_SECTF:1;             // 5 Execute-Only Flash Sector F 
    Uint16 EXEONLY_SECTG:1;             // 6 Execute-Only Flash Sector G 
    Uint16 EXEONLY_SECTH:1;             // 7 Execute-Only Flash Sector H
    Uint16 EXEONLY_SECTI:1;             // 8 Execute-Only Flash Sector I
    Uint16 EXEONLY_SECTJ:1;             // 9 Execute-Only Flash Sector J
    Uint16 EXEONLY_SECTK:1;             // 10 Execute-Only Flash Sector K
    Uint16 EXEONLY_SECTL:1;             // 11 Execute-Only Flash Sector L
    Uint16 EXEONLY_SECTM:1;             // 12 Execute-Only Flash Sector M
    Uint16 EXEONLY_SECTN:1;             // 13 Execute-Only Flash Sector N
    Uint16 EXEONLY_BANK1:1;             // 14 Execute-Only Flash BANK1
    Uint16 rsvd1:1;                     // 15 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union Z1_EXEONLYSECTR_REG {
    Uint32  all;
    struct  Z1_EXEONLYSECTR_BITS  bit;
};

struct Z1_EXEONLYRAMR_BITS {            // bits description
    Uint16 EXEONLY_RAM0:1;              // 0 Execute-Only RAM LS0
    Uint16 EXEONLY_RAM1:1;              // 1 Execute-Only RAM LS1
    Uint16 EXEONLY_RAM2:1;              // 2 Execute-Only RAM LS2
    Uint16 EXEONLY_RAM3:1;              // 3 Execute-Only RAM LS3
    Uint16 EXEONLY_RAM4:1;              // 4 Execute-Only RAM LS4
    Uint16 EXEONLY_RAM5:1;              // 5 Execute-Only RAM LS5
    Uint16 EXEONLY_RAM6:1;              // 6 Execute-Only RAM D0
    Uint16 EXEONLY_RAM7:1;              // 7 Execute-Only RAM D1
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union Z1_EXEONLYRAMR_REG {
    Uint32  all;
    struct  Z1_EXEONLYRAMR_BITS  bit;
};

struct DCSM_Z1_REGS {
    union   Z1_LINKPOINTER_REG               Z1_LINKPOINTER;               // Zone 1 Link Pointer
    union   Z1_OTPSECLOCK_REG                Z1_OTPSECLOCK;                // Zone 1 OTP Secure JTAG lock
    union   Z1_BOOTCTRL_REG                  Z1_BOOTCTRL;                  // Boot Mode
    Uint32                                   Z1_LINKPOINTERERR;            // Link Pointer Error
    Uint16                                   rsvd1[8];                     // Reserved
    Uint32                                   Z1_CSMKEY0;                   // Zone 1 CSM Key 0
    Uint32                                   Z1_CSMKEY1;                   // Zone 1 CSM Key 1
    Uint32                                   Z1_CSMKEY2;                   // Zone 1 CSM Key 2
    Uint32                                   Z1_CSMKEY3;                   // Zone 1 CSM Key 3
    Uint16                                   rsvd2;                        // Reserved
    union   Z1_CR_REG                        Z1_CR;                        // Zone 1 CSM Control Register
    union   Z1_GRABSECTR_REG                 Z1_GRABSECTR;                 // Zone 1 Grab Flash Sectors Register
    union   Z1_GRABRAMR_REG                  Z1_GRABRAMR;                  // Zone 1 Grab RAM Blocks Register
    union   Z1_EXEONLYSECTR_REG              Z1_EXEONLYSECTR;              // Zone 1 Flash Execute_Only Sector Register
    union   Z1_EXEONLYRAMR_REG               Z1_EXEONLYRAMR;               // Zone 1 RAM Execute_Only Block Register
    Uint16                                   rsvd3;                        // Reserved
};

struct Z2_LINKPOINTER_BITS {            // bits description
    Uint32 LINKPOINTER:29;              // 28:0 Zone2 LINK Pointer.
    Uint16 rsvd1:3;                     // 31:29 Reserved
};

union Z2_LINKPOINTER_REG {
    Uint32  all;
    struct  Z2_LINKPOINTER_BITS  bit;
};

struct Z2_OTPSECLOCK_BITS {             // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 PSWDLOCK:4;                  // 7:4 Zone2 Password Lock.
    Uint16 CRCLOCK:4;                   // 11:8 Zone2 CRC Lock.
    Uint16 rsvd2:4;                     // 15:12 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union Z2_OTPSECLOCK_REG {
    Uint32  all;
    struct  Z2_OTPSECLOCK_BITS  bit;
};

struct Z2_BOOTCTRL_BITS {               // bits description
    Uint16 KEY:8;                       // 7:0 OTP Boot Key
    Uint16 BMODE:8;                     // 15:8 OTP Boot Mode
    Uint16 BOOTPIN0:8;                  // 23:16 OTP Boot Pin 0 Mapping
    Uint16 BOOTPIN1:8;                  // 31:24 OTP Boot Pin 1 Mapping
};

union Z2_BOOTCTRL_REG {
    Uint32  all;
    struct  Z2_BOOTCTRL_BITS  bit;
};

struct Z2_CR_BITS {                     // bits description
    Uint16 rsvd1:3;                     // 2:0 Reserved
    Uint16 ALLZERO:1;                   // 3 CSMPSWD All Zeros
    Uint16 ALLONE:1;                    // 4 CSMPSWD All Ones
    Uint16 UNSECURE:1;                  // 5 CSMPSWD Match CSMKEY
    Uint16 ARMED:1;                     // 6 CSM Armed
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:7;                     // 14:8 Reserved
    Uint16 FORCESEC:1;                  // 15 Force Secure
};

union Z2_CR_REG {
    Uint16  all;
    struct  Z2_CR_BITS  bit;
};

struct Z2_GRABSECTR_BITS {              // bits description
    Uint16 GRAB_SECTA:2;                // 1:0 Grab Flash Sector A
    Uint16 GRAB_SECTB:2;                // 3:2 Grab Flash Sector B
    Uint16 GRAB_SECTC:2;                // 5:4 Grab Flash Sector C
    Uint16 GRAB_SECTD:2;                // 7:6 Grab Flash Sector D
    Uint16 GRAB_SECTE:2;                // 9:8 Grab Flash Sector E
    Uint16 GRAB_SECTF:2;                // 11:10 Grab Flash Sector F
    Uint16 GRAB_SECTG:2;                // 13:12 Grab Flash Sector G
    Uint16 GRAB_SECTH:2;                // 15:14 Grab Flash Sector H
    Uint16 GRAB_SECTI:2;                // 17:16 Grab Flash Sector I
    Uint16 GRAB_SECTJ:2;                // 19:18 Grab Flash Sector J
    Uint16 GRAB_SECTK:2;                // 21:20 Grab Flash Sector K
    Uint16 GRAB_SECTL:2;                // 23:22 Grab Flash Sector L
    Uint16 GRAB_SECTM:2;                // 25:24 Grab Flash Sector M
    Uint16 GRAB_SECTN:2;                // 27:26 Grab Flash Sector N
    Uint16 GRAB_BANK1:2;                // 29:28 Grab BANK1 (all sectors of bank 1)
    Uint16 rsvd1:2;                     // 31:30 Reserved
};

union Z2_GRABSECTR_REG {
    Uint32  all;
    struct  Z2_GRABSECTR_BITS  bit;
};

struct Z2_GRABRAMR_BITS {               // bits description
    Uint16 GRAB_RAM0:2;                 // 1:0 Grab RAM LS0
    Uint16 GRAB_RAM1:2;                 // 3:2 Grab RAM LS1
    Uint16 GRAB_RAM2:2;                 // 5:4 Grab RAM LS2
    Uint16 GRAB_RAM3:2;                 // 7:6 Grab RAM LS3
    Uint16 GRAB_RAM4:2;                 // 9:8 Grab RAM LS4
    Uint16 GRAB_RAM5:2;                 // 11:10 Grab RAM LS5
    Uint16 GRAB_RAM6:2;                 // 13:12 Grab RAM D0
    Uint16 GRAB_RAM7:2;                 // 15:14 Grab RAM D1
    Uint16 rsvd1:12;                    // 27:16 Reserved
    Uint16 GRAB_CLA1:2;                 // 29:28 Grab CLA1
    Uint16 rsvd2:2;                     // 31:30 Reserved
};

union Z2_GRABRAMR_REG {
    Uint32  all;
    struct  Z2_GRABRAMR_BITS  bit;
};

struct Z2_EXEONLYSECTR_BITS {           // bits description
    Uint16 EXEONLY_SECTA:1;             // 0 Execute-Only Flash Sector A
    Uint16 EXEONLY_SECTB:1;             // 1 Execute-Only Flash Sector B
    Uint16 EXEONLY_SECTC:1;             // 2 Execute-Only Flash Sector C
    Uint16 EXEONLY_SECTD:1;             // 3 Execute-Only Flash Sector D 
    Uint16 EXEONLY_SECTE:1;             // 4 Execute-Only Flash Sector E
    Uint16 EXEONLY_SECTF:1;             // 5 Execute-Only Flash Sector F 
    Uint16 EXEONLY_SECTG:1;             // 6 Execute-Only Flash Sector G 
    Uint16 EXEONLY_SECTH:1;             // 7 Execute-Only Flash Sector H
    Uint16 EXEONLY_SECTI:1;             // 8 Execute-Only Flash Sector I
    Uint16 EXEONLY_SECTJ:1;             // 9 Execute-Only Flash Sector J
    Uint16 EXEONLY_SECTK:1;             // 10 Execute-Only Flash Sector K
    Uint16 EXEONLY_SECTL:1;             // 11 Execute-Only Flash Sector L
    Uint16 EXEONLY_SECTM:1;             // 12 Execute-Only Flash Sector M
    Uint16 EXEONLY_SECTN:1;             // 13 Execute-Only Flash Sector N
    Uint16 EXEONLY_BANK1:1;             // 14 Execute-Only Flash BANK1
    Uint16 rsvd1:1;                     // 15 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union Z2_EXEONLYSECTR_REG {
    Uint32  all;
    struct  Z2_EXEONLYSECTR_BITS  bit;
};

struct Z2_EXEONLYRAMR_BITS {            // bits description
    Uint16 EXEONLY_RAM0:1;              // 0 Execute-Only RAM LS0
    Uint16 EXEONLY_RAM1:1;              // 1 Execute-Only RAM LS1
    Uint16 EXEONLY_RAM2:1;              // 2 Execute-Only RAM LS2
    Uint16 EXEONLY_RAM3:1;              // 3 Execute-Only RAM LS3
    Uint16 EXEONLY_RAM4:1;              // 4 Execute-Only RAM LS4
    Uint16 EXEONLY_RAM5:1;              // 5 Execute-Only RAM LS5
    Uint16 EXEONLY_RAM6:1;              // 6 Execute-Only RAM D0
    Uint16 EXEONLY_RAM7:1;              // 7 Execute-Only RAM D1
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union Z2_EXEONLYRAMR_REG {
    Uint32  all;
    struct  Z2_EXEONLYRAMR_BITS  bit;
};

struct DCSM_Z2_REGS {
    union   Z2_LINKPOINTER_REG               Z2_LINKPOINTER;               // Zone 2 Link Pointer
    union   Z2_OTPSECLOCK_REG                Z2_OTPSECLOCK;                // Zone 2 OTP Secure JTAG lock
    union   Z2_BOOTCTRL_REG                  Z2_BOOTCTRL;                  // Boot Mode
    Uint32                                   Z2_LINKPOINTERERR;            // Link Pointer Error
    Uint16                                   rsvd1[8];                     // Reserved
    Uint32                                   Z2_CSMKEY0;                   // Zone 2 CSM Key 0
    Uint32                                   Z2_CSMKEY1;                   // Zone 2 CSM Key 1
    Uint32                                   Z2_CSMKEY2;                   // Zone 2 CSM Key 2
    Uint32                                   Z2_CSMKEY3;                   // Zone 2 CSM Key 3
    Uint16                                   rsvd2;                        // Reserved
    union   Z2_CR_REG                        Z2_CR;                        // Zone 2 CSM Control Register
    union   Z2_GRABSECTR_REG                 Z2_GRABSECTR;                 // Zone 2 Grab Flash Sectors Register
    union   Z2_GRABRAMR_REG                  Z2_GRABRAMR;                  // Zone 2 Grab RAM Blocks Register
    union   Z2_EXEONLYSECTR_REG              Z2_EXEONLYSECTR;              // Zone 2 Flash Execute_Only Sector Register
    union   Z2_EXEONLYRAMR_REG               Z2_EXEONLYRAMR;               // Zone 2 RAM Execute_Only Block Register
    Uint16                                   rsvd3;                        // Reserved
};

struct FLSEM_BITS {                     // bits description
    Uint16 SEM:2;                       // 1:0 Flash Semaphore Bit
    Uint16 rsvd1:6;                     // 7:2 Reserved
    Uint16 KEY:8;                       // 15:8 Semaphore Key
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FLSEM_REG {
    Uint32  all;
    struct  FLSEM_BITS  bit;
};

struct SECTSTAT_BITS {                  // bits description
    Uint16 STATUS_SECTA:2;              // 1:0 Zone Status Flash Sector A
    Uint16 STATUS_SECTB:2;              // 3:2 Zone Status Flash Sector B
    Uint16 STATUS_SECTC:2;              // 5:4 Zone Status Flash Sector C
    Uint16 STATUS_SECTD:2;              // 7:6 Zone Status Flash Sector D 
    Uint16 STATUS_SECTE:2;              // 9:8 Zone Status Flash Sector E
    Uint16 STATUS_SECTF:2;              // 11:10 Zone Status Flash Sector F 
    Uint16 STATUS_SECTG:2;              // 13:12 Zone Status Flash Sector G 
    Uint16 STATUS_SECTH:2;              // 15:14 Zone Status Flash Sector H
    Uint16 STATUS_SECTI:2;              // 17:16 Zone Status Flash Sector I
    Uint16 STATUS_SECTJ:2;              // 19:18 Zone Status Flash Sector J
    Uint16 STATUS_SECTK:2;              // 21:20 Zone Status Flash Sector K
    Uint16 STATUS_SECTL:2;              // 23:22 Zone Status Flash Sector L
    Uint16 STATUS_SECTM:2;              // 25:24 Zone Status Flash Sector M
    Uint16 STATUS_SECTN:2;              // 27:26 Zone Status Flash Sector N
    Uint16 STATUS_BANK1:2;              // 29:28 Zone Status Flash BANK1
    Uint16 rsvd1:2;                     // 31:30 Reserved
};

union SECTSTAT_REG {
    Uint32  all;
    struct  SECTSTAT_BITS  bit;
};

struct RAMSTAT_BITS {                   // bits description
    Uint16 STATUS_RAM0:2;               // 1:0 Zone Status RAM LS0
    Uint16 STATUS_RAM1:2;               // 3:2 Zone Status RAM LS1
    Uint16 STATUS_RAM2:2;               // 5:4 Zone Status RAM LS2
    Uint16 STATUS_RAM3:2;               // 7:6 Zone Status RAM LS3
    Uint16 STATUS_RAM4:2;               // 9:8 Zone Status RAM LS4
    Uint16 STATUS_RAM5:2;               // 11:10 Zone Status RAM LS5
    Uint16 STATUS_RAM6:2;               // 13:12 Zone Status RAM D0
    Uint16 STATUS_RAM7:2;               // 15:14 Zone Status RAM D1
    Uint16 rsvd1:12;                    // 27:16 Reserved
    Uint16 STATUS_CLA1:2;               // 29:28 Zone Status CLA1
    Uint16 rsvd2:2;                     // 31:30 Reserved
};

union RAMSTAT_REG {
    Uint32  all;
    struct  RAMSTAT_BITS  bit;
};

struct DCSM_COMMON_REGS {
    union   FLSEM_REG                        FLSEM;                        // Flash Wrapper Semaphore Register
    union   SECTSTAT_REG                     SECTSTAT;                     // Sectors Status Register
    union   RAMSTAT_REG                      RAMSTAT;                      // RAM Status Register
    Uint16                                   rsvd1[2];                     // Reserved
};

//---------------------------------------------------------------------------
// DCSM External References & Function Declarations:
//
extern volatile struct DCSM_Z1_REGS DcsmZ1Regs;
extern volatile struct DCSM_Z2_REGS DcsmZ2Regs;
extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_dma.h
//
// TITLE:  F2807x Device DMA Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// DMA Individual Register Bit Definitions:

struct MODE_BITS {     // bits description
	Uint16	PERINTSEL:5;		// 4:0	Peripheral Interrupt and Sync Select
	Uint16	rsvd1:2;			// 6:5	Reserved
	Uint16	OVRINTE:1;			// 7	Overflow Interrupt Enable
	Uint16	PERINTE:1;			// 8	Peripheral Interrupt Enable
	Uint16	CHINTMODE:1;		// 9	Channel Interrupt Mode
	Uint16	ONESHOT:1;			// 10	One Shot Mode Bit
	Uint16	CONTINUOUS:1;		// 11	Continuous Mode Bit
	Uint16	rsvd2:2;			// 13:12	Reserved
	Uint16	DATASIZE:1;			// 14	Data Size Mode Bit
	Uint16	CHINTE:1;			// 15	Channel Interrupt Enable Bit
};

union MODE_REG {
	Uint16 all;
	struct MODE_BITS	bit;
};

struct CONTROL_BITS {     // bits description
	Uint16	RUN:1;			// 0	Run Bit
	Uint16	HALT:1;			// 1	Halt Bit
	Uint16	SOFTRESET:1;	// 2	Soft Reset Bit
	Uint16	PERINTFRC:1;	// 3	Interrupt Force Bit
	Uint16	PERINTCLR:1;	// 4	Interrupt Clear Bit
	Uint16	rsvd2:2;		// 6:5	Reserved
	Uint16	ERRCLR:1;		// 7	Error Clear Bit
	Uint16	PERINTFLG:1;	// 8	Interrupt Flag Bit
	Uint16	SYNCFLG:1;		// 9	Sync Flag Bit
	Uint16	SYNCERR:1;		// 10	Sync Error Flag Bit
	Uint16	TRANSFERSTS:1;	// 11	Transfer Status Bit
	Uint16	BURSTSTS:1;		// 12	Burst Status Bit
	Uint16	RUNSTS:1;		// 13	Run Status Bit
	Uint16	OVRFLG:1;		// 14	Overflow Flag Bit
	Uint16	rsvd1:1;		// 15	Reserved
};

union CONTROL_REG {
	Uint16 all;
	struct CONTROL_BITS	bit;
};

struct DMACTRL_BITS {     // bits description
	Uint16	HARDRESET:1;			// 0	Hard Reset Bit
	Uint16	PRIORITYRESET:1;		// 1	Priority Reset Bit
	Uint16	rsvd1:14;				// 15:2	Reserved
};

union DMACTRL_REG {
	Uint16 all;
	struct DMACTRL_BITS	bit;
};

struct DEBUGCTRL_BITS {     // bits description
	Uint16	rsvd1:15;		// 14:0	Reserved
	Uint16	FREE:1;			// 15	Debug Mode Bit
};

union DEBUGCTRL_REG {
	Uint16 all;
	struct DEBUGCTRL_BITS	bit;
};

struct PRIORITYCTRL1_BITS {     // bits description
	Uint16	CH1PRIORITY:1;		// 0	Ch1 Priority Bit
	Uint16	rsvd1:15;			// 15:1	Reserved
};

union PRIORITYCTRL1_REG {
	Uint16 all;
	struct PRIORITYCTRL1_BITS	bit;
};

struct PRIORITYSTAT_BITS {     // bits description
	Uint16	ACTIVESTS:3;		// 2:0	Active Channel Status Bits
	Uint16	rsvd1:1;			// 3	Reserved
	Uint16	ACTIVESTS_SHADOW:3;	// 6:4	Active Channel Status Shadow Bits
	Uint16	rsvd2:9;			// 15:7	Reserved
};

union PRIORITYSTAT_REG {
	Uint16 all;
	struct PRIORITYSTAT_BITS	bit;
};

struct BURST_SIZE_BITS {     // bits description
	Uint16	BURSTSIZE:5;		// 4:0	Burst Transfer Size
	Uint16	rsvd1:11;			// 15:5	Reserved
};

union BURST_SIZE_REG {
	Uint16 all;
	struct BURST_SIZE_BITS	bit;
};

struct BURST_COUNT_BITS {     // bits description
	Uint16	BURSTCOUNT:5;		// 4:0	Burst Transfer Count
	Uint16	rsvd1:11;			// 15:5	Reserved
};

union BURST_COUNT_REG {
	Uint16 all;
	struct BURST_COUNT_BITS	bit;
};

struct CH_REGS {
	union	MODE_REG		MODE;					// Mode Register
	union	CONTROL_REG		CONTROL;				// Control Register
	union	BURST_SIZE_REG	BURST_SIZE;				// Burst Size Register
	union	BURST_COUNT_REG	BURST_COUNT;			// Burst Count Register
	int16					SRC_BURST_STEP;			// Source Burst Step Register
	int16					DST_BURST_STEP;			// Destination Burst Step Register
	Uint16					TRANSFER_SIZE;			// Transfer Size Register
	Uint16					TRANSFER_COUNT;			// Transfer Count Register
	int16					SRC_TRANSFER_STEP;		// Source Transfer Step Register
	int16					DST_TRANSFER_STEP;		// Destination Transfer Step Register
	Uint16					SRC_WRAP_SIZE;			// Source Wrap Size Register
	Uint16					SRC_WRAP_COUNT;			// Source Wrap Count Register
	int16					SRC_WRAP_STEP;			// Source Wrap Step Register
	Uint16					DST_WRAP_SIZE;			// Destination Wrap Size Register
	Uint16					DST_WRAP_COUNT;			// Destination Wrap Count Register
	int16					DST_WRAP_STEP;			// Destination Wrap Step Register
	Uint32					SRC_BEG_ADDR_SHADOW;	// Source Begin Address Shadow Register
	Uint32					SRC_ADDR_SHADOW;		// Source Address Shadow Register
	Uint32					SRC_BEG_ADDR_ACTIVE;	// Source Begin Address Active Register
	Uint32					SRC_ADDR_ACTIVE;		// Source Address Active Register
	Uint32					DST_BEG_ADDR_SHADOW;	// Destination Begin Address Shadow Register
	Uint32					DST_ADDR_SHADOW;		// Destination Address Shadow Register
	Uint32					DST_BEG_ADDR_ACTIVE;		// Destination Begin Address Active Register
	Uint32					DST_ADDR_ACTIVE;		// Destination Address Active Register
};

struct DMA_REGS {
	union	DMACTRL_REG			DMACTRL;		// DMA Control Register
	union	DEBUGCTRL_REG		DEBUGCTRL;		// Debug Control Register
	Uint16						rsvd0;			// Reserved
	Uint16						rsvd1;			// Reserved
	union	PRIORITYCTRL1_REG	PRIORITYCTRL1;	// Priority Control 1 Register
	Uint16						rsvd2;			// Reserved
	union	PRIORITYSTAT_REG	PRIORITYSTAT;	// Priority Status Register
	Uint16						rsvd3[25];		// Reserved
	struct CH_REGS             	CH1;            // DMA Channel 1 Registers
	struct CH_REGS             	CH2;            // DMA Channel 2 Registers
	struct CH_REGS             	CH3;            // DMA Channel 3 Registers
	struct CH_REGS             	CH4;            // DMA Channel 4 Registers
	struct CH_REGS             	CH5;            // DMA Channel 5 Registers
	struct CH_REGS             	CH6;            // DMA Channel 6 Registers
};

//---------------------------------------------------------------------------
// DMA External References & Function Declarations:
//
extern volatile struct DMA_REGS DmaRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   can.h
//
// TITLE:  Defines and Macros for the CAN controller.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//! \addtogroup can_api
//! @{
//*****************************************************************************

//*****************************************************************************
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//*****************************************************************************
extern "C"
{





//****************************************************************************
//   These are the Defines to select CAN pin muxing when calling the functions
//  ConfigCanPinMuxing(), ConfigGpioCanA() & ConfigGpioCanB() in F2837x_Can.c
//****************************************************************************


//*****************************************************************************
// Miscellaneous defines for Message ID Types
//*****************************************************************************

//*****************************************************************************
// These are the flags used by the tCANMsgObject.ui32Flags value when calling the
// CANMessageSet() and CANMessageGet() functions.
//*****************************************************************************

//! This definition is used with the tCANMsgObject ui32Flags value and indicates
//! that transmit interrupts should be enabled, or are enabled.

//! This indicates that receive interrupts should be enabled, or are
//! enabled.

//! This indicates that a message object will use or is using an extended
//! identifier.

//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.

//! This indicates that new data was available in the message object.

//! This indicates that data was lost since this message object was last
//! read.

//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer.  If the direction filtering is
//! used, then ID filtering must also be enabled.

//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier.  If the extended
//! identifier filtering is used, then ID filtering must also be enabled.

//! This indicates that a message object is a remote frame.

//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.

//! This indicates that a message object has no flags set.

//*****************************************************************************
//! This define is used with the flag values to allow checking only status
//! flags and not configuration flags.
//*****************************************************************************

//*****************************************************************************
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//*****************************************************************************
typedef struct
{
        //! The CAN message identifier used for 11 or 29 bit identifiers.
        uint32_t ui32MsgID;

        //! The message identifier mask used when identifier filtering is enabled.
        uint32_t ui32MsgIDMask;

        //! This value holds various status flags and settings specified by
        //! tCANObjFlags.
        uint32_t ui32Flags;

        //! This value is the number of bytes of data in the message object.
        uint32_t ui32MsgLen;

        //! This is a pointer to the message object's data.
        unsigned char  *pucMsgData;
}
tCANMsgObject;

//*****************************************************************************
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller.  The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//*****************************************************************************
typedef struct
{
        //! This value holds the sum of the Synchronization, Propagation, and Phase
        //! Buffer 1 segments, measured in time quanta.  The valid values for this
        //! setting range from 2 to 16.
        uint16_t  uSyncPropPhase1Seg;

        //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
        //! values for this setting range from 1 to 8.
        uint16_t  uPhase2Seg;

        //! This value holds the Resynchronization Jump Width in time quanta.  The
        //! valid values for this setting range from 1 to 4.
        uint16_t  uSJW;

        //! This value holds the CAN_CLK divider used to determine time quanta.
        //! The valid values for this setting range from 1 to 1023.
        uint16_t  uQuantumPrescaler;
}
tCANBitClkParms;

//*****************************************************************************
//! This data type is used to identify the interrupt status register.  This is
//! used when calling the CANIntStatus() function.
//*****************************************************************************
typedef enum
{
        //! Read the CAN interrupt status information.
        CAN_INT_STS_CAUSE,

        //! Read a message object's interrupt status.
        CAN_INT_STS_OBJECT
}
tCANIntStsReg;

//*****************************************************************************
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//*****************************************************************************
typedef enum
{
        //! Read the full CAN controller status.
        CAN_STS_CONTROL,

        //! Read the full 32-bit mask of message objects with a transmit request
        //! set.
        CAN_STS_TXREQUEST,

        //! Read the full 32-bit mask of message objects with new data available.
        CAN_STS_NEWDAT,

        //! Read the full 32-bit mask of message objects that are enabled.
        CAN_STS_MSGVAL
}
tCANStsReg;

//*****************************************************************************
// These definitions are used to specify interrupt sources to CANIntEnable()
// and CANIntDisable().
//*****************************************************************************
//! This flag is used to allow a CAN controller to generate error
//! interrupts.

//! This flag is used to allow a CAN controller to generate status
//! interrupts.

//! This flag is used to allow a CAN controller to generate interrupts
//! on interrupt line 0

//! This flag is used to allow a CAN controller to generate interrupts
//! on interrupt line 1

// Defined to maintain compatibility with Stellaris Examples

//*****************************************************************************
// These definitions are used to specify the clock source to
// CANClkSourceSelect()
//*****************************************************************************
//! This flag is used to clock the CAN controller Selected CPU SYSCLKOUT
//! (CPU1.Sysclk or CPU2.Sysclk).

//! This flag is used to clock the CAN controller with the X1/X2 oscillator
//! clock.

//! This flag is used to clock the CAN controller with the clock from
//! AUXCLKIN (from GPIO)


//*****************************************************************************
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//*****************************************************************************
typedef enum
{
        //! Transmit message object.
        MSG_OBJ_TYPE_TX,

        //! Transmit remote request message object
        MSG_OBJ_TYPE_TX_REMOTE,

        //! Receive message object.
        MSG_OBJ_TYPE_RX,

        //! Receive remote request message object.
        MSG_OBJ_TYPE_RX_REMOTE,

        //! Remote frame receive remote, with auto-transmit message object.
        MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;

//*****************************************************************************
// The following enumeration contains all error or status indicators that can
// be returned when calling the CANStatusGet() function.
//*****************************************************************************
//! CAN controller is in local power down mode.

//! CAN controller has initiated a system wakeup.

//! CAN controller has detected a parity error.

//! CAN controller has entered a Bus Off state.

//! CAN controller error level has reached warning level.

//! CAN controller error level has reached error passive level.

//! A message was received successfully since the last read of this status.

//! A message was transmitted successfully since the last read of this
//! status.

//! This is the mask for the last error code field.

//! There was no error.

//! A bit stuffing error has occurred.

//! A formatting error has occurred.

//! An acknowledge error has occurred.

//! The bus remained a bit level of 1 for longer than is allowed.

//! The bus remained a bit level of 0 for longer than is allowed.

//! A CRC error has occurred.

//*****************************************************************************
// The following macros are added for the new Global Interrupt EN/FLG/CLR
// register
//*****************************************************************************
//CANINT0 global interrupt bit

//CANINT1 global interrupt bit

//*****************************************************************************
// The following macros are missing in hw_can.h because of scripting
// but driverlib can.c needs them
//*****************************************************************************




//*****************************************************************************
// API Function prototypes
//*****************************************************************************
extern void CANClkSourceSelect(uint32_t ui32Base, uint16_t  ucSource);
extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
                              uint32_t ui32BitRate);
extern void CANDisable(uint32_t ui32Base);
extern void CANEnable(uint32_t ui32Base);
extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
                          uint32_t *pui32TxCount);
extern void CANInit(uint32_t ui32Base);
extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber,
                           void (*pfnHandler)(void));
extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber);
extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
                          tCANMsgObject *pMsgObject, bool bClrPendingInt);
extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
                          tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern bool CANRetryGet(uint32_t ui32Base);
extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
extern void CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern bool CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags);




//*****************************************************************************
// Mark the end of the C bindings section for C++ compilers.
//*****************************************************************************
}

//*****************************************************************************
// Close the Doxygen group.
//! @}
//*****************************************************************************




//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_ecap.h
//
// TITLE:   F2807x Device ECAP Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// ECAP Individual Register Bit Definitions:

struct ECCTL1_BITS {                    // bits description
    Uint16 CAP1POL:1;                   // 0 Capture Event 1 Polarity select
    Uint16 CTRRST1:1;                   // 1 Counter Reset on Capture Event 1 
    Uint16 CAP2POL:1;                   // 2 Capture Event 2 Polarity select 
    Uint16 CTRRST2:1;                   // 3 Counter Reset on Capture Event 2 
    Uint16 CAP3POL:1;                   // 4 Capture Event 3 Polarity select 
    Uint16 CTRRST3:1;                   // 5 Counter Reset on Capture Event 3 
    Uint16 CAP4POL:1;                   // 6 Capture Event 4 Polarity select 
    Uint16 CTRRST4:1;                   // 7 Counter Reset on Capture Event 4 
    Uint16 CAPLDEN:1;                   // 8 Enable Loading CAP1-4 regs on a Cap Event 
    Uint16 PRESCALE:5;                  // 13:9 Event Filter prescale select 
    Uint16 FREE_SOFT:2;                 // 15:14 Emulation mode 
};

union ECCTL1_REG {
    Uint16  all;
    struct  ECCTL1_BITS  bit;
};

struct ECCTL2_BITS {                    // bits description
    Uint16 CONT_ONESHT:1;               // 0 Continuous or one-shot 
    Uint16 STOP_WRAP:2;                 // 2:1 Stop value for one-shot, Wrap for continuous
    Uint16 REARM:1;                     // 3 One-shot re-arm 
    Uint16 TSCTRSTOP:1;                 // 4 TSCNT counter stop 
    Uint16 SYNCI_EN:1;                  // 5 Counter sync-in select
    Uint16 SYNCO_SEL:2;                 // 7:6 Sync-out mode 
    Uint16 SWSYNC:1;                    // 8 SW forced counter sync 
    Uint16 CAP_APWM:1;                  // 9 CAP/APWM operating mode select 
    Uint16 APWMPOL:1;                   // 10  APWM output polarity select 
    Uint16 rsvd1:5;                     // 15:11 Reserved
};

union ECCTL2_REG {
    Uint16  all;
    struct  ECCTL2_BITS  bit;
};

struct ECEINT_BITS {                    // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CEVT1:1;                     // 1 Capture Event 1 Interrupt Enable 
    Uint16 CEVT2:1;                     // 2 Capture Event 2 Interrupt Enable 
    Uint16 CEVT3:1;                     // 3 Capture Event 3 Interrupt Enable 
    Uint16 CEVT4:1;                     // 4 Capture Event 4 Interrupt Enable 
    Uint16 CTROVF:1;                    // 5 Counter Overflow Interrupt Enable 
    Uint16 CTR_EQ_PRD:1;                // 6 Period Equal Interrupt Enable
    Uint16 CTR_EQ_CMP:1;                // 7 Compare Equal Interrupt Enable 
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union ECEINT_REG {
    Uint16  all;
    struct  ECEINT_BITS  bit;
};

struct ECFLG_BITS {                     // bits description
    Uint16 INT:1;                       // 0 Global Flag 
    Uint16 CEVT1:1;                     // 1 Capture Event 1 Interrupt Flag 
    Uint16 CEVT2:1;                     // 2 Capture Event 2 Interrupt Flag 
    Uint16 CEVT3:1;                     // 3 Capture Event 3 Interrupt Flag 
    Uint16 CEVT4:1;                     // 4 Capture Event 4 Interrupt Flag 
    Uint16 CTROVF:1;                    // 5 Counter Overflow Interrupt Flag 
    Uint16 CTR_PRD:1;                   // 6 Period Equal Interrupt Flag 
    Uint16 CTR_CMP:1;                   // 7 Compare Equal Interrupt Flag
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union ECFLG_REG {
    Uint16  all;
    struct  ECFLG_BITS  bit;
};

struct ECCLR_BITS {                     // bits description
    Uint16 INT:1;                       // 0 ECAP Global Interrupt Status Clear
    Uint16 CEVT1:1;                     // 1 Capture Event 1 Status Clear
    Uint16 CEVT2:1;                     // 2 Capture Event 2 Status Clear
    Uint16 CEVT3:1;                     // 3 Capture Event 3 Status Clear
    Uint16 CEVT4:1;                     // 4 Capture Event 4 Status Clear
    Uint16 CTROVF:1;                    // 5 Counter Overflow Status Clear
    Uint16 CTR_PRD:1;                   // 6 Period Equal Status Clear
    Uint16 CTR_CMP:1;                   // 7 Compare Equal Status Clear 
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union ECCLR_REG {
    Uint16  all;
    struct  ECCLR_BITS  bit;
};

struct ECFRC_BITS {                     // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CEVT1:1;                     // 1 Capture Event 1 Force Interrupt 
    Uint16 CEVT2:1;                     // 2 Capture Event 2 Force Interrupt 
    Uint16 CEVT3:1;                     // 3 Capture Event 3 Force Interrupt 
    Uint16 CEVT4:1;                     // 4 Capture Event 4 Force Interrupt 
    Uint16 CTROVF:1;                    // 5 Counter Overflow Force Interrupt 
    Uint16 CTR_PRD:1;                   // 6 Period Equal Force Interrupt
    Uint16 CTR_CMP:1;                   // 7 Compare Equal Force Interrupt 
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union ECFRC_REG {
    Uint16  all;
    struct  ECFRC_BITS  bit;
};

struct ECAP_REGS {
    Uint32                                   TSCTR;                        // Time-Stamp Counter
    Uint32                                   CTRPHS;                       // Counter Phase Offset Value Register
    Uint32                                   CAP1;                         // Capture 1 Register
    Uint32                                   CAP2;                         // Capture 2 Register
    Uint32                                   CAP3;                         // Capture 3 Register
    Uint32                                   CAP4;                         // Capture 4 Register
    Uint16                                   rsvd1[8];                     // Reserved
    union   ECCTL1_REG                       ECCTL1;                       // Capture Control Register 1
    union   ECCTL2_REG                       ECCTL2;                       // Capture Control Register 2
    union   ECEINT_REG                       ECEINT;                       // Capture Interrupt Enable Register
    union   ECFLG_REG                        ECFLG;                        // Capture Interrupt Flag Register
    union   ECCLR_REG                        ECCLR;                        // Capture Interrupt Clear Register
    union   ECFRC_REG                        ECFRC;                        // Capture Interrupt Force Register
    Uint16                                   rsvd2[6];                     // Reserved
};

//---------------------------------------------------------------------------
// ECAP External References & Function Declarations:
//
extern volatile struct ECAP_REGS ECap1Regs;
extern volatile struct ECAP_REGS ECap2Regs;
extern volatile struct ECAP_REGS ECap3Regs;
extern volatile struct ECAP_REGS ECap4Regs;
extern volatile struct ECAP_REGS ECap5Regs;
extern volatile struct ECAP_REGS ECap6Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_emif.h
//
// TITLE:   F2807x Device EMIF Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// EMIF Individual Register Bit Definitions:

struct RCSR_BITS {                      // bits description
    Uint16 MINOR_REVISION:8;            // 7:0 Minor Revision. 
    Uint16 MAJOR_REVISION:8;            // 15:8 Major Revision. 
    Uint16 MODULE_ID:14;                // 29:16 EMIF module ID.
    Uint16 FR:1;                        // 30 EMIF is running in full rate or half rate.
    Uint16 BE:1;                        // 31 EMIF endian mode.
};

union RCSR_REG {
    Uint32  all;
    struct  RCSR_BITS  bit;
};

struct ASYNC_WCCR_BITS {                // bits description
    Uint16 MAX_EXT_WAIT:8;              // 7:0 Maximum Extended Wait cycles.
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:2;                     // 17:16 Reserved
    Uint16 rsvd3:2;                     // 19:18 Reserved
    Uint16 rsvd4:2;                     // 21:20 Reserved
    Uint16 rsvd5:2;                     // 23:22 Reserved
    Uint16 rsvd6:4;                     // 27:24 Reserved
    Uint16 WP0:1;                       // 28  Polarity for EMxWAIT.
    Uint16 rsvd7:1;                     // 29 Reserved
    Uint16 rsvd8:1;                     // 30 Reserved
    Uint16 rsvd9:1;                     // 31 Reserved
};

union ASYNC_WCCR_REG {
    Uint32  all;
    struct  ASYNC_WCCR_BITS  bit;
};

struct SDRAM_CR_BITS {                  // bits description
    Uint16 PAGESIGE:3;                  // 2:0 Page Size.
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 IBANK:3;                     // 6:4 Internal Bank setup of SDRAM devices.
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 BIT_11_9_LOCK:1;             // 8 Bits 11 to 9 are writable only if this bit is set.
    Uint16 CL:3;                        // 11:9 CAS Latency.
    Uint16 rsvd3:1;                     // 12 Reserved
    Uint16 rsvd4:1;                     // 13 Reserved
    Uint16 NM:1;                        // 14 Narrow Mode.
    Uint16 rsvd5:1;                     // 15 Reserved
    Uint16 rsvd6:1;                     // 16 Reserved
    Uint16 rsvd7:2;                     // 18:17 Reserved
    Uint16 rsvd8:1;                     // 19 Reserved
    Uint16 rsvd9:3;                     // 22:20 Reserved
    Uint16 rsvd10:3;                    // 25:23 Reserved
    Uint16 rsvd11:3;                    // 28:26 Reserved
    Uint16 PDWR:1;                      // 29 Perform refreshes during Power Down.
    Uint16 PD:1;                        // 30 Power Down.
    Uint16 SR:1;                        // 31 Self Refresh.
};

union SDRAM_CR_REG {
    Uint32  all;
    struct  SDRAM_CR_BITS  bit;
};

struct SDRAM_RCR_BITS {                 // bits description
    Uint16 REFRESH_RATE:13;             // 12:0 Refresh Rate.
    Uint16 rsvd1:3;                     // 15:13 Reserved
    Uint16 rsvd2:3;                     // 18:16 Reserved
    Uint16 rsvd3:13;                    // 31:19 Reserved
};

union SDRAM_RCR_REG {
    Uint32  all;
    struct  SDRAM_RCR_BITS  bit;
};

struct ASYNC_CS2_CR_BITS {              // bits description
    Uint16 ASIZE:2;                     // 1:0 Asynchronous Memory Size.
    Uint16 TA:2;                        // 3:2 Turn Around cycles.
    Uint16 R_HOLD:3;                    // 6:4 Read Strobe Hold cycles.
    Uint16 R_STROBE:6;                  // 12:7 Read Strobe Duration cycles.
    Uint32 R_SETUP:4;                   // 16:13 Read Strobe Setup cycles.
    Uint16 W_HOLD:3;                    // 19:17 Write Strobe Hold cycles.
    Uint16 W_STROBE:6;                  // 25:20 Write Strobe Duration cycles.
    Uint16 W_SETUP:4;                   // 29:26 Write Strobe Setup cycles.
    Uint16 EW:1;                        // 30 Extend Wait mode.
    Uint16 SS:1;                        // 31 Select Strobe mode.
};

union ASYNC_CS2_CR_REG {
    Uint32  all;
    struct  ASYNC_CS2_CR_BITS  bit;
};

struct ASYNC_CS3_CR_BITS {              // bits description
    Uint16 ASIZE:2;                     // 1:0 Asynchronous Memory Size.
    Uint16 TA:2;                        // 3:2 Turn Around cycles.
    Uint16 R_HOLD:3;                    // 6:4 Read Strobe Hold cycles.
    Uint16 R_STROBE:6;                  // 12:7 Read Strobe Duration cycles.
    Uint32 R_SETUP:4;                   // 16:13 Read Strobe Setup cycles.
    Uint16 W_HOLD:3;                    // 19:17 Write Strobe Hold cycles.
    Uint16 W_STROBE:6;                  // 25:20 Write Strobe Duration cycles.
    Uint16 W_SETUP:4;                   // 29:26 Write Strobe Setup cycles.
    Uint16 EW:1;                        // 30 Extend Wait mode.
    Uint16 SS:1;                        // 31 Select Strobe mode.
};

union ASYNC_CS3_CR_REG {
    Uint32  all;
    struct  ASYNC_CS3_CR_BITS  bit;
};

struct ASYNC_CS4_CR_BITS {              // bits description
    Uint16 ASIZE:2;                     // 1:0 Asynchronous Memory Size.
    Uint16 TA:2;                        // 3:2 Turn Around cycles.
    Uint16 R_HOLD:3;                    // 6:4 Read Strobe Hold cycles.
    Uint16 R_STROBE:6;                  // 12:7 Read Strobe Duration cycles.
    Uint32 R_SETUP:4;                   // 16:13 Read Strobe Setup cycles.
    Uint16 W_HOLD:3;                    // 19:17 Write Strobe Hold cycles.
    Uint16 W_STROBE:6;                  // 25:20 Write Strobe Duration cycles.
    Uint16 W_SETUP:4;                   // 29:26 Write Strobe Setup cycles.
    Uint16 EW:1;                        // 30 Extend Wait mode.
    Uint16 SS:1;                        // 31 Select Strobe mode.
};

union ASYNC_CS4_CR_REG {
    Uint32  all;
    struct  ASYNC_CS4_CR_BITS  bit;
};

struct SDRAM_TR_BITS {                  // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 T_RRD:3;                     // 6:4 Activate to Activate timing for different bank.
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 T_RC:4;                      // 11:8 Activate to Activate timing .
    Uint16 T_RAS:4;                     // 15:12 Activate to Precharge timing.
    Uint16 T_WR:3;                      // 18:16 Last Write to Precharge timing.
    Uint16 rsvd3:1;                     // 19 Reserved
    Uint16 T_RCD:3;                     // 22:20 Activate to Read/Write timing.
    Uint16 rsvd4:1;                     // 23 Reserved
    Uint16 T_RP:3;                      // 26:24 Precharge to Activate/Refresh timing.
    Uint16 T_RFC:5;                     // 31:27 Refresh/Load Mode to Refresh/Activate timing
};

union SDRAM_TR_REG {
    Uint32  all;
    struct  SDRAM_TR_BITS  bit;
};

struct SDR_EXT_TMNG_BITS {              // bits description
    Uint16 T_XS:5;                      // 4:0 Self Refresh exit to new command timing.
    Uint16 rsvd1:11;                    // 15:5 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SDR_EXT_TMNG_REG {
    Uint32  all;
    struct  SDR_EXT_TMNG_BITS  bit;
};

struct INT_RAW_BITS {                   // bits description
    Uint16 AT:1;                        // 0 Asynchronous Timeout.
    Uint16 LT:1;                        // 1 Line Trap.
    Uint16 WR:4;                        // 5:2 Wait Rise.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union INT_RAW_REG {
    Uint32  all;
    struct  INT_RAW_BITS  bit;
};

struct INT_MSK_BITS {                   // bits description
    Uint16 AT_MASKED:1;                 // 0 Asynchronous Timeout.
    Uint16 LT_MASKED:1;                 // 1 Line Trap.
    Uint16 WR_MASKED:4;                 // 5:2 Wait Rise.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union INT_MSK_REG {
    Uint32  all;
    struct  INT_MSK_BITS  bit;
};

struct INT_MSK_SET_BITS {               // bits description
    Uint16 AT_MASK_SET:1;               // 0 Asynchronous Timeout.
    Uint16 LT_MASK_SET:1;               // 1 Line Trap.
    Uint16 WR_MASK_SET:4;               // 5:2 Wait Rise.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union INT_MSK_SET_REG {
    Uint32  all;
    struct  INT_MSK_SET_BITS  bit;
};

struct INT_MSK_CLR_BITS {               // bits description
    Uint16 AT_MASK_CLR:1;               // 0 Asynchronous Timeout.
    Uint16 LT_MASK_CLR:1;               // 1 Line Trap.
    Uint16 WR_MASK_CLR:4;               // 5:2 Wait Rise.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union INT_MSK_CLR_REG {
    Uint32  all;
    struct  INT_MSK_CLR_BITS  bit;
};

struct EMIF_REGS {
    union   RCSR_REG                         RCSR;                         // Revision Code and Status Register
    union   ASYNC_WCCR_REG                   ASYNC_WCCR;                   // Async Wait Cycle Config Register
    union   SDRAM_CR_REG                     SDRAM_CR;                     // SDRAM (EMxCS0n) Config Register
    union   SDRAM_RCR_REG                    SDRAM_RCR;                    // SDRAM Refresh Control Register
    union   ASYNC_CS2_CR_REG                 ASYNC_CS2_CR;                 // Async 1 (EMxCS2n) Config Register
    union   ASYNC_CS3_CR_REG                 ASYNC_CS3_CR;                 // Async 2 (EMxCS3n) Config Register
    union   ASYNC_CS4_CR_REG                 ASYNC_CS4_CR;                 // Async 3 (EMxCS4n) Config Register
    Uint16                                   rsvd1[2];                     // Reserved
    union   SDRAM_TR_REG                     SDRAM_TR;                     // SDRAM Timing Register
    Uint16                                   rsvd2[6];                     // Reserved
    Uint32                                   TOTAL_SDRAM_AR;               // Total SDRAM Accesses Register
    Uint32                                   TOTAL_SDRAM_ACTR;             // Total SDRAM Activate Register
    Uint16                                   rsvd3[2];                     // Reserved
    union   SDR_EXT_TMNG_REG                 SDR_EXT_TMNG;                 // SDRAM SR/PD Exit Timing Register
    union   INT_RAW_REG                      INT_RAW;                      // Interrupt Raw Register
    union   INT_MSK_REG                      INT_MSK;                      // Interrupt Masked Register
    union   INT_MSK_SET_REG                  INT_MSK_SET;                  // Interrupt Mask Set Register
    union   INT_MSK_CLR_REG                  INT_MSK_CLR;                  // Interrupt Mask Clear Register
    Uint16                                   rsvd4[72];                    // Reserved
};

//---------------------------------------------------------------------------
// EMIF External References & Function Declarations:
//
extern volatile struct EMIF_REGS Emif1Regs;
extern volatile struct EMIF_REGS Emif2Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_epwm.h
//
// TITLE:   F2807x Device EPWM Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// EPWM Individual Register Bit Definitions:

struct TBCTL_BITS {                     // bits description
    Uint16 CTRMODE:2;                   // 1:0 Counter Mode
    Uint16 PHSEN:1;                     // 2 Phase Load Enable
    Uint16 PRDLD:1;                     // 3 Active Period Load
    Uint16 SYNCOSEL:2;                  // 5:4 Sync Output Select
    Uint16 SWFSYNC:1;                   // 6 Software Force Sync Pulse
    Uint16 HSPCLKDIV:3;                 // 9:7 High Speed TBCLK Pre-scaler
    Uint16 CLKDIV:3;                    // 12:10 Time Base Clock Pre-scaler
    Uint16 PHSDIR:1;                    // 13 Phase Direction Bit
    Uint16 FREE_SOFT:2;                 // 15:14 Emulation Mode Bits
};

union TBCTL_REG {
    Uint16  all;
    struct  TBCTL_BITS  bit;
};

struct TBCTL2_BITS {                    // bits description
    Uint16 rsvd1:5;                     // 4:0 Reserved
    Uint16 SELFCLRTRREM:1;              // 5 Self clear Translator reminder
    Uint16 OSHTSYNCMODE:1;              // 6 One shot sync mode
    Uint16 OSHTSYNC:1;                  // 7 One shot sync
    Uint16 rsvd2:4;                     // 11:8 Reserved
    Uint16 SYNCOSELX:2;                 // 13:12 Syncout selection
    Uint16 PRDLDSYNC:2;                 // 15:14 PRD Shadow to Active Load on SYNC Event
};

union TBCTL2_REG {
    Uint16  all;
    struct  TBCTL2_BITS  bit;
};

struct TBSTS_BITS {                     // bits description
    Uint16 CTRDIR:1;                    // 0 Counter Direction Status
    Uint16 SYNCI:1;                     // 1 External Input Sync Status
    Uint16 CTRMAX:1;                    // 2 Counter Max Latched Status
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union TBSTS_REG {
    Uint16  all;
    struct  TBSTS_BITS  bit;
};

struct CMPCTL_BITS {                    // bits description
    Uint16 LOADAMODE:2;                 // 1:0 Active Compare A Load
    Uint16 LOADBMODE:2;                 // 3:2 Active Compare B Load
    Uint16 SHDWAMODE:1;                 // 4 Compare A Register Block Operating Mode
    Uint16 rsvd1:1;                     // 5 Reserved
    Uint16 SHDWBMODE:1;                 // 6 Compare B Register Block Operating Mode
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 SHDWAFULL:1;                 // 8 Compare A Shadow Register Full Status
    Uint16 SHDWBFULL:1;                 // 9 Compare B Shadow Register Full Status
    Uint16 LOADASYNC:2;                 // 11:10 Active Compare A Load on SYNC
    Uint16 LOADBSYNC:2;                 // 13:12 Active Compare B Load on SYNC
    Uint16 rsvd3:2;                     // 15:14 Reserved
};

union CMPCTL_REG {
    Uint16  all;
    struct  CMPCTL_BITS  bit;
};

struct CMPCTL2_BITS {                   // bits description
    Uint16 LOADCMODE:2;                 // 1:0 Active Compare C Load
    Uint16 LOADDMODE:2;                 // 3:2 Active Compare D load
    Uint16 SHDWCMODE:1;                 // 4 Compare C Block Operating Mode
    Uint16 rsvd1:1;                     // 5 Reserved
    Uint16 SHDWDMODE:1;                 // 6 Compare D Block Operating Mode
    Uint16 rsvd2:3;                     // 9:7 Reserved
    Uint16 LOADCSYNC:2;                 // 11:10 Active Compare C Load on SYNC
    Uint16 LOADDSYNC:2;                 // 13:12 Active Compare D Load on SYNC
    Uint16 rsvd3:2;                     // 15:14 Reserved
};

union CMPCTL2_REG {
    Uint16  all;
    struct  CMPCTL2_BITS  bit;
};

struct DBCTL_BITS {                     // bits description
    Uint16 OUT_MODE:2;                  // 1:0 Dead Band Output Mode Control
    Uint16 POLSEL:2;                    // 3:2 Polarity Select Control
    Uint16 IN_MODE:2;                   // 5:4 Dead Band Input Select Mode Control
    Uint16 LOADREDMODE:2;               // 7:6 Active DBRED Load Mode
    Uint16 LOADFEDMODE:2;               // 9:8 Active DBFED Load Mode
    Uint16 SHDWDBREDMODE:1;             // 10 DBRED Block Operating Mode
    Uint16 SHDWDBFEDMODE:1;             // 11 DBFED Block Operating Mode
    Uint16 OUTSWAP:2;                   // 13:12 Dead Band Output Swap Control
    Uint16 DEDB_MODE:1;                 // 14 Dead Band Dual-Edge B Mode Control
    Uint16 HALFCYCLE:1;                 // 15 Half Cycle Clocking Enable
};

union DBCTL_REG {
    Uint16  all;
    struct  DBCTL_BITS  bit;
};

struct DBCTL2_BITS {                    // bits description
    Uint16 LOADDBCTLMODE:2;             // 1:0 DBCTL Load from Shadow Mode Select
    Uint16 SHDWDBCTLMODE:1;             // 2 DBCTL Load mode Select
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union DBCTL2_REG {
    Uint16  all;
    struct  DBCTL2_BITS  bit;
};

struct AQCTL_BITS {                     // bits description
    Uint16 LDAQAMODE:2;                 // 1:0 Action Qualifier A Load Select
    Uint16 LDAQBMODE:2;                 // 3:2 Action Qualifier B Load Select
    Uint16 SHDWAQAMODE:1;               // 4 Action Qualifer A Operating Mode
    Uint16 rsvd1:1;                     // 5 Reserved
    Uint16 SHDWAQBMODE:1;               // 6 Action Qualifier B Operating Mode
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 LDAQASYNC:2;                 // 9:8 AQCTLA Register Load on SYNC
    Uint16 LDAQBSYNC:2;                 // 11:10 AQCTLB Register Load on SYNC
    Uint16 rsvd3:4;                     // 15:12 Reserved
};

union AQCTL_REG {
    Uint16  all;
    struct  AQCTL_BITS  bit;
};

struct AQTSRCSEL_BITS {                 // bits description
    Uint16 T1SEL:4;                     // 3:0 T1 Event Source Select Bits
    Uint16 T2SEL:4;                     // 7:4 T2 Event Source Select Bits
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union AQTSRCSEL_REG {
    Uint16  all;
    struct  AQTSRCSEL_BITS  bit;
};

struct PCCTL_BITS {                     // bits description
    Uint16 CHPEN:1;                     // 0 PWM chopping enable
    Uint16 OSHTWTH:4;                   // 4:1 One-shot pulse width
    Uint16 CHPFREQ:3;                   // 7:5 Chopping clock frequency
    Uint16 CHPDUTY:3;                   // 10:8 Chopping clock Duty cycle
    Uint16 rsvd1:5;                     // 15:11 Reserved
};

union PCCTL_REG {
    Uint16  all;
    struct  PCCTL_BITS  bit;
};

struct HRCNFG_BITS {                    // bits description
    Uint16 EDGMODE:2;                   // 1:0 ePWMxA Edge Mode Select Bits
    Uint16 CTLMODE:1;                   // 2 ePWMxA Control Mode Select Bits
    Uint16 HRLOAD:2;                    // 4:3 ePWMxA Shadow Mode Select Bits
    Uint16 SELOUTB:1;                   // 5 EPWMB Output Selection Bit
    Uint16 AUTOCONV:1;                  // 6 Autoconversion Bit
    Uint16 SWAPAB:1;                    // 7 Swap EPWMA and EPWMB Outputs Bit
    Uint16 EDGMODEB:2;                  // 9:8 ePWMxB Edge Mode Select Bits
    Uint16 CTLMODEB:1;                  // 10 ePWMxB Control Mode Select Bits
    Uint16 HRLOADB:2;                   // 12:11 ePWMxB Shadow Mode Select Bits
    Uint16 rsvd1:1;                     // 13 Reserved
    Uint16 rsvd2:2;                     // 15:14 Reserved
};

union HRCNFG_REG {
    Uint16  all;
    struct  HRCNFG_BITS  bit;
};

struct HRPWR_BITS {                     // bits description
    Uint16 rsvd1:2;                     // 1:0 Reserved
    Uint16 rsvd2:1;                     // 2 Reserved
    Uint16 rsvd3:1;                     // 3 Reserved
    Uint16 rsvd4:1;                     // 4 Reserved
    Uint16 rsvd5:1;                     // 5 Reserved
    Uint16 rsvd6:4;                     // 9:6 Reserved
    Uint16 rsvd7:5;                     // 14:10 Reserved
    Uint16 CALPWRON:1;                  // 15 Calibration Power On
};

union HRPWR_REG {
    Uint16  all;
    struct  HRPWR_BITS  bit;
};

struct HRMSTEP_BITS {                   // bits description
    Uint16 HRMSTEP:8;                   // 7:0 High Resolution Micro Step Value
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union HRMSTEP_REG {
    Uint16  all;
    struct  HRMSTEP_BITS  bit;
};

struct HRCNFG2_BITS {                   // bits description
    Uint16 EDGMODEDB:2;                 // 1:0 Dead-Band Edge-Mode Select Bits
    Uint16 CTLMODEDBRED:2;              // 3:2 DBRED Control Mode Select Bits
    Uint16 CTLMODEDBFED:2;              // 5:4 DBFED Control Mode Select Bits
    Uint16 rsvd1:8;                     // 13:6 Reserved
    Uint16 rsvd2:1;                     // 14 Reserved
    Uint16 rsvd3:1;                     // 15 Reserved
};

union HRCNFG2_REG {
    Uint16  all;
    struct  HRCNFG2_BITS  bit;
};

struct HRPCTL_BITS {                    // bits description
    Uint16 HRPE:1;                      // 0 High Resolution Period Enable
    Uint16 PWMSYNCSEL:1;                // 1 PWMSYNC Source Select 
    Uint16 TBPHSHRLOADE:1;              // 2 TBPHSHR Load Enable 
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 PWMSYNCSELX:3;               // 6:4 PWMSYNCX Source Select Bit: 
    Uint16 rsvd2:9;                     // 15:7 Reserved
};

union HRPCTL_REG {
    Uint16  all;
    struct  HRPCTL_BITS  bit;
};

struct GLDCTL_BITS {                    // bits description
    Uint16 GLD:1;                       // 0 Global Shadow to Active load event control
    Uint16 GLDMODE:4;                   // 4:1 Shadow to Active Global Load Pulse Selection
    Uint16 OSHTMODE:1;                  // 5 One Shot Load mode control bit
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 GLDPRD:3;                    // 9:7 Global Reload Strobe Period Select Register
    Uint16 GLDCNT:3;                    // 12:10 Global Reload Strobe Counter Register
    Uint16 rsvd2:3;                     // 15:13 Reserved
};

union GLDCTL_REG {
    Uint16  all;
    struct  GLDCTL_BITS  bit;
};

struct GLDCFG_BITS {                    // bits description
    Uint16 TBPRD_TBPRDHR:1;             // 0 Global load event configuration for TBPRD:TBPRDHR 
    Uint16 CMPA_CMPAHR:1;               // 1 Global load event configuration for CMPA:CMPAHR 
    Uint16 CMPB_CMPBHR:1;               // 2 Global load event configuration for CMPB:CMPBHR 
    Uint16 CMPC:1;                      // 3 Global load event configuration for CMPC 
    Uint16 CMPD:1;                      // 4 Global load event configuration for CMPD 
    Uint16 DBRED_DBREDHR:1;             // 5 Global load event configuration for DBRED:DBREDHR 
    Uint16 DBFED_DBFEDHR:1;             // 6 Global load event configuration for DBFED:DBFEDHR
    Uint16 DBCTL:1;                     // 7 Global load event configuration for DBCTL
    Uint16 AQCTLA_AQCTLA2:1;            // 8 Global load event configuration for AQCTLA/A2 
    Uint16 AQCTLB_AQCTLB2:1;            // 9 Global load event configuration for AQCTLB/B2 
    Uint16 AQCSFRC:1;                   // 10 Global load event configuration for AQCSFRC 
    Uint16 rsvd1:5;                     // 15:11 Reserved
};

union GLDCFG_REG {
    Uint16  all;
    struct  GLDCFG_BITS  bit;
};

struct EPWMXLINK_BITS {                 // bits description
    Uint16 TBPRDLINK:4;                 // 3:0 TBPRD:TBPRDHR  Link 
    Uint16 CMPALINK:4;                  // 7:4 CMPA:CMPAHR Link 
    Uint16 CMPBLINK:4;                  // 11:8 CMPB:CMPBHR Link
    Uint16 CMPCLINK:4;                  // 15:12 CMPC Link
    Uint16 CMPDLINK:4;                  // 19:16 CMPD Link
    Uint16 rsvd1:8;                     // 27:20 Reserved
    Uint16 GLDCTL2LINK:4;               // 31:28 GLDCTL2 Link
};

union EPWMXLINK_REG {
    Uint32  all;
    struct  EPWMXLINK_BITS  bit;
};

struct AQCTLA_BITS {                    // bits description
    Uint16 ZRO:2;                       // 1:0 Action Counter = Zero
    Uint16 PRD:2;                       // 3:2 Action Counter = Period
    Uint16 CAU:2;                       // 5:4 Action Counter = Compare A Up
    Uint16 CAD:2;                       // 7:6 Action Counter = Compare A Down
    Uint16 CBU:2;                       // 9:8 Action Counter = Compare B Up
    Uint16 CBD:2;                       // 11:10 Action Counter = Compare B Down
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union AQCTLA_REG {
    Uint16  all;
    struct  AQCTLA_BITS  bit;
};

struct AQCTLA2_BITS {                   // bits description
    Uint16 T1U:2;                       // 1:0 Action when event occurs on T1 in UP-Count
    Uint16 T1D:2;                       // 3:2 Action when event occurs on T1 in DOWN-Count
    Uint16 T2U:2;                       // 5:4 Action when event occurs on T2 in UP-Count
    Uint16 T2D:2;                       // 7:6 Action when event occurs on T2 in DOWN-Count
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union AQCTLA2_REG {
    Uint16  all;
    struct  AQCTLA2_BITS  bit;
};

struct AQCTLB_BITS {                    // bits description
    Uint16 ZRO:2;                       // 1:0 Action Counter = Zero
    Uint16 PRD:2;                       // 3:2 Action Counter = Period
    Uint16 CAU:2;                       // 5:4 Action Counter = Compare A Up
    Uint16 CAD:2;                       // 7:6 Action Counter = Compare A Down
    Uint16 CBU:2;                       // 9:8 Action Counter = Compare B Up
    Uint16 CBD:2;                       // 11:10 Action Counter = Compare B Down
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union AQCTLB_REG {
    Uint16  all;
    struct  AQCTLB_BITS  bit;
};

struct AQCTLB2_BITS {                   // bits description
    Uint16 T1U:2;                       // 1:0 Action when event occurs on T1 in UP-Count
    Uint16 T1D:2;                       // 3:2 Action when event occurs on T1 in DOWN-Count
    Uint16 T2U:2;                       // 5:4 Action when event occurs on T2 in UP-Count
    Uint16 T2D:2;                       // 7:6 Action when event occurs on T2 in DOWN-Count
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union AQCTLB2_REG {
    Uint16  all;
    struct  AQCTLB2_BITS  bit;
};

struct AQSFRC_BITS {                    // bits description
    Uint16 ACTSFA:2;                    // 1:0 Action when One-time SW Force A Invoked
    Uint16 OTSFA:1;                     // 2 One-time SW Force A Output
    Uint16 ACTSFB:2;                    // 4:3 Action when One-time SW Force B Invoked
    Uint16 OTSFB:1;                     // 5 One-time SW Force A Output
    Uint16 RLDCSF:2;                    // 7:6 Reload from Shadow Options
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union AQSFRC_REG {
    Uint16  all;
    struct  AQSFRC_BITS  bit;
};

struct AQCSFRC_BITS {                   // bits description
    Uint16 CSFA:2;                      // 1:0 Continuous Software Force on output A
    Uint16 CSFB:2;                      // 3:2 Continuous Software Force on output B
    Uint16 rsvd1:12;                    // 15:4 Reserved
};

union AQCSFRC_REG {
    Uint16  all;
    struct  AQCSFRC_BITS  bit;
};

struct DBREDHR_BITS {                   // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:7;                     // 7:1 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 DBREDHR:7;                   // 15:9 DBREDHR High Resolution Bits
};

union DBREDHR_REG {
    Uint16  all;
    struct  DBREDHR_BITS  bit;
};

struct DBRED_BITS {                     // bits description
    Uint16 DBRED:14;                    // 13:0 Rising edge delay value
    Uint16 rsvd1:2;                     // 15:14 Reserved
};

union DBRED_REG {
    Uint16  all;
    struct  DBRED_BITS  bit;
};

struct DBFEDHR_BITS {                   // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:7;                     // 7:1 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 DBFEDHR:7;                   // 15:9 DBFEDHR High Resolution Bits
};

union DBFEDHR_REG {
    Uint16  all;
    struct  DBFEDHR_BITS  bit;
};

struct DBFED_BITS {                     // bits description
    Uint16 DBFED:14;                    // 13:0 Falling edge delay value
    Uint16 rsvd1:2;                     // 15:14 Reserved
};

union DBFED_REG {
    Uint16  all;
    struct  DBFED_BITS  bit;
};

struct TBPHS_BITS {                     // bits description
    Uint16 TBPHSHR:16;                  // 15:0 Extension Register for HRPWM Phase (8-bits) 
    Uint16 TBPHS:16;                    // 31:16 Phase Offset Register
};

union TBPHS_REG {
    Uint32  all;
    struct  TBPHS_BITS  bit;
};

struct CMPA_BITS {                      // bits description
    Uint16 CMPAHR:16;                   // 15:0 Compare A HRPWM Extension Register
    Uint16 CMPA:16;                     // 31:16 Compare A Register
};

union CMPA_REG {
    Uint32  all;
    struct  CMPA_BITS  bit;
};

struct CMPB_BITS {                      // bits description
    Uint16 CMPBHR:16;                   // 15:0 Compare B High Resolution Bits
    Uint16 CMPB:16;                     // 31:16 Compare B Register
};

union CMPB_REG {
    Uint32  all;
    struct  CMPB_BITS  bit;
};

struct GLDCTL2_BITS {                   // bits description
    Uint16 OSHTLD:1;                    // 0 Enable reload event in one shot mode 
    Uint16 GFRCLD:1;                    // 1 Force reload event in one shot mode 
    Uint16 rsvd1:14;                    // 15:2 Reserved
};

union GLDCTL2_REG {
    Uint16  all;
    struct  GLDCTL2_BITS  bit;
};

struct TZSEL_BITS {                     // bits description
    Uint16 CBC1:1;                      // 0 TZ1 CBC select
    Uint16 CBC2:1;                      // 1 TZ2 CBC select
    Uint16 CBC3:1;                      // 2 TZ3 CBC select
    Uint16 CBC4:1;                      // 3 TZ4 CBC select
    Uint16 CBC5:1;                      // 4 TZ5 CBC select
    Uint16 CBC6:1;                      // 5 TZ6 CBC select
    Uint16 DCAEVT2:1;                   // 6 DCAEVT2 CBC select
    Uint16 DCBEVT2:1;                   // 7 DCBEVT2 CBC select
    Uint16 OSHT1:1;                     // 8 One-shot TZ1 select
    Uint16 OSHT2:1;                     // 9 One-shot TZ2 select
    Uint16 OSHT3:1;                     // 10 One-shot TZ3 select
    Uint16 OSHT4:1;                     // 11 One-shot TZ4 select
    Uint16 OSHT5:1;                     // 12 One-shot TZ5 select
    Uint16 OSHT6:1;                     // 13 One-shot TZ6 select
    Uint16 DCAEVT1:1;                   // 14 One-shot DCAEVT1 select
    Uint16 DCBEVT1:1;                   // 15 One-shot DCBEVT1 select
};

union TZSEL_REG {
    Uint16  all;
    struct  TZSEL_BITS  bit;
};

struct TZDCSEL_BITS {                   // bits description
    Uint16 DCAEVT1:3;                   // 2:0 Digital Compare Output A Event 1
    Uint16 DCAEVT2:3;                   // 5:3 Digital Compare Output A Event 2
    Uint16 DCBEVT1:3;                   // 8:6 Digital Compare Output B Event 1
    Uint16 DCBEVT2:3;                   // 11:9 Digital Compare Output B Event 2
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union TZDCSEL_REG {
    Uint16  all;
    struct  TZDCSEL_BITS  bit;
};

struct TZCTL_BITS {                     // bits description
    Uint16 TZA:2;                       // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
    Uint16 TZB:2;                       // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
    Uint16 DCAEVT1:2;                   // 5:4 EPWMxA action on DCAEVT1
    Uint16 DCAEVT2:2;                   // 7:6 EPWMxA action on DCAEVT2
    Uint16 DCBEVT1:2;                   // 9:8 EPWMxB action on DCBEVT1
    Uint16 DCBEVT2:2;                   // 11:10 EPWMxB action on DCBEVT2
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union TZCTL_REG {
    Uint16  all;
    struct  TZCTL_BITS  bit;
};

struct TZCTL2_BITS {                    // bits description
    Uint16 TZAU:3;                      // 2:0 Trip Action On EPWMxA while Count direction is UP
    Uint16 TZAD:3;                      // 5:3 Trip Action On EPWMxA while Count direction is DOWN
    Uint16 TZBU:3;                      // 8:6 Trip Action On EPWMxB while Count direction is UP
    Uint16 TZBD:3;                      // 11:9 Trip Action On EPWMxB while Count direction is DOWN
    Uint16 rsvd1:3;                     // 14:12 Reserved
    Uint16 ETZE:1;                      // 15 TZCTL2 Enable
};

union TZCTL2_REG {
    Uint16  all;
    struct  TZCTL2_BITS  bit;
};

struct TZCTLDCA_BITS {                  // bits description
    Uint16 DCAEVT1U:3;                  // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP
    Uint16 DCAEVT1D:3;                  // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN
    Uint16 DCAEVT2U:3;                  // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP
    Uint16 DCAEVT2D:3;                  // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union TZCTLDCA_REG {
    Uint16  all;
    struct  TZCTLDCA_BITS  bit;
};

struct TZCTLDCB_BITS {                  // bits description
    Uint16 DCBEVT1U:3;                  // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP
    Uint16 DCBEVT1D:3;                  // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN
    Uint16 DCBEVT2U:3;                  // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP
    Uint16 DCBEVT2D:3;                  // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union TZCTLDCB_REG {
    Uint16  all;
    struct  TZCTLDCB_BITS  bit;
};

struct TZEINT_BITS {                    // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CBC:1;                       // 1 Trip Zones Cycle By Cycle Int Enable
    Uint16 OST:1;                       // 2 Trip Zones One Shot Int Enable
    Uint16 DCAEVT1:1;                   // 3 Digital Compare A Event 1 Int Enable
    Uint16 DCAEVT2:1;                   // 4 Digital Compare A Event 2 Int Enable
    Uint16 DCBEVT1:1;                   // 5 Digital Compare B Event 1 Int Enable
    Uint16 DCBEVT2:1;                   // 6 Digital Compare B Event 2 Int Enable
    Uint16 rsvd2:9;                     // 15:7 Reserved
};

union TZEINT_REG {
    Uint16  all;
    struct  TZEINT_BITS  bit;
};

struct TZFLG_BITS {                     // bits description
    Uint16 INT:1;                       // 0 Global Int Status Flag
    Uint16 CBC:1;                       // 1 Trip Zones Cycle By Cycle Flag
    Uint16 OST:1;                       // 2 Trip Zones One Shot Flag
    Uint16 DCAEVT1:1;                   // 3 Digital Compare A Event 1 Flag
    Uint16 DCAEVT2:1;                   // 4 Digital Compare A Event 2 Flag
    Uint16 DCBEVT1:1;                   // 5 Digital Compare B Event 1 Flag
    Uint16 DCBEVT2:1;                   // 6 Digital Compare B Event 2 Flag
    Uint16 rsvd1:9;                     // 15:7 Reserved
};

union TZFLG_REG {
    Uint16  all;
    struct  TZFLG_BITS  bit;
};

struct TZCBCFLG_BITS {                  // bits description
    Uint16 CBC1:1;                      // 0 Latched Status Flag for CBC1 Trip Latch
    Uint16 CBC2:1;                      // 1 Latched Status Flag for CBC2 Trip Latch
    Uint16 CBC3:1;                      // 2 Latched Status Flag for CBC3 Trip Latch
    Uint16 CBC4:1;                      // 3 Latched Status Flag for CBC4 Trip Latch
    Uint16 CBC5:1;                      // 4 Latched Status Flag for CBC5 Trip Latch
    Uint16 CBC6:1;                      // 5 Latched Status Flag for CBC6 Trip Latch
    Uint16 DCAEVT2:1;                   // 6 Latched Status Flag for Digital Compare Output A Event 2
    Uint16 DCBEVT2:1;                   // 7 Latched Status Flag for Digital Compare Output B Event 2
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union TZCBCFLG_REG {
    Uint16  all;
    struct  TZCBCFLG_BITS  bit;
};

struct TZOSTFLG_BITS {                  // bits description
    Uint16 OST1:1;                      // 0 Latched Status Flag for OST1 Trip Latch
    Uint16 OST2:1;                      // 1 Latched Status Flag for OST2 Trip Latch
    Uint16 OST3:1;                      // 2 Latched Status Flag for OST3 Trip Latch
    Uint16 OST4:1;                      // 3 Latched Status Flag for OST4 Trip Latch
    Uint16 OST5:1;                      // 4 Latched Status Flag for OST5 Trip Latch
    Uint16 OST6:1;                      // 5 Latched Status Flag for OST6 Trip Latch
    Uint16 DCAEVT1:1;                   // 6 Latched Status Flag for Digital Compare Output A Event 1
    Uint16 DCBEVT1:1;                   // 7 Latched Status Flag for Digital Compare Output B Event 1
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union TZOSTFLG_REG {
    Uint16  all;
    struct  TZOSTFLG_BITS  bit;
};

struct TZCLR_BITS {                     // bits description
    Uint16 INT:1;                       // 0 Global Interrupt Clear Flag
    Uint16 CBC:1;                       // 1 Cycle-By-Cycle Flag Clear
    Uint16 OST:1;                       // 2 One-Shot Flag Clear
    Uint16 DCAEVT1:1;                   // 3 DCAVET1 Flag Clear
    Uint16 DCAEVT2:1;                   // 4 DCAEVT2 Flag Clear
    Uint16 DCBEVT1:1;                   // 5 DCBEVT1 Flag Clear
    Uint16 DCBEVT2:1;                   // 6 DCBEVT2 Flag Clear
    Uint16 rsvd1:7;                     // 13:7 Reserved
    Uint16 CBCPULSE:2;                  // 15:14 Clear Pulse for CBC Trip Latch
};

union TZCLR_REG {
    Uint16  all;
    struct  TZCLR_BITS  bit;
};

struct TZCBCCLR_BITS {                  // bits description
    Uint16 CBC1:1;                      // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch
    Uint16 CBC2:1;                      // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch
    Uint16 CBC3:1;                      // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch
    Uint16 CBC4:1;                      // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch
    Uint16 CBC5:1;                      // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch
    Uint16 CBC6:1;                      // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch
    Uint16 DCAEVT2:1;                   // 6 Clear Flag forDCAEVT2 selected for CBC
    Uint16 DCBEVT2:1;                   // 7 Clear Flag for DCBEVT2 selected for CBC
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union TZCBCCLR_REG {
    Uint16  all;
    struct  TZCBCCLR_BITS  bit;
};

struct TZOSTCLR_BITS {                  // bits description
    Uint16 OST1:1;                      // 0 Clear Flag for Oneshot (OST1) Trip Latch
    Uint16 OST2:1;                      // 1 Clear Flag for Oneshot (OST2) Trip Latch
    Uint16 OST3:1;                      // 2 Clear Flag for Oneshot (OST3) Trip Latch
    Uint16 OST4:1;                      // 3 Clear Flag for Oneshot (OST4) Trip Latch
    Uint16 OST5:1;                      // 4 Clear Flag for Oneshot (OST5) Trip Latch
    Uint16 OST6:1;                      // 5 Clear Flag for Oneshot (OST6) Trip Latch
    Uint16 DCAEVT1:1;                   // 6 Clear Flag for DCAEVT1 selected for OST
    Uint16 DCBEVT1:1;                   // 7 Clear Flag for DCBEVT1 selected for OST
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union TZOSTCLR_REG {
    Uint16  all;
    struct  TZOSTCLR_BITS  bit;
};

struct TZFRC_BITS {                     // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CBC:1;                       // 1 Force Trip Zones Cycle By Cycle Event
    Uint16 OST:1;                       // 2 Force Trip Zones One Shot Event
    Uint16 DCAEVT1:1;                   // 3 Force Digital Compare A Event 1 
    Uint16 DCAEVT2:1;                   // 4 Force Digital Compare A Event 2 
    Uint16 DCBEVT1:1;                   // 5 Force Digital Compare B Event 1 
    Uint16 DCBEVT2:1;                   // 6 Force Digital Compare B Event 2 
    Uint16 rsvd2:9;                     // 15:7 Reserved
};

union TZFRC_REG {
    Uint16  all;
    struct  TZFRC_BITS  bit;
};

struct ETSEL_BITS {                     // bits description
    Uint16 INTSEL:3;                    // 2:0 EPWMxINTn Select
    Uint16 INTEN:1;                     // 3 EPWMxINTn Enable
    Uint16 SOCASELCMP:1;                // 4 EPWMxSOCA Compare Select
    Uint16 SOCBSELCMP:1;                // 5 EPWMxSOCB Compare Select
    Uint16 INTSELCMP:1;                 // 6 EPWMxINT Compare Select
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 SOCASEL:3;                   // 10:8 Start of Conversion A Select
    Uint16 SOCAEN:1;                    // 11 Start of Conversion A Enable
    Uint16 SOCBSEL:3;                   // 14:12 Start of Conversion B Select
    Uint16 SOCBEN:1;                    // 15 Start of Conversion B Enable
};

union ETSEL_REG {
    Uint16  all;
    struct  ETSEL_BITS  bit;
};

struct ETPS_BITS {                      // bits description
    Uint16 INTPRD:2;                    // 1:0 EPWMxINTn Period Select
    Uint16 INTCNT:2;                    // 3:2 EPWMxINTn Counter Register
    Uint16 INTPSSEL:1;                  // 4 EPWMxINTn Pre-Scale Selection Bits
    Uint16 SOCPSSEL:1;                  // 5 EPWMxSOC A/B  Pre-Scale Selection Bits
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 SOCAPRD:2;                   // 9:8 EPWMxSOCA Period Select
    Uint16 SOCACNT:2;                   // 11:10 EPWMxSOCA Counter Register
    Uint16 SOCBPRD:2;                   // 13:12 EPWMxSOCB Period Select
    Uint16 SOCBCNT:2;                   // 15:14 EPWMxSOCB Counter
};

union ETPS_REG {
    Uint16  all;
    struct  ETPS_BITS  bit;
};

struct ETFLG_BITS {                     // bits description
    Uint16 INT:1;                       // 0 EPWMxINTn Flag
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 SOCA:1;                      // 2 EPWMxSOCA Flag
    Uint16 SOCB:1;                      // 3 EPWMxSOCB Flag
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union ETFLG_REG {
    Uint16  all;
    struct  ETFLG_BITS  bit;
};

struct ETCLR_BITS {                     // bits description
    Uint16 INT:1;                       // 0 EPWMxINTn Clear
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 SOCA:1;                      // 2 EPWMxSOCA Clear
    Uint16 SOCB:1;                      // 3 EPWMxSOCB Clear
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union ETCLR_REG {
    Uint16  all;
    struct  ETCLR_BITS  bit;
};

struct ETFRC_BITS {                     // bits description
    Uint16 INT:1;                       // 0 EPWMxINTn Force
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 SOCA:1;                      // 2 EPWMxSOCA Force
    Uint16 SOCB:1;                      // 3 EPWMxSOCB Force
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union ETFRC_REG {
    Uint16  all;
    struct  ETFRC_BITS  bit;
};

struct ETINTPS_BITS {                   // bits description
    Uint16 INTPRD2:4;                   // 3:0 EPWMxINTn Period Select
    Uint16 INTCNT2:4;                   // 7:4 EPWMxINTn Counter Register
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union ETINTPS_REG {
    Uint16  all;
    struct  ETINTPS_BITS  bit;
};

struct ETSOCPS_BITS {                   // bits description
    Uint16 SOCAPRD2:4;                  // 3:0 EPWMxSOCA Period Select
    Uint16 SOCACNT2:4;                  // 7:4 EPWMxSOCA Counter Register
    Uint16 SOCBPRD2:4;                  // 11:8 EPWMxSOCB Period Select
    Uint16 SOCBCNT2:4;                  // 15:12 EPWMxSOCB Counter Register
};

union ETSOCPS_REG {
    Uint16  all;
    struct  ETSOCPS_BITS  bit;
};

struct ETCNTINITCTL_BITS {              // bits description
    Uint16 rsvd1:10;                    // 9:0 Reserved
    Uint16 INTINITFRC:1;                // 10 EPWMxINT Counter Initialization Force
    Uint16 SOCAINITFRC:1;               // 11 EPWMxSOCA Counter Initialization Force
    Uint16 SOCBINITFRC:1;               // 12 EPWMxSOCB Counter Initialization Force
    Uint16 INTINITEN:1;                 // 13 EPWMxINT Counter Initialization Enable
    Uint16 SOCAINITEN:1;                // 14 EPWMxSOCA Counter Initialization Enable
    Uint16 SOCBINITEN:1;                // 15 EPWMxSOCB Counter Initialization Enable
};

union ETCNTINITCTL_REG {
    Uint16  all;
    struct  ETCNTINITCTL_BITS  bit;
};

struct ETCNTINIT_BITS {                 // bits description
    Uint16 INTINIT:4;                   // 3:0 EPWMxINT Counter Initialization Bits
    Uint16 SOCAINIT:4;                  // 7:4 EPWMxSOCA Counter Initialization Bits
    Uint16 SOCBINIT:4;                  // 11:8 EPWMxSOCB Counter Initialization Bits
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union ETCNTINIT_REG {
    Uint16  all;
    struct  ETCNTINIT_BITS  bit;
};

struct DCTRIPSEL_BITS {                 // bits description
    Uint16 DCAHCOMPSEL:4;               // 3:0 Digital Compare A High COMP Input Select 
    Uint16 DCALCOMPSEL:4;               // 7:4 Digital Compare A Low COMP Input Select 
    Uint16 DCBHCOMPSEL:4;               // 11:8 Digital Compare B High COMP Input Select
    Uint16 DCBLCOMPSEL:4;               // 15:12 Digital Compare B Low COMP Input Select
};

union DCTRIPSEL_REG {
    Uint16  all;
    struct  DCTRIPSEL_BITS  bit;
};

struct DCACTL_BITS {                    // bits description
    Uint16 EVT1SRCSEL:1;                // 0 DCAEVT1 Source Signal
    Uint16 EVT1FRCSYNCSEL:1;            // 1 DCAEVT1 Force Sync Signal
    Uint16 EVT1SOCE:1;                  // 2 DCAEVT1 SOC Enable
    Uint16 EVT1SYNCE:1;                 // 3 DCAEVT1 SYNC Enable
    Uint16 rsvd1:4;                     // 7:4 Reserved
    Uint16 EVT2SRCSEL:1;                // 8 DCAEVT2 Source Signal
    Uint16 EVT2FRCSYNCSEL:1;            // 9 DCAEVT2 Force Sync Signal
    Uint16 rsvd2:6;                     // 15:10 Reserved
};

union DCACTL_REG {
    Uint16  all;
    struct  DCACTL_BITS  bit;
};

struct DCBCTL_BITS {                    // bits description
    Uint16 EVT1SRCSEL:1;                // 0 DCBEVT1 Source Signal
    Uint16 EVT1FRCSYNCSEL:1;            // 1 DCBEVT1 Force Sync Signal
    Uint16 EVT1SOCE:1;                  // 2 DCBEVT1 SOC Enable
    Uint16 EVT1SYNCE:1;                 // 3 DCBEVT1 SYNC Enable
    Uint16 rsvd1:4;                     // 7:4 Reserved
    Uint16 EVT2SRCSEL:1;                // 8 DCBEVT2 Source Signal
    Uint16 EVT2FRCSYNCSEL:1;            // 9 DCBEVT2 Force Sync Signal
    Uint16 rsvd2:6;                     // 15:10 Reserved
};

union DCBCTL_REG {
    Uint16  all;
    struct  DCBCTL_BITS  bit;
};

struct DCFCTL_BITS {                    // bits description
    Uint16 SRCSEL:2;                    // 1:0 Filter Block Signal Source Select
    Uint16 BLANKE:1;                    // 2 Blanking Enable/Disable
    Uint16 BLANKINV:1;                  // 3 Blanking Window Inversion
    Uint16 PULSESEL:2;                  // 5:4 Pulse Select for Blanking & Capture Alignment
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:2;                     // 9:8 Reserved
    Uint16 rsvd4:3;                     // 12:10 Reserved
    Uint16 rsvd5:3;                     // 15:13 Reserved
};

union DCFCTL_REG {
    Uint16  all;
    struct  DCFCTL_BITS  bit;
};

struct DCCAPCTL_BITS {                  // bits description
    Uint16 CAPE:1;                      // 0 Counter Capture Enable
    Uint16 SHDWMODE:1;                  // 1 Counter Capture Mode
    Uint16 rsvd1:11;                    // 12:2 Reserved
    Uint16 rsvd2:1;                     // 13 Reserved
    Uint16 rsvd3:1;                     // 14 Reserved
    Uint16 rsvd4:1;                     // 15 Reserved
};

union DCCAPCTL_REG {
    Uint16  all;
    struct  DCCAPCTL_BITS  bit;
};

struct DCAHTRIPSEL_BITS {               // bits description
    Uint16 TRIPINPUT1:1;                // 0 Trip Input 1 Select to DCAH Mux
    Uint16 TRIPINPUT2:1;                // 1 Trip Input 2 Select to DCAH Mux
    Uint16 TRIPINPUT3:1;                // 2 Trip Input 3 Select to DCAH Mux
    Uint16 TRIPINPUT4:1;                // 3 Trip Input 4 Select to DCAH Mux
    Uint16 TRIPINPUT5:1;                // 4 Trip Input 5 Select to DCAH Mux
    Uint16 TRIPINPUT6:1;                // 5 Trip Input 6 Select to DCAH Mux
    Uint16 TRIPINPUT7:1;                // 6 Trip Input 7 Select to DCAH Mux
    Uint16 TRIPINPUT8:1;                // 7 Trip Input 8 Select to DCAH Mux
    Uint16 TRIPINPUT9:1;                // 8 Trip Input 9 Select to DCAH Mux
    Uint16 TRIPINPUT10:1;               // 9 Trip Input 10 Select to DCAH Mux
    Uint16 TRIPINPUT11:1;               // 10 Trip Input 11 Select to DCAH Mux
    Uint16 TRIPINPUT12:1;               // 11 Trip Input 12 Select to DCAH Mux
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 TRIPINPUT14:1;               // 13 Trip Input 14 Select to DCAH Mux
    Uint16 TRIPINPUT15:1;               // 14 Trip Input 15 Select to DCAH Mux
    Uint16 rsvd2:1;                     // 15 Reserved
};

union DCAHTRIPSEL_REG {
    Uint16  all;
    struct  DCAHTRIPSEL_BITS  bit;
};

struct DCALTRIPSEL_BITS {               // bits description
    Uint16 TRIPINPUT1:1;                // 0 Trip Input 1 Select to DCAL Mux
    Uint16 TRIPINPUT2:1;                // 1 Trip Input 2 Select to DCAL Mux
    Uint16 TRIPINPUT3:1;                // 2 Trip Input 3 Select to DCAL Mux
    Uint16 TRIPINPUT4:1;                // 3 Trip Input 4 Select to DCAL Mux
    Uint16 TRIPINPUT5:1;                // 4 Trip Input 5 Select to DCAL Mux
    Uint16 TRIPINPUT6:1;                // 5 Trip Input 6 Select to DCAL Mux
    Uint16 TRIPINPUT7:1;                // 6 Trip Input 7 Select to DCAL Mux
    Uint16 TRIPINPUT8:1;                // 7 Trip Input 8 Select to DCAL Mux
    Uint16 TRIPINPUT9:1;                // 8 Trip Input 9 Select to DCAL Mux
    Uint16 TRIPINPUT10:1;               // 9 Trip Input 10 Select to DCAL Mux
    Uint16 TRIPINPUT11:1;               // 10 Trip Input 11 Select to DCAL Mux
    Uint16 TRIPINPUT12:1;               // 11 Trip Input 12 Select to DCAL Mux
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 TRIPINPUT14:1;               // 13 Trip Input 14 Select to DCAL Mux
    Uint16 TRIPINPUT15:1;               // 14 Trip Input 15 Select to DCAL Mux
    Uint16 rsvd2:1;                     // 15 Reserved
};

union DCALTRIPSEL_REG {
    Uint16  all;
    struct  DCALTRIPSEL_BITS  bit;
};

struct DCBHTRIPSEL_BITS {               // bits description
    Uint16 TRIPINPUT1:1;                // 0 Trip Input 1 Select to DCBH Mux
    Uint16 TRIPINPUT2:1;                // 1 Trip Input 2 Select to DCBH Mux
    Uint16 TRIPINPUT3:1;                // 2 Trip Input 3 Select to DCBH Mux
    Uint16 TRIPINPUT4:1;                // 3 Trip Input 4 Select to DCBH Mux
    Uint16 TRIPINPUT5:1;                // 4 Trip Input 5 Select to DCBH Mux
    Uint16 TRIPINPUT6:1;                // 5 Trip Input 6 Select to DCBH Mux
    Uint16 TRIPINPUT7:1;                // 6 Trip Input 7 Select to DCBH Mux
    Uint16 TRIPINPUT8:1;                // 7 Trip Input 8 Select to DCBH Mux
    Uint16 TRIPINPUT9:1;                // 8 Trip Input 9 Select to DCBH Mux
    Uint16 TRIPINPUT10:1;               // 9 Trip Input 10 Select to DCBH Mux
    Uint16 TRIPINPUT11:1;               // 10 Trip Input 11 Select to DCBH Mux
    Uint16 TRIPINPUT12:1;               // 11 Trip Input 12 Select to DCBH Mux
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 TRIPINPUT14:1;               // 13 Trip Input 14 Select to DCBH Mux
    Uint16 TRIPINPUT15:1;               // 14 Trip Input 15 Select to DCBH Mux
    Uint16 rsvd2:1;                     // 15 Reserved
};

union DCBHTRIPSEL_REG {
    Uint16  all;
    struct  DCBHTRIPSEL_BITS  bit;
};

struct DCBLTRIPSEL_BITS {               // bits description
    Uint16 TRIPINPUT1:1;                // 0 Trip Input 1 Select to DCBL Mux
    Uint16 TRIPINPUT2:1;                // 1 Trip Input 2 Select to DCBL Mux
    Uint16 TRIPINPUT3:1;                // 2 Trip Input 3 Select to DCBL Mux
    Uint16 TRIPINPUT4:1;                // 3 Trip Input 4 Select to DCBL Mux
    Uint16 TRIPINPUT5:1;                // 4 Trip Input 5 Select to DCBL Mux
    Uint16 TRIPINPUT6:1;                // 5 Trip Input 6 Select to DCBL Mux
    Uint16 TRIPINPUT7:1;                // 6 Trip Input 7 Select to DCBL Mux
    Uint16 TRIPINPUT8:1;                // 7 Trip Input 8 Select to DCBL Mux
    Uint16 TRIPINPUT9:1;                // 8 Trip Input 9 Select to DCBL Mux
    Uint16 TRIPINPUT10:1;               // 9 Trip Input 10 Select to DCBL Mux
    Uint16 TRIPINPUT11:1;               // 10 Trip Input 11 Select to DCBL Mux
    Uint16 TRIPINPUT12:1;               // 11 Trip Input 12 Select to DCBL Mux
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 TRIPINPUT14:1;               // 13 Trip Input 14 Select to DCBL Mux
    Uint16 TRIPINPUT15:1;               // 14 Trip Input 15 Select to DCBL Mux
    Uint16 rsvd2:1;                     // 15 Reserved
};

union DCBLTRIPSEL_REG {
    Uint16  all;
    struct  DCBLTRIPSEL_BITS  bit;
};

struct EPWM_REGS {
    union   TBCTL_REG                        TBCTL;                        // Time Base Control Register
    union   TBCTL2_REG                       TBCTL2;                       // Time Base Control Register 2
    Uint16                                   rsvd1[2];                     // Reserved
    Uint16                                   TBCTR;                        // Time Base Counter Register
    union   TBSTS_REG                        TBSTS;                        // Time Base Status Register
    Uint16                                   rsvd2[2];                     // Reserved
    union   CMPCTL_REG                       CMPCTL;                       // Counter Compare Control Register
    union   CMPCTL2_REG                      CMPCTL2;                      // Counter Compare Control Register 2
    Uint16                                   rsvd3[2];                     // Reserved
    union   DBCTL_REG                        DBCTL;                        // Dead-Band Generator Control Register
    union   DBCTL2_REG                       DBCTL2;                       // Dead-Band Generator Control Register 2
    Uint16                                   rsvd4[2];                     // Reserved
    union   AQCTL_REG                        AQCTL;                        // Action Qualifier Control Register
    union   AQTSRCSEL_REG                    AQTSRCSEL;                    // Action Qualifier Trigger Event Source Select Register
    Uint16                                   rsvd5[2];                     // Reserved
    union   PCCTL_REG                        PCCTL;                        // PWM Chopper Control Register
    Uint16                                   rsvd6[11];                    // Reserved
    union   HRCNFG_REG                       HRCNFG;                       // HRPWM Configuration Register
    union   HRPWR_REG                        HRPWR;                        // HRPWM Power Register
    Uint16                                   rsvd7[4];                     // Reserved
    union   HRMSTEP_REG                      HRMSTEP;                      // HRPWM MEP Step Register
    union   HRCNFG2_REG                      HRCNFG2;                      // HRPWM Configuration 2 Register
    Uint16                                   rsvd8[5];                     // Reserved
    union   HRPCTL_REG                       HRPCTL;                       // High Resolution Period Control Register 
    Uint16                                   rsvd9[6];                     // Reserved
    union   GLDCTL_REG                       GLDCTL;                       // Global PWM Load Control Register
    union   GLDCFG_REG                       GLDCFG;                       // Global PWM Load Config Register 
    Uint16                                   rsvd10[2];                    // Reserved
    union   EPWMXLINK_REG                    EPWMXLINK;                    // EPWMx Link Register
    Uint16                                   rsvd11[6];                    // Reserved
    union   AQCTLA_REG                       AQCTLA;                       // Action Qualifier Control Register For Output A 
    union   AQCTLA2_REG                      AQCTLA2;                      // Additional Action Qualifier Control Register For Output A 
    union   AQCTLB_REG                       AQCTLB;                       // Action Qualifier Control Register For Output B 
    union   AQCTLB2_REG                      AQCTLB2;                      // Additional Action Qualifier Control Register For Output B 
    Uint16                                   rsvd12[3];                    // Reserved
    union   AQSFRC_REG                       AQSFRC;                       // Action Qualifier Software Force Register
    Uint16                                   rsvd13;                       // Reserved
    union   AQCSFRC_REG                      AQCSFRC;                      // Action Qualifier Continuous S/W Force Register 
    Uint16                                   rsvd14[6];                    // Reserved
    union   DBREDHR_REG                      DBREDHR;                      // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register 
    union   DBRED_REG                        DBRED;                        // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register 
    union   DBFEDHR_REG                      DBFEDHR;                      // Dead-Band Generator Falling Edge Delay High Resolution Register 
    union   DBFED_REG                        DBFED;                        // Dead-Band Generator Falling Edge Delay Count Register
    Uint16                                   rsvd15[12];                   // Reserved
    union   TBPHS_REG                        TBPHS;                        // Time Base Phase High
    Uint16                                   TBPRDHR;                      // Time Base Period High Resolution Register 
    Uint16                                   TBPRD;                        // Time Base Period Register 
    Uint16                                   rsvd16[6];                    // Reserved
    union   CMPA_REG                         CMPA;                         // Counter Compare A Register 
    union   CMPB_REG                         CMPB;                         // Compare B Register 
    Uint16                                   rsvd17;                       // Reserved
    Uint16                                   CMPC;                         // Counter Compare C Register
    Uint16                                   rsvd18;                       // Reserved
    Uint16                                   CMPD;                         // Counter Compare D Register
    Uint16                                   rsvd19[2];                    // Reserved
    union   GLDCTL2_REG                      GLDCTL2;                      // Global PWM Load Control Register 2
    Uint16                                   rsvd20[11];                   // Reserved
    union   TZSEL_REG                        TZSEL;                        // Trip Zone Select Register 
    Uint16                                   rsvd21;                       // Reserved
    union   TZDCSEL_REG                      TZDCSEL;                      // Trip Zone Digital Comparator Select Register
    Uint16                                   rsvd22;                       // Reserved
    union   TZCTL_REG                        TZCTL;                        // Trip Zone Control Register
    union   TZCTL2_REG                       TZCTL2;                       // Additional Trip Zone Control Register
    union   TZCTLDCA_REG                     TZCTLDCA;                     // Trip Zone Control Register Digital Compare A 
    union   TZCTLDCB_REG                     TZCTLDCB;                     // Trip Zone Control Register Digital Compare B 
    Uint16                                   rsvd23[5];                    // Reserved
    union   TZEINT_REG                       TZEINT;                       // Trip Zone Enable Interrupt Register
    Uint16                                   rsvd24[5];                    // Reserved
    union   TZFLG_REG                        TZFLG;                        // Trip Zone Flag Register
    union   TZCBCFLG_REG                     TZCBCFLG;                     // Trip Zone CBC Flag Register
    union   TZOSTFLG_REG                     TZOSTFLG;                     // Trip Zone OST Flag Register
    Uint16                                   rsvd25;                       // Reserved
    union   TZCLR_REG                        TZCLR;                        // Trip Zone Clear Register
    union   TZCBCCLR_REG                     TZCBCCLR;                     // Trip Zone CBC Clear Register
    union   TZOSTCLR_REG                     TZOSTCLR;                     // Trip Zone OST Clear Register
    Uint16                                   rsvd26;                       // Reserved
    union   TZFRC_REG                        TZFRC;                        // Trip Zone Force Register
    Uint16                                   rsvd27[8];                    // Reserved
    union   ETSEL_REG                        ETSEL;                        // Event Trigger Selection Register
    Uint16                                   rsvd28;                       // Reserved
    union   ETPS_REG                         ETPS;                         // Event Trigger Pre-Scale Register
    Uint16                                   rsvd29;                       // Reserved
    union   ETFLG_REG                        ETFLG;                        // Event Trigger Flag Register
    Uint16                                   rsvd30;                       // Reserved
    union   ETCLR_REG                        ETCLR;                        // Event Trigger Clear Register
    Uint16                                   rsvd31;                       // Reserved
    union   ETFRC_REG                        ETFRC;                        // Event Trigger Force Register
    Uint16                                   rsvd32;                       // Reserved
    union   ETINTPS_REG                      ETINTPS;                      // Event-Trigger Interrupt Pre-Scale Register
    Uint16                                   rsvd33;                       // Reserved
    union   ETSOCPS_REG                      ETSOCPS;                      // Event-Trigger SOC Pre-Scale Register
    Uint16                                   rsvd34;                       // Reserved
    union   ETCNTINITCTL_REG                 ETCNTINITCTL;                 // Event-Trigger Counter Initialization Control Register
    Uint16                                   rsvd35;                       // Reserved
    union   ETCNTINIT_REG                    ETCNTINIT;                    // Event-Trigger Counter Initialization Register
    Uint16                                   rsvd36[11];                   // Reserved
    union   DCTRIPSEL_REG                    DCTRIPSEL;                    // Digital Compare Trip Select Register
    Uint16                                   rsvd37[2];                    // Reserved
    union   DCACTL_REG                       DCACTL;                       // Digital Compare A Control Register
    union   DCBCTL_REG                       DCBCTL;                       // Digital Compare B Control Register
    Uint16                                   rsvd38[2];                    // Reserved
    union   DCFCTL_REG                       DCFCTL;                       // Digital Compare Filter Control Register
    union   DCCAPCTL_REG                     DCCAPCTL;                     // Digital Compare Capture Control Register
    Uint16                                   DCFOFFSET;                    // Digital Compare Filter Offset Register 
    Uint16                                   DCFOFFSETCNT;                 // Digital Compare Filter Offset Counter Register
    Uint16                                   DCFWINDOW;                    // Digital Compare Filter Window Register
    Uint16                                   DCFWINDOWCNT;                 // Digital Compare Filter Window Counter Register
    Uint16                                   rsvd39[2];                    // Reserved
    Uint16                                   DCCAP;                        // Digital Compare Counter Capture Register 
    Uint16                                   rsvd40[2];                    // Reserved
    union   DCAHTRIPSEL_REG                  DCAHTRIPSEL;                  // Digital Compare AH Trip Select 
    union   DCALTRIPSEL_REG                  DCALTRIPSEL;                  // Digital Compare AL Trip Select 
    union   DCBHTRIPSEL_REG                  DCBHTRIPSEL;                  // Digital Compare BH Trip Select 
    union   DCBLTRIPSEL_REG                  DCBLTRIPSEL;                  // Digital Compare BL Trip Select 
    Uint16                                   rsvd41[42];                   // Reserved
};

//---------------------------------------------------------------------------
// EPWM External References & Function Declarations:
//
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
extern volatile struct EPWM_REGS EPwm5Regs;
extern volatile struct EPWM_REGS EPwm6Regs;
extern volatile struct EPWM_REGS EPwm7Regs;
extern volatile struct EPWM_REGS EPwm8Regs;
extern volatile struct EPWM_REGS EPwm9Regs;
extern volatile struct EPWM_REGS EPwm10Regs;
extern volatile struct EPWM_REGS EPwm11Regs;
extern volatile struct EPWM_REGS EPwm12Regs;
}



//###########################################################################
//
// FILE:    F2807x_epwm_xbar.h
//
// TITLE:   F2807x Device EPWM_XBAR Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// EPWM_XBAR Individual Register Bit Definitions:

struct TRIP4MUX0TO15CFG_BITS {          // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR
};

union TRIP4MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP4MUX0TO15CFG_BITS  bit;
};

struct TRIP4MUX16TO31CFG_BITS {         // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR
};

union TRIP4MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP4MUX16TO31CFG_BITS  bit;
};

struct TRIP5MUX0TO15CFG_BITS {          // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR
};

union TRIP5MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP5MUX0TO15CFG_BITS  bit;
};

struct TRIP5MUX16TO31CFG_BITS {         // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR
};

union TRIP5MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP5MUX16TO31CFG_BITS  bit;
};

struct TRIP7MUX0TO15CFG_BITS {          // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR
};

union TRIP7MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP7MUX0TO15CFG_BITS  bit;
};

struct TRIP7MUX16TO31CFG_BITS {         // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR
};

union TRIP7MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP7MUX16TO31CFG_BITS  bit;
};

struct TRIP8MUX0TO15CFG_BITS {          // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR
};

union TRIP8MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP8MUX0TO15CFG_BITS  bit;
};

struct TRIP8MUX16TO31CFG_BITS {         // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR
};

union TRIP8MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP8MUX16TO31CFG_BITS  bit;
};

struct TRIP9MUX0TO15CFG_BITS {          // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR
};

union TRIP9MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP9MUX0TO15CFG_BITS  bit;
};

struct TRIP9MUX16TO31CFG_BITS {         // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR
};

union TRIP9MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP9MUX16TO31CFG_BITS  bit;
};

struct TRIP10MUX0TO15CFG_BITS {         // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR
};

union TRIP10MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP10MUX0TO15CFG_BITS  bit;
};

struct TRIP10MUX16TO31CFG_BITS {        // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR
};

union TRIP10MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP10MUX16TO31CFG_BITS  bit;
};

struct TRIP11MUX0TO15CFG_BITS {         // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR
};

union TRIP11MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP11MUX0TO15CFG_BITS  bit;
};

struct TRIP11MUX16TO31CFG_BITS {        // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR
};

union TRIP11MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP11MUX16TO31CFG_BITS  bit;
};

struct TRIP12MUX0TO15CFG_BITS {         // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR
};

union TRIP12MUX0TO15CFG_REG {
    Uint32  all;
    struct  TRIP12MUX0TO15CFG_BITS  bit;
};

struct TRIP12MUX16TO31CFG_BITS {        // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR
};

union TRIP12MUX16TO31CFG_REG {
    Uint32  all;
    struct  TRIP12MUX16TO31CFG_BITS  bit;
};

struct TRIP4MUXENABLE_BITS {            // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP4 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP4 of EPWM-XBAR
};

union TRIP4MUXENABLE_REG {
    Uint32  all;
    struct  TRIP4MUXENABLE_BITS  bit;
};

struct TRIP5MUXENABLE_BITS {            // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP5 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP5 of EPWM-XBAR
};

union TRIP5MUXENABLE_REG {
    Uint32  all;
    struct  TRIP5MUXENABLE_BITS  bit;
};

struct TRIP7MUXENABLE_BITS {            // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP7 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP7 of EPWM-XBAR
};

union TRIP7MUXENABLE_REG {
    Uint32  all;
    struct  TRIP7MUXENABLE_BITS  bit;
};

struct TRIP8MUXENABLE_BITS {            // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP8 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP8 of EPWM-XBAR
};

union TRIP8MUXENABLE_REG {
    Uint32  all;
    struct  TRIP8MUXENABLE_BITS  bit;
};

struct TRIP9MUXENABLE_BITS {            // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP9 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP9 of EPWM-XBAR
};

union TRIP9MUXENABLE_REG {
    Uint32  all;
    struct  TRIP9MUXENABLE_BITS  bit;
};

struct TRIP10MUXENABLE_BITS {           // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP10 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP10 of EPWM-XBAR
};

union TRIP10MUXENABLE_REG {
    Uint32  all;
    struct  TRIP10MUXENABLE_BITS  bit;
};

struct TRIP11MUXENABLE_BITS {           // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP11 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP11 of EPWM-XBAR
};

union TRIP11MUXENABLE_REG {
    Uint32  all;
    struct  TRIP11MUXENABLE_BITS  bit;
};

struct TRIP12MUXENABLE_BITS {           // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive TRIP12 of EPWM-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive TRIP12 of EPWM-XBAR
};

union TRIP12MUXENABLE_REG {
    Uint32  all;
    struct  TRIP12MUXENABLE_BITS  bit;
};

struct TRIPOUTINV_BITS {                // bits description
    Uint16 TRIP4:1;                     // 0 Selects polarity for TRIP4 of EPWM-XBAR
    Uint16 TRIP5:1;                     // 1 Selects polarity for TRIP5 of EPWM-XBAR
    Uint16 TRIP7:1;                     // 2 Selects polarity for TRIP7 of EPWM-XBAR
    Uint16 TRIP8:1;                     // 3 Selects polarity for TRIP8 of EPWM-XBAR
    Uint16 TRIP9:1;                     // 4 Selects polarity for TRIP9 of EPWM-XBAR
    Uint16 TRIP10:1;                    // 5 Selects polarity for TRIP10 of EPWM-XBAR
    Uint16 TRIP11:1;                    // 6 Selects polarity for TRIP11 of EPWM-XBAR
    Uint16 TRIP12:1;                    // 7 Selects polarity for TRIP12 of EPWM-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union TRIPOUTINV_REG {
    Uint32  all;
    struct  TRIPOUTINV_BITS  bit;
};

struct TRIPLOCK_BITS {                  // bits description
    Uint16 LOCK:1;                      // 0 Locks the configuration for EPWM-XBAR
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 KEY:16;                      // 31:16 Write protection KEY
};

union TRIPLOCK_REG {
    Uint32  all;
    struct  TRIPLOCK_BITS  bit;
};

struct EPWM_XBAR_REGS {
    union   TRIP4MUX0TO15CFG_REG             TRIP4MUX0TO15CFG;             // ePWM XBAR Mux Configuration for TRIP4
    union   TRIP4MUX16TO31CFG_REG            TRIP4MUX16TO31CFG;            // ePWM XBAR Mux Configuration for TRIP4
    union   TRIP5MUX0TO15CFG_REG             TRIP5MUX0TO15CFG;             // ePWM XBAR Mux Configuration for TRIP5
    union   TRIP5MUX16TO31CFG_REG            TRIP5MUX16TO31CFG;            // ePWM XBAR Mux Configuration for TRIP5
    union   TRIP7MUX0TO15CFG_REG             TRIP7MUX0TO15CFG;             // ePWM XBAR Mux Configuration for TRIP7
    union   TRIP7MUX16TO31CFG_REG            TRIP7MUX16TO31CFG;            // ePWM XBAR Mux Configuration for TRIP7
    union   TRIP8MUX0TO15CFG_REG             TRIP8MUX0TO15CFG;             // ePWM XBAR Mux Configuration for TRIP8
    union   TRIP8MUX16TO31CFG_REG            TRIP8MUX16TO31CFG;            // ePWM XBAR Mux Configuration for TRIP8
    union   TRIP9MUX0TO15CFG_REG             TRIP9MUX0TO15CFG;             // ePWM XBAR Mux Configuration for TRIP9
    union   TRIP9MUX16TO31CFG_REG            TRIP9MUX16TO31CFG;            // ePWM XBAR Mux Configuration for TRIP9
    union   TRIP10MUX0TO15CFG_REG            TRIP10MUX0TO15CFG;            // ePWM XBAR Mux Configuration for TRIP10
    union   TRIP10MUX16TO31CFG_REG           TRIP10MUX16TO31CFG;           // ePWM XBAR Mux Configuration for TRIP10
    union   TRIP11MUX0TO15CFG_REG            TRIP11MUX0TO15CFG;            // ePWM XBAR Mux Configuration for TRIP11
    union   TRIP11MUX16TO31CFG_REG           TRIP11MUX16TO31CFG;           // ePWM XBAR Mux Configuration for TRIP11
    union   TRIP12MUX0TO15CFG_REG            TRIP12MUX0TO15CFG;            // ePWM XBAR Mux Configuration for TRIP12
    union   TRIP12MUX16TO31CFG_REG           TRIP12MUX16TO31CFG;           // ePWM XBAR Mux Configuration for TRIP12
    union   TRIP4MUXENABLE_REG               TRIP4MUXENABLE;               // ePWM XBAR Mux Enable for TRIP4
    union   TRIP5MUXENABLE_REG               TRIP5MUXENABLE;               // ePWM XBAR Mux Enable for TRIP5
    union   TRIP7MUXENABLE_REG               TRIP7MUXENABLE;               // ePWM XBAR Mux Enable for TRIP7
    union   TRIP8MUXENABLE_REG               TRIP8MUXENABLE;               // ePWM XBAR Mux Enable for TRIP8
    union   TRIP9MUXENABLE_REG               TRIP9MUXENABLE;               // ePWM XBAR Mux Enable for TRIP9
    union   TRIP10MUXENABLE_REG              TRIP10MUXENABLE;              // ePWM XBAR Mux Enable for TRIP10
    union   TRIP11MUXENABLE_REG              TRIP11MUXENABLE;              // ePWM XBAR Mux Enable for TRIP11
    union   TRIP12MUXENABLE_REG              TRIP12MUXENABLE;              // ePWM XBAR Mux Enable for TRIP12
    Uint16                                   rsvd1[8];                     // Reserved
    union   TRIPOUTINV_REG                   TRIPOUTINV;                   // ePWM XBAR Output Inversion Register
    Uint16                                   rsvd2[4];                     // Reserved
    union   TRIPLOCK_REG                     TRIPLOCK;                     // ePWM XBAR Configuration Lock register
};

//---------------------------------------------------------------------------
// EPWM_XBAR External References & Function Declarations:
//
extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_eqep.h
//
// TITLE:   F2807x Device EQEP Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// EQEP Individual Register Bit Definitions:

struct QDECCTL_BITS {                   // bits description
    Uint16 rsvd1:5;                     // 4:0 Reserved
    Uint16 QSP:1;                       // 5 QEPS input polarity
    Uint16 QIP:1;                       // 6 QEPI input polarity
    Uint16 QBP:1;                       // 7 QEPB input polarity
    Uint16 QAP:1;                       // 8 QEPA input polarity
    Uint16 IGATE:1;                     // 9 Index pulse gating option
    Uint16 SWAP:1;                      // 10 CLK/DIR Signal Source for Position Counter 
    Uint16 XCR:1;                       // 11 External Clock Rate
    Uint16 SPSEL:1;                     // 12 Sync output pin selection
    Uint16 SOEN:1;                      // 13 Sync output-enable
    Uint16 QSRC:2;                      // 15:14 Position-counter source selection
};

union QDECCTL_REG {
    Uint16  all;
    struct  QDECCTL_BITS  bit;
};

struct QEPCTL_BITS {                    // bits description
    Uint16 WDE:1;                       // 0 QEP watchdog enable 
    Uint16 UTE:1;                       // 1 QEP unit timer enable
    Uint16 QCLM:1;                      // 2 QEP capture latch mode 
    Uint16 QPEN:1;                      // 3 Quadrature postotion counter enable 
    Uint16 IEL:2;                       // 5:4 Index event latch 
    Uint16 SEL:1;                       // 6 Strobe event latch 
    Uint16 SWI:1;                       // 7 Software init position counter
    Uint16 IEI:2;                       // 9:8 Index event init of position count 
    Uint16 SEI:2;                       // 11:10 Strobe event init 
    Uint16 PCRM:2;                      // 13:12 Postion counter reset 
    Uint16 FREE_SOFT:2;                 // 15:14 Emulation mode 
};

union QEPCTL_REG {
    Uint16  all;
    struct  QEPCTL_BITS  bit;
};

struct QCAPCTL_BITS {                   // bits description
    Uint16 UPPS:4;                      // 3:0 Unit position event prescaler
    Uint16 CCPS:3;                      // 6:4 eQEP capture timer clock prescaler
    Uint16 rsvd1:8;                     // 14:7 Reserved
    Uint16 CEN:1;                       // 15 Enable eQEP capture
};

union QCAPCTL_REG {
    Uint16  all;
    struct  QCAPCTL_BITS  bit;
};

struct QPOSCTL_BITS {                   // bits description
    Uint16 PCSPW:12;                    // 11:0 Position compare sync pulse width 
    Uint16 PCE:1;                       // 12 Position compare enable/disable 
    Uint16 PCPOL:1;                     // 13 Polarity of sync output 
    Uint16 PCLOAD:1;                    // 14 Position compare of shadow load 
    Uint16 PCSHDW:1;                    // 15 Position compare of shadow enable
};

union QPOSCTL_REG {
    Uint16  all;
    struct  QPOSCTL_BITS  bit;
};

struct QEINT_BITS {                     // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 PCE:1;                       // 1 Position counter error interrupt enable
    Uint16 QPE:1;                       // 2 Quadrature phase error interrupt enable
    Uint16 QDC:1;                       // 3 Quadrature direction change interrupt enable
    Uint16 WTO:1;                       // 4 Watchdog time out interrupt enable
    Uint16 PCU:1;                       // 5 Position counter underflow interrupt enable
    Uint16 PCO:1;                       // 6 Position counter overflow interrupt enable
    Uint16 PCR:1;                       // 7 Position-compare ready interrupt enable
    Uint16 PCM:1;                       // 8 Position-compare match interrupt enable
    Uint16 SEL:1;                       // 9 Strobe event latch interrupt enable
    Uint16 IEL:1;                       // 10 Index event latch interrupt enable
    Uint16 UTO:1;                       // 11 Unit time out interrupt enable
    Uint16 rsvd2:4;                     // 15:12 Reserved
};

union QEINT_REG {
    Uint16  all;
    struct  QEINT_BITS  bit;
};

struct QFLG_BITS {                      // bits description
    Uint16 INT:1;                       // 0 Global interrupt status flag
    Uint16 PCE:1;                       // 1 Position counter error interrupt flag
    Uint16 PHE:1;                       // 2 Quadrature phase error interrupt flag
    Uint16 QDC:1;                       // 3 Quadrature direction change interrupt flag
    Uint16 WTO:1;                       // 4 Watchdog timeout interrupt flag
    Uint16 PCU:1;                       // 5 Position counter underflow interrupt flag
    Uint16 PCO:1;                       // 6 Position counter overflow interrupt flag
    Uint16 PCR:1;                       // 7 Position-compare ready interrupt flag
    Uint16 PCM:1;                       // 8 eQEP compare match event interrupt flag
    Uint16 SEL:1;                       // 9 Strobe event latch interrupt flag
    Uint16 IEL:1;                       // 10 Index event latch interrupt flag
    Uint16 UTO:1;                       // 11 Unit time out interrupt flag
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union QFLG_REG {
    Uint16  all;
    struct  QFLG_BITS  bit;
};

struct QCLR_BITS {                      // bits description
    Uint16 INT:1;                       // 0 Global interrupt clear flag
    Uint16 PCE:1;                       // 1 Clear position counter error interrupt flag
    Uint16 PHE:1;                       // 2 Clear quadrature phase error interrupt flag
    Uint16 QDC:1;                       // 3 Clear quadrature direction change interrupt flag
    Uint16 WTO:1;                       // 4 Clear watchdog timeout interrupt flag
    Uint16 PCU:1;                       // 5 Clear position counter underflow interrupt flag
    Uint16 PCO:1;                       // 6 Clear position counter overflow interrupt flag
    Uint16 PCR:1;                       // 7 Clear position-compare ready interrupt flag
    Uint16 PCM:1;                       // 8 Clear eQEP compare match event interrupt flag
    Uint16 SEL:1;                       // 9 Clear strobe event latch interrupt flag
    Uint16 IEL:1;                       // 10 Clear index event latch interrupt flag
    Uint16 UTO:1;                       // 11 Clear unit time out interrupt flag
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union QCLR_REG {
    Uint16  all;
    struct  QCLR_BITS  bit;
};

struct QFRC_BITS {                      // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 PCE:1;                       // 1 Force position counter error interrupt
    Uint16 PHE:1;                       // 2 Force quadrature phase error interrupt
    Uint16 QDC:1;                       // 3 Force quadrature direction change interrupt
    Uint16 WTO:1;                       // 4 Force watchdog time out interrupt
    Uint16 PCU:1;                       // 5 Force position counter underflow interrupt
    Uint16 PCO:1;                       // 6 Force position counter overflow interrupt
    Uint16 PCR:1;                       // 7 Force position-compare ready interrupt
    Uint16 PCM:1;                       // 8 Force position-compare match interrupt
    Uint16 SEL:1;                       // 9 Force strobe event latch interrupt
    Uint16 IEL:1;                       // 10 Force index event latch interrupt
    Uint16 UTO:1;                       // 11 Force unit time out interrupt
    Uint16 rsvd2:4;                     // 15:12 Reserved
};

union QFRC_REG {
    Uint16  all;
    struct  QFRC_BITS  bit;
};

struct QEPSTS_BITS {                    // bits description
    Uint16 PCEF:1;                      // 0 Position counter error flag.
    Uint16 FIMF:1;                      // 1 First index marker flag
    Uint16 CDEF:1;                      // 2 Capture direction error flag
    Uint16 COEF:1;                      // 3 Capture overflow error flag
    Uint16 QDLF:1;                      // 4 eQEP direction latch flag
    Uint16 QDF:1;                       // 5 Quadrature direction flag
    Uint16 FIDF:1;                      // 6 The first index marker
    Uint16 UPEVNT:1;                    // 7 Unit position event flag
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union QEPSTS_REG {
    Uint16  all;
    struct  QEPSTS_BITS  bit;
};

struct EQEP_REGS {
    Uint32                                   QPOSCNT;                      // Position Counter 
    Uint32                                   QPOSINIT;                     // Position Counter Init 
    Uint32                                   QPOSMAX;                      // Maximum Position Count 
    Uint32                                   QPOSCMP;                      // Position Compare 
    Uint32                                   QPOSILAT;                     // Index Position Latch 
    Uint32                                   QPOSSLAT;                     // Strobe Position Latch
    Uint32                                   QPOSLAT;                      // Position Latch 
    Uint32                                   QUTMR;                        // QEP Unit Timer 
    Uint32                                   QUPRD;                        // QEP Unit Period 
    Uint16                                   QWDTMR;                       // QEP Watchdog Timer 
    Uint16                                   QWDPRD;                       // QEP Watchdog Period 
    union   QDECCTL_REG                      QDECCTL;                      // Quadrature Decoder Control 
    union   QEPCTL_REG                       QEPCTL;                       // QEP Control 
    union   QCAPCTL_REG                      QCAPCTL;                      // Qaudrature Capture Control 
    union   QPOSCTL_REG                      QPOSCTL;                      // Position Compare Control 
    union   QEINT_REG                        QEINT;                        // QEP Interrupt Control 
    union   QFLG_REG                         QFLG;                         // QEP Interrupt Flag 
    union   QCLR_REG                         QCLR;                         // QEP Interrupt Clear 
    union   QFRC_REG                         QFRC;                         // QEP Interrupt Force 
    union   QEPSTS_REG                       QEPSTS;                       // QEP Status 
    Uint16                                   QCTMR;                        // QEP Capture Timer 
    Uint16                                   QCPRD;                        // QEP Capture Period 
    Uint16                                   QCTMRLAT;                     // QEP Capture Latch 
    Uint16                                   QCPRDLAT;                     // QEP Capture Period Latch 
    Uint16                                   rsvd1;                        // Reserved
};

//---------------------------------------------------------------------------
// EQEP External References & Function Declarations:
//
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
extern volatile struct EQEP_REGS EQep3Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_flash.h
//
// TITLE:   F2807x Device FLASH Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// FLASH Individual Register Bit Definitions:

struct FRDCNTL_BITS {                   // bits description
    Uint16 rsvd1:8;                     // 7:0 Reserved
    Uint16 RWAIT:4;                     // 11:8 Random Read Waitstate
    Uint16 rsvd2:4;                     // 15:12 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union FRDCNTL_REG {
    Uint32  all;
    struct  FRDCNTL_BITS  bit;
};

struct FBAC_BITS {                      // bits description
    Uint16 VREADST:8;                   // 7:0 VREAD Setup Time Count
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FBAC_REG {
    Uint32  all;
    struct  FBAC_BITS  bit;
};

struct FBFALLBACK_BITS {                // bits description
    Uint16 BNKPWR0:2;                   // 1:0 Bank Power Mode
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FBFALLBACK_REG {
    Uint32  all;
    struct  FBFALLBACK_BITS  bit;
};

struct FBPRDY_BITS {                    // bits description
    Uint16 BANKRDY:1;                   // 0 Flash Bank Active Power State
    Uint16 rsvd1:14;                    // 14:1 Reserved
    Uint16 PUMPRDY:1;                   // 15 Flash Pump Active Power Mode
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FBPRDY_REG {
    Uint32  all;
    struct  FBPRDY_BITS  bit;
};

struct FPAC1_BITS {                     // bits description
    Uint16 PMPPWR:1;                    // 0 Charge Pump Fallback Power Mode
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 PSLEEP:12;                   // 27:16 Pump Sleep Down Count
    Uint16 rsvd2:4;                     // 31:28 Reserved
};

union FPAC1_REG {
    Uint32  all;
    struct  FPAC1_BITS  bit;
};

struct FMAC_BITS {                      // bits description
    Uint16 BANK:3;                      // 2:0 Flash Bank for FSM and Software Interface Operations
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FMAC_REG {
    Uint32  all;
    struct  FMAC_BITS  bit;
};

struct FMSTAT_BITS {                    // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 VOLTSTAT:1;                  // 3 Flash Pump Power Status
    Uint16 CSTAT:1;                     // 4 Command Fail Status
    Uint16 INVDAT:1;                    // 5 Invalid Data
    Uint16 PGM:1;                       // 6 Program Operation Status
    Uint16 ERS:1;                       // 7 Erase Operation Status
    Uint16 BUSY:1;                      // 8 Busy Bit
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 EV:1;                        // 10 Erase Verify Status
    Uint16 rsvd5:1;                     // 11 Reserved
    Uint16 PGV:1;                       // 12 Programming Verify Status
    Uint16 rsvd6:1;                     // 13 Reserved
    Uint16 ILA:1;                       // 14 Illegal Address Detected
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:14;                   // 31:18 Reserved
};

union FMSTAT_REG {
    Uint32  all;
    struct  FMSTAT_BITS  bit;
};

struct FRD_INTF_CTRL_BITS {             // bits description
    Uint16 PREFETCH_EN:1;               // 0 Prefetch Enable
    Uint16 DATA_CACHE_EN:1;             // 1 Data Cache Enable
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FRD_INTF_CTRL_REG {
    Uint32  all;
    struct  FRD_INTF_CTRL_BITS  bit;
};

struct FLASH_CTRL_REGS {
    union   FRDCNTL_REG                      FRDCNTL;                      // Flash Read Control Register
    Uint16                                   rsvd1[28];                    // Reserved
    union   FBAC_REG                         FBAC;                         // Flash Bank Access Control Register
    union   FBFALLBACK_REG                   FBFALLBACK;                   // Flash Bank Fallback Power Register
    union   FBPRDY_REG                       FBPRDY;                       // Flash Bank Pump Ready Register
    union   FPAC1_REG                        FPAC1;                        // Flash Pump Access Control Register 1
    Uint16                                   rsvd2[2];                     // Reserved
    union   FMAC_REG                         FMAC;                         // Flash Module Access Control Register
    union   FMSTAT_REG                       FMSTAT;                       // Flash Module Status Register
    Uint16                                   rsvd3[340];                   // Reserved
    union   FRD_INTF_CTRL_REG                FRD_INTF_CTRL;                // Flash Read Interface Control Register
};

struct ECC_ENABLE_BITS {                // bits description
    Uint16 ECCENABLE:4;                    // 3:0 Enable ECC
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union ECC_ENABLE_REG {
    Uint32  all;
    struct  ECC_ENABLE_BITS  bit;
};

struct ERR_STATUS_BITS {                // bits description
    Uint16 FAIL_0_L:1;                  // 0 Lower 64bits Single Bit Error Corrected Value 0
    Uint16 FAIL_1_L:1;                  // 1 Lower 64bits Single Bit Error Corrected Value 1
    Uint16 UNC_ERR_L:1;                 // 2 Lower 64 bits Uncorrectable error occurred
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 FAIL_0_H:1;                  // 16 Upper 64bits Single Bit Error Corrected Value 0
    Uint16 FAIL_1_H:1;                  // 17 Upper 64bits Single Bit Error Corrected Value 1
    Uint16 UNC_ERR_H:1;                 // 18 Upper 64 bits Uncorrectable error occurred
    Uint16 rsvd2:13;                    // 31:19 Reserved
};

union ERR_STATUS_REG {
    Uint32  all;
    struct  ERR_STATUS_BITS  bit;
};

struct ERR_POS_BITS {                   // bits description
    Uint16 ERR_POS_L:6;                 // 5:0 Bit Position of Single bit Error in lower 64 bits
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 ERR_TYPE_L:1;                // 8 Error Type in lower 64 bits
    Uint16 rsvd2:7;                     // 15:9 Reserved
    Uint16 ERR_POS_H:6;                 // 21:16 Bit Position of Single bit Error in upper 64 bits
    Uint16 rsvd3:2;                     // 23:22 Reserved
    Uint16 ERR_TYPE_H:1;                // 24 Error Type in upper 64 bits
    Uint16 rsvd4:7;                     // 31:25 Reserved
};

union ERR_POS_REG {
    Uint32  all;
    struct  ERR_POS_BITS  bit;
};

struct ERR_STATUS_CLR_BITS {            // bits description
    Uint16 FAIL_0_L_CLR:1;              // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear
    Uint16 FAIL_1_L_CLR:1;              // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear
    Uint16 UNC_ERR_L_CLR:1;             // 2 Lower 64 bits Uncorrectable error occurred Clear
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 FAIL_0_H_CLR:1;              // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear
    Uint16 FAIL_1_H_CLR:1;              // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear
    Uint16 UNC_ERR_H_CLR:1;             // 18 Upper 64 bits Uncorrectable error occurred Clear
    Uint16 rsvd2:13;                    // 31:19 Reserved
};

union ERR_STATUS_CLR_REG {
    Uint32  all;
    struct  ERR_STATUS_CLR_BITS  bit;
};

struct ERR_CNT_BITS {                   // bits description
    Uint16 ERR_CNT:16;                  // 15:0 Error counter
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union ERR_CNT_REG {
    Uint32  all;
    struct  ERR_CNT_BITS  bit;
};

struct ERR_THRESHOLD_BITS {             // bits description
    Uint16 ERR_THRESHOLD:16;            // 15:0 Error Threshold
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union ERR_THRESHOLD_REG {
    Uint32  all;
    struct  ERR_THRESHOLD_BITS  bit;
};

struct ERR_INTFLG_BITS {                // bits description
    Uint16 SINGLE_ERR_INTFLG:1;         // 0 Single Error Interrupt Flag
    Uint16 UNC_ERR_INTFLG:1;            // 1 Uncorrectable Interrupt Flag
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union ERR_INTFLG_REG {
    Uint32  all;
    struct  ERR_INTFLG_BITS  bit;
};

struct ERR_INTCLR_BITS {                // bits description
    Uint16 SINGLE_ERR_INTCLR:1;         // 0 Single Error Interrupt Flag Clear
    Uint16 UNC_ERR_INTCLR:1;            // 1 Uncorrectable Interrupt Flag Clear
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union ERR_INTCLR_REG {
    Uint32  all;
    struct  ERR_INTCLR_BITS  bit;
};

struct FADDR_TEST_BITS {                // bits description
    Uint16 rsvd1:3;                     // 2:0 Reserved
    Uint16 ADDRL:13;                    // 15:3 ECC Address Low
    Uint16 ADDRH:6;                     // 21:16 ECC Address High
    Uint16 rsvd2:10;                    // 31:22 Reserved
};

union FADDR_TEST_REG {
    Uint32  all;
    struct  FADDR_TEST_BITS  bit;
};

struct FECC_TEST_BITS {                 // bits description
    Uint16 ECC:8;                       // 7:0 ECC Control Bits
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FECC_TEST_REG {
    Uint32  all;
    struct  FECC_TEST_BITS  bit;
};

struct FECC_CTRL_BITS {                 // bits description
    Uint16 ECC_TEST_EN:1;               // 0 Enable ECC Test Logic
    Uint16 ECC_SELECT:1;                // 1 ECC Bit Select
    Uint16 DO_ECC_CALC:1;               // 2 Enable ECC Calculation
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FECC_CTRL_REG {
    Uint32  all;
    struct  FECC_CTRL_BITS  bit;
};

struct FECC_STATUS_BITS {               // bits description
    Uint16 SINGLE_ERR:1;                // 0 Test Result is Single Bit Error
    Uint16 UNC_ERR:1;                   // 1 Test Result is Uncorrectable Error
    Uint16 DATA_ERR_POS:6;              // 7:2 Holds Bit Position of Error
    Uint16 ERR_TYPE:1;                  // 8 Holds Bit Position of 8 Check Bits of Error
    Uint16 rsvd1:7;                     // 15:9 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FECC_STATUS_REG {
    Uint32  all;
    struct  FECC_STATUS_BITS  bit;
};

struct FLASH_ECC_REGS {
    union   ECC_ENABLE_REG                   ECC_ENABLE;                   // ECC Enable
    Uint32                                   SINGLE_ERR_ADDR_LOW;          // Single Error Address Low
    Uint32                                   SINGLE_ERR_ADDR_HIGH;         // Single Error Address High
    Uint32                                   UNC_ERR_ADDR_LOW;             // Uncorrectable Error Address Low
    Uint32                                   UNC_ERR_ADDR_HIGH;            // Uncorrectable Error Address High
    union   ERR_STATUS_REG                   ERR_STATUS;                   // Error Status
    union   ERR_POS_REG                      ERR_POS;                      // Error Position
    union   ERR_STATUS_CLR_REG               ERR_STATUS_CLR;               // Error Status Clear
    union   ERR_CNT_REG                      ERR_CNT;                      // Error Control
    union   ERR_THRESHOLD_REG                ERR_THRESHOLD;                // Error Threshold
    union   ERR_INTFLG_REG                   ERR_INTFLG;                   // Error Interrupt Flag
    union   ERR_INTCLR_REG                   ERR_INTCLR;                   // Error Interrupt Flag Clear
    Uint32                                   FDATAH_TEST;                  // Data High Test
    Uint32                                   FDATAL_TEST;                  // Data Low Test
    union   FADDR_TEST_REG                   FADDR_TEST;                   // ECC Test Address
    union   FECC_TEST_REG                    FECC_TEST;                    // ECC Test Address
    union   FECC_CTRL_REG                    FECC_CTRL;                    // ECC Control
    Uint32                                   FOUTH_TEST;                   // Test Data Out High
    Uint32                                   FOUTL_TEST;                   // Test Data Out Low
    union   FECC_STATUS_REG                  FECC_STATUS;                  // ECC Status
};

//---------------------------------------------------------------------------
// FLASH External References & Function Declarations:
//
extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
extern volatile struct FLASH_ECC_REGS Flash0EccRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_gpio.h
//
// TITLE:   F2807x Device GPIO Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// GPIO Individual Register Bit Definitions:

struct GPACTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO0 to GPIO7
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO8 to GPIO15
    Uint16 QUALPRD2:8;                  // 23:16 Qualification sampling period for GPIO16 to GPIO23
    Uint16 QUALPRD3:8;                  // 31:24 Qualification sampling period for GPIO24 to GPIO31
};

union GPACTRL_REG {
    Uint32  all;
    struct  GPACTRL_BITS  bit;
};

struct GPAQSEL1_BITS {                  // bits description
    Uint16 GPIO0:2;                     // 1:0 Select input qualification type for GPIO0
    Uint16 GPIO1:2;                     // 3:2 Select input qualification type for GPIO1
    Uint16 GPIO2:2;                     // 5:4 Select input qualification type for GPIO2
    Uint16 GPIO3:2;                     // 7:6 Select input qualification type for GPIO3
    Uint16 GPIO4:2;                     // 9:8 Select input qualification type for GPIO4
    Uint16 GPIO5:2;                     // 11:10 Select input qualification type for GPIO5
    Uint16 GPIO6:2;                     // 13:12 Select input qualification type for GPIO6
    Uint16 GPIO7:2;                     // 15:14 Select input qualification type for GPIO7
    Uint16 GPIO8:2;                     // 17:16 Select input qualification type for GPIO8
    Uint16 GPIO9:2;                     // 19:18 Select input qualification type for GPIO9
    Uint16 GPIO10:2;                    // 21:20 Select input qualification type for GPIO10
    Uint16 GPIO11:2;                    // 23:22 Select input qualification type for GPIO11
    Uint16 GPIO12:2;                    // 25:24 Select input qualification type for GPIO12
    Uint16 GPIO13:2;                    // 27:26 Select input qualification type for GPIO13
    Uint16 GPIO14:2;                    // 29:28 Select input qualification type for GPIO14
    Uint16 GPIO15:2;                    // 31:30 Select input qualification type for GPIO15
};

union GPAQSEL1_REG {
    Uint32  all;
    struct  GPAQSEL1_BITS  bit;
};

struct GPAQSEL2_BITS {                  // bits description
    Uint16 GPIO16:2;                    // 1:0 Select input qualification type for GPIO16
    Uint16 GPIO17:2;                    // 3:2 Select input qualification type for GPIO17
    Uint16 GPIO18:2;                    // 5:4 Select input qualification type for GPIO18
    Uint16 GPIO19:2;                    // 7:6 Select input qualification type for GPIO19
    Uint16 GPIO20:2;                    // 9:8 Select input qualification type for GPIO20
    Uint16 GPIO21:2;                    // 11:10 Select input qualification type for GPIO21
    Uint16 GPIO22:2;                    // 13:12 Select input qualification type for GPIO22
    Uint16 GPIO23:2;                    // 15:14 Select input qualification type for GPIO23
    Uint16 GPIO24:2;                    // 17:16 Select input qualification type for GPIO24
    Uint16 GPIO25:2;                    // 19:18 Select input qualification type for GPIO25
    Uint16 GPIO26:2;                    // 21:20 Select input qualification type for GPIO26
    Uint16 GPIO27:2;                    // 23:22 Select input qualification type for GPIO27
    Uint16 GPIO28:2;                    // 25:24 Select input qualification type for GPIO28
    Uint16 GPIO29:2;                    // 27:26 Select input qualification type for GPIO29
    Uint16 GPIO30:2;                    // 29:28 Select input qualification type for GPIO30
    Uint16 GPIO31:2;                    // 31:30 Select input qualification type for GPIO31
};

union GPAQSEL2_REG {
    Uint32  all;
    struct  GPAQSEL2_BITS  bit;
};

struct GPAMUX1_BITS {                   // bits description
    Uint16 GPIO0:2;                     // 1:0 Defines pin-muxing selection for GPIO0
    Uint16 GPIO1:2;                     // 3:2 Defines pin-muxing selection for GPIO1
    Uint16 GPIO2:2;                     // 5:4 Defines pin-muxing selection for GPIO2
    Uint16 GPIO3:2;                     // 7:6 Defines pin-muxing selection for GPIO3
    Uint16 GPIO4:2;                     // 9:8 Defines pin-muxing selection for GPIO4
    Uint16 GPIO5:2;                     // 11:10 Defines pin-muxing selection for GPIO5
    Uint16 GPIO6:2;                     // 13:12 Defines pin-muxing selection for GPIO6
    Uint16 GPIO7:2;                     // 15:14 Defines pin-muxing selection for GPIO7
    Uint16 GPIO8:2;                     // 17:16 Defines pin-muxing selection for GPIO8
    Uint16 GPIO9:2;                     // 19:18 Defines pin-muxing selection for GPIO9
    Uint16 GPIO10:2;                    // 21:20 Defines pin-muxing selection for GPIO10
    Uint16 GPIO11:2;                    // 23:22 Defines pin-muxing selection for GPIO11
    Uint16 GPIO12:2;                    // 25:24 Defines pin-muxing selection for GPIO12
    Uint16 GPIO13:2;                    // 27:26 Defines pin-muxing selection for GPIO13
    Uint16 GPIO14:2;                    // 29:28 Defines pin-muxing selection for GPIO14
    Uint16 GPIO15:2;                    // 31:30 Defines pin-muxing selection for GPIO15
};

union GPAMUX1_REG {
    Uint32  all;
    struct  GPAMUX1_BITS  bit;
};

struct GPAMUX2_BITS {                   // bits description
    Uint16 GPIO16:2;                    // 1:0 Defines pin-muxing selection for GPIO16
    Uint16 GPIO17:2;                    // 3:2 Defines pin-muxing selection for GPIO17
    Uint16 GPIO18:2;                    // 5:4 Defines pin-muxing selection for GPIO18
    Uint16 GPIO19:2;                    // 7:6 Defines pin-muxing selection for GPIO19
    Uint16 GPIO20:2;                    // 9:8 Defines pin-muxing selection for GPIO20
    Uint16 GPIO21:2;                    // 11:10 Defines pin-muxing selection for GPIO21
    Uint16 GPIO22:2;                    // 13:12 Defines pin-muxing selection for GPIO22
    Uint16 GPIO23:2;                    // 15:14 Defines pin-muxing selection for GPIO23
    Uint16 GPIO24:2;                    // 17:16 Defines pin-muxing selection for GPIO24
    Uint16 GPIO25:2;                    // 19:18 Defines pin-muxing selection for GPIO25
    Uint16 GPIO26:2;                    // 21:20 Defines pin-muxing selection for GPIO26
    Uint16 GPIO27:2;                    // 23:22 Defines pin-muxing selection for GPIO27
    Uint16 GPIO28:2;                    // 25:24 Defines pin-muxing selection for GPIO28
    Uint16 GPIO29:2;                    // 27:26 Defines pin-muxing selection for GPIO29
    Uint16 GPIO30:2;                    // 29:28 Defines pin-muxing selection for GPIO30
    Uint16 GPIO31:2;                    // 31:30 Defines pin-muxing selection for GPIO31
};

union GPAMUX2_REG {
    Uint32  all;
    struct  GPAMUX2_BITS  bit;
};

struct GPADIR_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO1:1;                     // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO2:1;                     // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO3:1;                     // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO4:1;                     // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO5:1;                     // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO6:1;                     // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO7:1;                     // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO8:1;                     // 8 Defines direction for this pin in GPIO mode
    Uint16 GPIO9:1;                     // 9 Defines direction for this pin in GPIO mode
    Uint16 GPIO10:1;                    // 10 Defines direction for this pin in GPIO mode
    Uint16 GPIO11:1;                    // 11 Defines direction for this pin in GPIO mode
    Uint16 GPIO12:1;                    // 12 Defines direction for this pin in GPIO mode
    Uint16 GPIO13:1;                    // 13 Defines direction for this pin in GPIO mode
    Uint16 GPIO14:1;                    // 14 Defines direction for this pin in GPIO mode
    Uint16 GPIO15:1;                    // 15 Defines direction for this pin in GPIO mode
    Uint16 GPIO16:1;                    // 16 Defines direction for this pin in GPIO mode
    Uint16 GPIO17:1;                    // 17 Defines direction for this pin in GPIO mode
    Uint16 GPIO18:1;                    // 18 Defines direction for this pin in GPIO mode
    Uint16 GPIO19:1;                    // 19 Defines direction for this pin in GPIO mode
    Uint16 GPIO20:1;                    // 20 Defines direction for this pin in GPIO mode
    Uint16 GPIO21:1;                    // 21 Defines direction for this pin in GPIO mode
    Uint16 GPIO22:1;                    // 22 Defines direction for this pin in GPIO mode
    Uint16 GPIO23:1;                    // 23 Defines direction for this pin in GPIO mode
    Uint16 GPIO24:1;                    // 24 Defines direction for this pin in GPIO mode
    Uint16 GPIO25:1;                    // 25 Defines direction for this pin in GPIO mode
    Uint16 GPIO26:1;                    // 26 Defines direction for this pin in GPIO mode
    Uint16 GPIO27:1;                    // 27 Defines direction for this pin in GPIO mode
    Uint16 GPIO28:1;                    // 28 Defines direction for this pin in GPIO mode
    Uint16 GPIO29:1;                    // 29 Defines direction for this pin in GPIO mode
    Uint16 GPIO30:1;                    // 30 Defines direction for this pin in GPIO mode
    Uint16 GPIO31:1;                    // 31 Defines direction for this pin in GPIO mode
};

union GPADIR_REG {
    Uint32  all;
    struct  GPADIR_BITS  bit;
};

struct GPAPUD_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Pull-Up Disable control for this pin
    Uint16 GPIO1:1;                     // 1 Pull-Up Disable control for this pin
    Uint16 GPIO2:1;                     // 2 Pull-Up Disable control for this pin
    Uint16 GPIO3:1;                     // 3 Pull-Up Disable control for this pin
    Uint16 GPIO4:1;                     // 4 Pull-Up Disable control for this pin
    Uint16 GPIO5:1;                     // 5 Pull-Up Disable control for this pin
    Uint16 GPIO6:1;                     // 6 Pull-Up Disable control for this pin
    Uint16 GPIO7:1;                     // 7 Pull-Up Disable control for this pin
    Uint16 GPIO8:1;                     // 8 Pull-Up Disable control for this pin
    Uint16 GPIO9:1;                     // 9 Pull-Up Disable control for this pin
    Uint16 GPIO10:1;                    // 10 Pull-Up Disable control for this pin
    Uint16 GPIO11:1;                    // 11 Pull-Up Disable control for this pin
    Uint16 GPIO12:1;                    // 12 Pull-Up Disable control for this pin
    Uint16 GPIO13:1;                    // 13 Pull-Up Disable control for this pin
    Uint16 GPIO14:1;                    // 14 Pull-Up Disable control for this pin
    Uint16 GPIO15:1;                    // 15 Pull-Up Disable control for this pin
    Uint16 GPIO16:1;                    // 16 Pull-Up Disable control for this pin
    Uint16 GPIO17:1;                    // 17 Pull-Up Disable control for this pin
    Uint16 GPIO18:1;                    // 18 Pull-Up Disable control for this pin
    Uint16 GPIO19:1;                    // 19 Pull-Up Disable control for this pin
    Uint16 GPIO20:1;                    // 20 Pull-Up Disable control for this pin
    Uint16 GPIO21:1;                    // 21 Pull-Up Disable control for this pin
    Uint16 GPIO22:1;                    // 22 Pull-Up Disable control for this pin
    Uint16 GPIO23:1;                    // 23 Pull-Up Disable control for this pin
    Uint16 GPIO24:1;                    // 24 Pull-Up Disable control for this pin
    Uint16 GPIO25:1;                    // 25 Pull-Up Disable control for this pin
    Uint16 GPIO26:1;                    // 26 Pull-Up Disable control for this pin
    Uint16 GPIO27:1;                    // 27 Pull-Up Disable control for this pin
    Uint16 GPIO28:1;                    // 28 Pull-Up Disable control for this pin
    Uint16 GPIO29:1;                    // 29 Pull-Up Disable control for this pin
    Uint16 GPIO30:1;                    // 30 Pull-Up Disable control for this pin
    Uint16 GPIO31:1;                    // 31 Pull-Up Disable control for this pin
};

union GPAPUD_REG {
    Uint32  all;
    struct  GPAPUD_BITS  bit;
};

struct GPAINV_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Input inversion control for this pin
    Uint16 GPIO1:1;                     // 1 Input inversion control for this pin
    Uint16 GPIO2:1;                     // 2 Input inversion control for this pin
    Uint16 GPIO3:1;                     // 3 Input inversion control for this pin
    Uint16 GPIO4:1;                     // 4 Input inversion control for this pin
    Uint16 GPIO5:1;                     // 5 Input inversion control for this pin
    Uint16 GPIO6:1;                     // 6 Input inversion control for this pin
    Uint16 GPIO7:1;                     // 7 Input inversion control for this pin
    Uint16 GPIO8:1;                     // 8 Input inversion control for this pin
    Uint16 GPIO9:1;                     // 9 Input inversion control for this pin
    Uint16 GPIO10:1;                    // 10 Input inversion control for this pin
    Uint16 GPIO11:1;                    // 11 Input inversion control for this pin
    Uint16 GPIO12:1;                    // 12 Input inversion control for this pin
    Uint16 GPIO13:1;                    // 13 Input inversion control for this pin
    Uint16 GPIO14:1;                    // 14 Input inversion control for this pin
    Uint16 GPIO15:1;                    // 15 Input inversion control for this pin
    Uint16 GPIO16:1;                    // 16 Input inversion control for this pin
    Uint16 GPIO17:1;                    // 17 Input inversion control for this pin
    Uint16 GPIO18:1;                    // 18 Input inversion control for this pin
    Uint16 GPIO19:1;                    // 19 Input inversion control for this pin
    Uint16 GPIO20:1;                    // 20 Input inversion control for this pin
    Uint16 GPIO21:1;                    // 21 Input inversion control for this pin
    Uint16 GPIO22:1;                    // 22 Input inversion control for this pin
    Uint16 GPIO23:1;                    // 23 Input inversion control for this pin
    Uint16 GPIO24:1;                    // 24 Input inversion control for this pin
    Uint16 GPIO25:1;                    // 25 Input inversion control for this pin
    Uint16 GPIO26:1;                    // 26 Input inversion control for this pin
    Uint16 GPIO27:1;                    // 27 Input inversion control for this pin
    Uint16 GPIO28:1;                    // 28 Input inversion control for this pin
    Uint16 GPIO29:1;                    // 29 Input inversion control for this pin
    Uint16 GPIO30:1;                    // 30 Input inversion control for this pin
    Uint16 GPIO31:1;                    // 31 Input inversion control for this pin
};

union GPAINV_REG {
    Uint32  all;
    struct  GPAINV_BITS  bit;
};

struct GPAODR_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO1:1;                     // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO2:1;                     // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO3:1;                     // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO4:1;                     // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO5:1;                     // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO6:1;                     // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO7:1;                     // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO8:1;                     // 8 Outpout Open-Drain control for this pin
    Uint16 GPIO9:1;                     // 9 Outpout Open-Drain control for this pin
    Uint16 GPIO10:1;                    // 10 Outpout Open-Drain control for this pin
    Uint16 GPIO11:1;                    // 11 Outpout Open-Drain control for this pin
    Uint16 GPIO12:1;                    // 12 Outpout Open-Drain control for this pin
    Uint16 GPIO13:1;                    // 13 Outpout Open-Drain control for this pin
    Uint16 GPIO14:1;                    // 14 Outpout Open-Drain control for this pin
    Uint16 GPIO15:1;                    // 15 Outpout Open-Drain control for this pin
    Uint16 GPIO16:1;                    // 16 Outpout Open-Drain control for this pin
    Uint16 GPIO17:1;                    // 17 Outpout Open-Drain control for this pin
    Uint16 GPIO18:1;                    // 18 Outpout Open-Drain control for this pin
    Uint16 GPIO19:1;                    // 19 Outpout Open-Drain control for this pin
    Uint16 GPIO20:1;                    // 20 Outpout Open-Drain control for this pin
    Uint16 GPIO21:1;                    // 21 Outpout Open-Drain control for this pin
    Uint16 GPIO22:1;                    // 22 Outpout Open-Drain control for this pin
    Uint16 GPIO23:1;                    // 23 Outpout Open-Drain control for this pin
    Uint16 GPIO24:1;                    // 24 Outpout Open-Drain control for this pin
    Uint16 GPIO25:1;                    // 25 Outpout Open-Drain control for this pin
    Uint16 GPIO26:1;                    // 26 Outpout Open-Drain control for this pin
    Uint16 GPIO27:1;                    // 27 Outpout Open-Drain control for this pin
    Uint16 GPIO28:1;                    // 28 Outpout Open-Drain control for this pin
    Uint16 GPIO29:1;                    // 29 Outpout Open-Drain control for this pin
    Uint16 GPIO30:1;                    // 30 Outpout Open-Drain control for this pin
    Uint16 GPIO31:1;                    // 31 Outpout Open-Drain control for this pin
};

union GPAODR_REG {
    Uint32  all;
    struct  GPAODR_BITS  bit;
};

struct GPAGMUX1_BITS {                  // bits description
    Uint16 GPIO0:2;                     // 1:0 Defines pin-muxing selection for GPIO0
    Uint16 GPIO1:2;                     // 3:2 Defines pin-muxing selection for GPIO1
    Uint16 GPIO2:2;                     // 5:4 Defines pin-muxing selection for GPIO2
    Uint16 GPIO3:2;                     // 7:6 Defines pin-muxing selection for GPIO3
    Uint16 GPIO4:2;                     // 9:8 Defines pin-muxing selection for GPIO4
    Uint16 GPIO5:2;                     // 11:10 Defines pin-muxing selection for GPIO5
    Uint16 GPIO6:2;                     // 13:12 Defines pin-muxing selection for GPIO6
    Uint16 GPIO7:2;                     // 15:14 Defines pin-muxing selection for GPIO7
    Uint16 GPIO8:2;                     // 17:16 Defines pin-muxing selection for GPIO8
    Uint16 GPIO9:2;                     // 19:18 Defines pin-muxing selection for GPIO9
    Uint16 GPIO10:2;                    // 21:20 Defines pin-muxing selection for GPIO10
    Uint16 GPIO11:2;                    // 23:22 Defines pin-muxing selection for GPIO11
    Uint16 GPIO12:2;                    // 25:24 Defines pin-muxing selection for GPIO12
    Uint16 GPIO13:2;                    // 27:26 Defines pin-muxing selection for GPIO13
    Uint16 GPIO14:2;                    // 29:28 Defines pin-muxing selection for GPIO14
    Uint16 GPIO15:2;                    // 31:30 Defines pin-muxing selection for GPIO15
};

union GPAGMUX1_REG {
    Uint32  all;
    struct  GPAGMUX1_BITS  bit;
};

struct GPAGMUX2_BITS {                  // bits description
    Uint16 GPIO16:2;                    // 1:0 Defines pin-muxing selection for GPIO16
    Uint16 GPIO17:2;                    // 3:2 Defines pin-muxing selection for GPIO17
    Uint16 GPIO18:2;                    // 5:4 Defines pin-muxing selection for GPIO18
    Uint16 GPIO19:2;                    // 7:6 Defines pin-muxing selection for GPIO19
    Uint16 GPIO20:2;                    // 9:8 Defines pin-muxing selection for GPIO20
    Uint16 GPIO21:2;                    // 11:10 Defines pin-muxing selection for GPIO21
    Uint16 GPIO22:2;                    // 13:12 Defines pin-muxing selection for GPIO22
    Uint16 GPIO23:2;                    // 15:14 Defines pin-muxing selection for GPIO23
    Uint16 GPIO24:2;                    // 17:16 Defines pin-muxing selection for GPIO24
    Uint16 GPIO25:2;                    // 19:18 Defines pin-muxing selection for GPIO25
    Uint16 GPIO26:2;                    // 21:20 Defines pin-muxing selection for GPIO26
    Uint16 GPIO27:2;                    // 23:22 Defines pin-muxing selection for GPIO27
    Uint16 GPIO28:2;                    // 25:24 Defines pin-muxing selection for GPIO28
    Uint16 GPIO29:2;                    // 27:26 Defines pin-muxing selection for GPIO29
    Uint16 GPIO30:2;                    // 29:28 Defines pin-muxing selection for GPIO30
    Uint16 GPIO31:2;                    // 31:30 Defines pin-muxing selection for GPIO31
};

union GPAGMUX2_REG {
    Uint32  all;
    struct  GPAGMUX2_BITS  bit;
};

struct GPACSEL1_BITS {                  // bits description
    Uint16 GPIO0:4;                     // 3:0 GPIO0 Master CPU Select
    Uint16 GPIO1:4;                     // 7:4 GPIO1 Master CPU Select
    Uint16 GPIO2:4;                     // 11:8 GPIO2 Master CPU Select
    Uint16 GPIO3:4;                     // 15:12 GPIO3 Master CPU Select
    Uint16 GPIO4:4;                     // 19:16 GPIO4 Master CPU Select
    Uint16 GPIO5:4;                     // 23:20 GPIO5 Master CPU Select
    Uint16 GPIO6:4;                     // 27:24 GPIO6 Master CPU Select
    Uint16 GPIO7:4;                     // 31:28 GPIO7 Master CPU Select
};

union GPACSEL1_REG {
    Uint32  all;
    struct  GPACSEL1_BITS  bit;
};

struct GPACSEL2_BITS {                  // bits description
    Uint16 GPIO8:4;                     // 3:0 GPIO8 Master CPU Select
    Uint16 GPIO9:4;                     // 7:4 GPIO9 Master CPU Select
    Uint16 GPIO10:4;                    // 11:8 GPIO10 Master CPU Select
    Uint16 GPIO11:4;                    // 15:12 GPIO11 Master CPU Select
    Uint16 GPIO12:4;                    // 19:16 GPIO12 Master CPU Select
    Uint16 GPIO13:4;                    // 23:20 GPIO13 Master CPU Select
    Uint16 GPIO14:4;                    // 27:24 GPIO14 Master CPU Select
    Uint16 GPIO15:4;                    // 31:28 GPIO15 Master CPU Select
};

union GPACSEL2_REG {
    Uint32  all;
    struct  GPACSEL2_BITS  bit;
};

struct GPACSEL3_BITS {                  // bits description
    Uint16 GPIO16:4;                    // 3:0 GPIO16 Master CPU Select
    Uint16 GPIO17:4;                    // 7:4 GPIO17 Master CPU Select
    Uint16 GPIO18:4;                    // 11:8 GPIO18 Master CPU Select
    Uint16 GPIO19:4;                    // 15:12 GPIO19 Master CPU Select
    Uint16 GPIO20:4;                    // 19:16 GPIO20 Master CPU Select
    Uint16 GPIO21:4;                    // 23:20 GPIO21 Master CPU Select
    Uint16 GPIO22:4;                    // 27:24 GPIO22 Master CPU Select
    Uint16 GPIO23:4;                    // 31:28 GPIO23 Master CPU Select
};

union GPACSEL3_REG {
    Uint32  all;
    struct  GPACSEL3_BITS  bit;
};

struct GPACSEL4_BITS {                  // bits description
    Uint16 GPIO24:4;                    // 3:0 GPIO24 Master CPU Select
    Uint16 GPIO25:4;                    // 7:4 GPIO25 Master CPU Select
    Uint16 GPIO26:4;                    // 11:8 GPIO26 Master CPU Select
    Uint16 GPIO27:4;                    // 15:12 GPIO27 Master CPU Select
    Uint16 GPIO28:4;                    // 19:16 GPIO28 Master CPU Select
    Uint16 GPIO29:4;                    // 23:20 GPIO29 Master CPU Select
    Uint16 GPIO30:4;                    // 27:24 GPIO30 Master CPU Select
    Uint16 GPIO31:4;                    // 31:28 GPIO31 Master CPU Select
};

union GPACSEL4_REG {
    Uint32  all;
    struct  GPACSEL4_BITS  bit;
};

struct GPALOCK_BITS {                   // bits description
    Uint16 GPIO0:1;                     // 0 Configuration Lock bit for this pin
    Uint16 GPIO1:1;                     // 1 Configuration Lock bit for this pin
    Uint16 GPIO2:1;                     // 2 Configuration Lock bit for this pin
    Uint16 GPIO3:1;                     // 3 Configuration Lock bit for this pin
    Uint16 GPIO4:1;                     // 4 Configuration Lock bit for this pin
    Uint16 GPIO5:1;                     // 5 Configuration Lock bit for this pin
    Uint16 GPIO6:1;                     // 6 Configuration Lock bit for this pin
    Uint16 GPIO7:1;                     // 7 Configuration Lock bit for this pin
    Uint16 GPIO8:1;                     // 8 Configuration Lock bit for this pin
    Uint16 GPIO9:1;                     // 9 Configuration Lock bit for this pin
    Uint16 GPIO10:1;                    // 10 Configuration Lock bit for this pin
    Uint16 GPIO11:1;                    // 11 Configuration Lock bit for this pin
    Uint16 GPIO12:1;                    // 12 Configuration Lock bit for this pin
    Uint16 GPIO13:1;                    // 13 Configuration Lock bit for this pin
    Uint16 GPIO14:1;                    // 14 Configuration Lock bit for this pin
    Uint16 GPIO15:1;                    // 15 Configuration Lock bit for this pin
    Uint16 GPIO16:1;                    // 16 Configuration Lock bit for this pin
    Uint16 GPIO17:1;                    // 17 Configuration Lock bit for this pin
    Uint16 GPIO18:1;                    // 18 Configuration Lock bit for this pin
    Uint16 GPIO19:1;                    // 19 Configuration Lock bit for this pin
    Uint16 GPIO20:1;                    // 20 Configuration Lock bit for this pin
    Uint16 GPIO21:1;                    // 21 Configuration Lock bit for this pin
    Uint16 GPIO22:1;                    // 22 Configuration Lock bit for this pin
    Uint16 GPIO23:1;                    // 23 Configuration Lock bit for this pin
    Uint16 GPIO24:1;                    // 24 Configuration Lock bit for this pin
    Uint16 GPIO25:1;                    // 25 Configuration Lock bit for this pin
    Uint16 GPIO26:1;                    // 26 Configuration Lock bit for this pin
    Uint16 GPIO27:1;                    // 27 Configuration Lock bit for this pin
    Uint16 GPIO28:1;                    // 28 Configuration Lock bit for this pin
    Uint16 GPIO29:1;                    // 29 Configuration Lock bit for this pin
    Uint16 GPIO30:1;                    // 30 Configuration Lock bit for this pin
    Uint16 GPIO31:1;                    // 31 Configuration Lock bit for this pin
};

union GPALOCK_REG {
    Uint32  all;
    struct  GPALOCK_BITS  bit;
};

struct GPACR_BITS {                     // bits description
    Uint16 GPIO0:1;                     // 0 Configuration lock commit bit for this pin
    Uint16 GPIO1:1;                     // 1 Configuration lock commit bit for this pin
    Uint16 GPIO2:1;                     // 2 Configuration lock commit bit for this pin
    Uint16 GPIO3:1;                     // 3 Configuration lock commit bit for this pin
    Uint16 GPIO4:1;                     // 4 Configuration lock commit bit for this pin
    Uint16 GPIO5:1;                     // 5 Configuration lock commit bit for this pin
    Uint16 GPIO6:1;                     // 6 Configuration lock commit bit for this pin
    Uint16 GPIO7:1;                     // 7 Configuration lock commit bit for this pin
    Uint16 GPIO8:1;                     // 8 Configuration lock commit bit for this pin
    Uint16 GPIO9:1;                     // 9 Configuration lock commit bit for this pin
    Uint16 GPIO10:1;                    // 10 Configuration lock commit bit for this pin
    Uint16 GPIO11:1;                    // 11 Configuration lock commit bit for this pin
    Uint16 GPIO12:1;                    // 12 Configuration lock commit bit for this pin
    Uint16 GPIO13:1;                    // 13 Configuration lock commit bit for this pin
    Uint16 GPIO14:1;                    // 14 Configuration lock commit bit for this pin
    Uint16 GPIO15:1;                    // 15 Configuration lock commit bit for this pin
    Uint16 GPIO16:1;                    // 16 Configuration lock commit bit for this pin
    Uint16 GPIO17:1;                    // 17 Configuration lock commit bit for this pin
    Uint16 GPIO18:1;                    // 18 Configuration lock commit bit for this pin
    Uint16 GPIO19:1;                    // 19 Configuration lock commit bit for this pin
    Uint16 GPIO20:1;                    // 20 Configuration lock commit bit for this pin
    Uint16 GPIO21:1;                    // 21 Configuration lock commit bit for this pin
    Uint16 GPIO22:1;                    // 22 Configuration lock commit bit for this pin
    Uint16 GPIO23:1;                    // 23 Configuration lock commit bit for this pin
    Uint16 GPIO24:1;                    // 24 Configuration lock commit bit for this pin
    Uint16 GPIO25:1;                    // 25 Configuration lock commit bit for this pin
    Uint16 GPIO26:1;                    // 26 Configuration lock commit bit for this pin
    Uint16 GPIO27:1;                    // 27 Configuration lock commit bit for this pin
    Uint16 GPIO28:1;                    // 28 Configuration lock commit bit for this pin
    Uint16 GPIO29:1;                    // 29 Configuration lock commit bit for this pin
    Uint16 GPIO30:1;                    // 30 Configuration lock commit bit for this pin
    Uint16 GPIO31:1;                    // 31 Configuration lock commit bit for this pin
};

union GPACR_REG {
    Uint32  all;
    struct  GPACR_BITS  bit;
};

struct GPBCTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO32 to GPIO39
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO40 to GPIO47
    Uint16 QUALPRD2:8;                  // 23:16 Qualification sampling period for GPIO48 to GPIO55
    Uint16 QUALPRD3:8;                  // 31:24 Qualification sampling period for GPIO56 to GPIO63
};

union GPBCTRL_REG {
    Uint32  all;
    struct  GPBCTRL_BITS  bit;
};

struct GPBQSEL1_BITS {                  // bits description
    Uint16 GPIO32:2;                    // 1:0 Select input qualification type for GPIO32
    Uint16 GPIO33:2;                    // 3:2 Select input qualification type for GPIO33
    Uint16 GPIO34:2;                    // 5:4 Select input qualification type for GPIO34
    Uint16 GPIO35:2;                    // 7:6 Select input qualification type for GPIO35
    Uint16 GPIO36:2;                    // 9:8 Select input qualification type for GPIO36
    Uint16 GPIO37:2;                    // 11:10 Select input qualification type for GPIO37
    Uint16 GPIO38:2;                    // 13:12 Select input qualification type for GPIO38
    Uint16 GPIO39:2;                    // 15:14 Select input qualification type for GPIO39
    Uint16 GPIO40:2;                    // 17:16 Select input qualification type for GPIO40
    Uint16 GPIO41:2;                    // 19:18 Select input qualification type for GPIO41
    Uint16 GPIO42:2;                    // 21:20 Select input qualification type for GPIO42
    Uint16 GPIO43:2;                    // 23:22 Select input qualification type for GPIO43
    Uint16 GPIO44:2;                    // 25:24 Select input qualification type for GPIO44
    Uint16 GPIO45:2;                    // 27:26 Select input qualification type for GPIO45
    Uint16 GPIO46:2;                    // 29:28 Select input qualification type for GPIO46
    Uint16 GPIO47:2;                    // 31:30 Select input qualification type for GPIO47
};

union GPBQSEL1_REG {
    Uint32  all;
    struct  GPBQSEL1_BITS  bit;
};

struct GPBQSEL2_BITS {                  // bits description
    Uint16 GPIO48:2;                    // 1:0 Select input qualification type for GPIO48
    Uint16 GPIO49:2;                    // 3:2 Select input qualification type for GPIO49
    Uint16 GPIO50:2;                    // 5:4 Select input qualification type for GPIO50
    Uint16 GPIO51:2;                    // 7:6 Select input qualification type for GPIO51
    Uint16 GPIO52:2;                    // 9:8 Select input qualification type for GPIO52
    Uint16 GPIO53:2;                    // 11:10 Select input qualification type for GPIO53
    Uint16 GPIO54:2;                    // 13:12 Select input qualification type for GPIO54
    Uint16 GPIO55:2;                    // 15:14 Select input qualification type for GPIO55
    Uint16 GPIO56:2;                    // 17:16 Select input qualification type for GPIO56
    Uint16 GPIO57:2;                    // 19:18 Select input qualification type for GPIO57
    Uint16 GPIO58:2;                    // 21:20 Select input qualification type for GPIO58
    Uint16 GPIO59:2;                    // 23:22 Select input qualification type for GPIO59
    Uint16 GPIO60:2;                    // 25:24 Select input qualification type for GPIO60
    Uint16 GPIO61:2;                    // 27:26 Select input qualification type for GPIO61
    Uint16 GPIO62:2;                    // 29:28 Select input qualification type for GPIO62
    Uint16 GPIO63:2;                    // 31:30 Select input qualification type for GPIO63
};

union GPBQSEL2_REG {
    Uint32  all;
    struct  GPBQSEL2_BITS  bit;
};

struct GPBMUX1_BITS {                   // bits description
    Uint16 GPIO32:2;                    // 1:0 Defines pin-muxing selection for GPIO32
    Uint16 GPIO33:2;                    // 3:2 Defines pin-muxing selection for GPIO33
    Uint16 GPIO34:2;                    // 5:4 Defines pin-muxing selection for GPIO34
    Uint16 GPIO35:2;                    // 7:6 Defines pin-muxing selection for GPIO35
    Uint16 GPIO36:2;                    // 9:8 Defines pin-muxing selection for GPIO36
    Uint16 GPIO37:2;                    // 11:10 Defines pin-muxing selection for GPIO37
    Uint16 GPIO38:2;                    // 13:12 Defines pin-muxing selection for GPIO38
    Uint16 GPIO39:2;                    // 15:14 Defines pin-muxing selection for GPIO39
    Uint16 GPIO40:2;                    // 17:16 Defines pin-muxing selection for GPIO40
    Uint16 GPIO41:2;                    // 19:18 Defines pin-muxing selection for GPIO41
    Uint16 GPIO42:2;                    // 21:20 Defines pin-muxing selection for GPIO42
    Uint16 GPIO43:2;                    // 23:22 Defines pin-muxing selection for GPIO43
    Uint16 GPIO44:2;                    // 25:24 Defines pin-muxing selection for GPIO44
    Uint16 GPIO45:2;                    // 27:26 Defines pin-muxing selection for GPIO45
    Uint16 GPIO46:2;                    // 29:28 Defines pin-muxing selection for GPIO46
    Uint16 GPIO47:2;                    // 31:30 Defines pin-muxing selection for GPIO47
};

union GPBMUX1_REG {
    Uint32  all;
    struct  GPBMUX1_BITS  bit;
};

struct GPBMUX2_BITS {                   // bits description
    Uint16 GPIO48:2;                    // 1:0 Defines pin-muxing selection for GPIO48
    Uint16 GPIO49:2;                    // 3:2 Defines pin-muxing selection for GPIO49
    Uint16 GPIO50:2;                    // 5:4 Defines pin-muxing selection for GPIO50
    Uint16 GPIO51:2;                    // 7:6 Defines pin-muxing selection for GPIO51
    Uint16 GPIO52:2;                    // 9:8 Defines pin-muxing selection for GPIO52
    Uint16 GPIO53:2;                    // 11:10 Defines pin-muxing selection for GPIO53
    Uint16 GPIO54:2;                    // 13:12 Defines pin-muxing selection for GPIO54
    Uint16 GPIO55:2;                    // 15:14 Defines pin-muxing selection for GPIO55
    Uint16 GPIO56:2;                    // 17:16 Defines pin-muxing selection for GPIO56
    Uint16 GPIO57:2;                    // 19:18 Defines pin-muxing selection for GPIO57
    Uint16 GPIO58:2;                    // 21:20 Defines pin-muxing selection for GPIO58
    Uint16 GPIO59:2;                    // 23:22 Defines pin-muxing selection for GPIO59
    Uint16 GPIO60:2;                    // 25:24 Defines pin-muxing selection for GPIO60
    Uint16 GPIO61:2;                    // 27:26 Defines pin-muxing selection for GPIO61
    Uint16 GPIO62:2;                    // 29:28 Defines pin-muxing selection for GPIO62
    Uint16 GPIO63:2;                    // 31:30 Defines pin-muxing selection for GPIO63
};

union GPBMUX2_REG {
    Uint32  all;
    struct  GPBMUX2_BITS  bit;
};

struct GPBDIR_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO33:1;                    // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO34:1;                    // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO35:1;                    // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO36:1;                    // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO37:1;                    // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO38:1;                    // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO39:1;                    // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO40:1;                    // 8 Defines direction for this pin in GPIO mode
    Uint16 GPIO41:1;                    // 9 Defines direction for this pin in GPIO mode
    Uint16 GPIO42:1;                    // 10 Defines direction for this pin in GPIO mode
    Uint16 GPIO43:1;                    // 11 Defines direction for this pin in GPIO mode
    Uint16 GPIO44:1;                    // 12 Defines direction for this pin in GPIO mode
    Uint16 GPIO45:1;                    // 13 Defines direction for this pin in GPIO mode
    Uint16 GPIO46:1;                    // 14 Defines direction for this pin in GPIO mode
    Uint16 GPIO47:1;                    // 15 Defines direction for this pin in GPIO mode
    Uint16 GPIO48:1;                    // 16 Defines direction for this pin in GPIO mode
    Uint16 GPIO49:1;                    // 17 Defines direction for this pin in GPIO mode
    Uint16 GPIO50:1;                    // 18 Defines direction for this pin in GPIO mode
    Uint16 GPIO51:1;                    // 19 Defines direction for this pin in GPIO mode
    Uint16 GPIO52:1;                    // 20 Defines direction for this pin in GPIO mode
    Uint16 GPIO53:1;                    // 21 Defines direction for this pin in GPIO mode
    Uint16 GPIO54:1;                    // 22 Defines direction for this pin in GPIO mode
    Uint16 GPIO55:1;                    // 23 Defines direction for this pin in GPIO mode
    Uint16 GPIO56:1;                    // 24 Defines direction for this pin in GPIO mode
    Uint16 GPIO57:1;                    // 25 Defines direction for this pin in GPIO mode
    Uint16 GPIO58:1;                    // 26 Defines direction for this pin in GPIO mode
    Uint16 GPIO59:1;                    // 27 Defines direction for this pin in GPIO mode
    Uint16 GPIO60:1;                    // 28 Defines direction for this pin in GPIO mode
    Uint16 GPIO61:1;                    // 29 Defines direction for this pin in GPIO mode
    Uint16 GPIO62:1;                    // 30 Defines direction for this pin in GPIO mode
    Uint16 GPIO63:1;                    // 31 Defines direction for this pin in GPIO mode
};

union GPBDIR_REG {
    Uint32  all;
    struct  GPBDIR_BITS  bit;
};

struct GPBPUD_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Pull-Up Disable control for this pin
    Uint16 GPIO33:1;                    // 1 Pull-Up Disable control for this pin
    Uint16 GPIO34:1;                    // 2 Pull-Up Disable control for this pin
    Uint16 GPIO35:1;                    // 3 Pull-Up Disable control for this pin
    Uint16 GPIO36:1;                    // 4 Pull-Up Disable control for this pin
    Uint16 GPIO37:1;                    // 5 Pull-Up Disable control for this pin
    Uint16 GPIO38:1;                    // 6 Pull-Up Disable control for this pin
    Uint16 GPIO39:1;                    // 7 Pull-Up Disable control for this pin
    Uint16 GPIO40:1;                    // 8 Pull-Up Disable control for this pin
    Uint16 GPIO41:1;                    // 9 Pull-Up Disable control for this pin
    Uint16 GPIO42:1;                    // 10 Pull-Up Disable control for this pin
    Uint16 GPIO43:1;                    // 11 Pull-Up Disable control for this pin
    Uint16 GPIO44:1;                    // 12 Pull-Up Disable control for this pin
    Uint16 GPIO45:1;                    // 13 Pull-Up Disable control for this pin
    Uint16 GPIO46:1;                    // 14 Pull-Up Disable control for this pin
    Uint16 GPIO47:1;                    // 15 Pull-Up Disable control for this pin
    Uint16 GPIO48:1;                    // 16 Pull-Up Disable control for this pin
    Uint16 GPIO49:1;                    // 17 Pull-Up Disable control for this pin
    Uint16 GPIO50:1;                    // 18 Pull-Up Disable control for this pin
    Uint16 GPIO51:1;                    // 19 Pull-Up Disable control for this pin
    Uint16 GPIO52:1;                    // 20 Pull-Up Disable control for this pin
    Uint16 GPIO53:1;                    // 21 Pull-Up Disable control for this pin
    Uint16 GPIO54:1;                    // 22 Pull-Up Disable control for this pin
    Uint16 GPIO55:1;                    // 23 Pull-Up Disable control for this pin
    Uint16 GPIO56:1;                    // 24 Pull-Up Disable control for this pin
    Uint16 GPIO57:1;                    // 25 Pull-Up Disable control for this pin
    Uint16 GPIO58:1;                    // 26 Pull-Up Disable control for this pin
    Uint16 GPIO59:1;                    // 27 Pull-Up Disable control for this pin
    Uint16 GPIO60:1;                    // 28 Pull-Up Disable control for this pin
    Uint16 GPIO61:1;                    // 29 Pull-Up Disable control for this pin
    Uint16 GPIO62:1;                    // 30 Pull-Up Disable control for this pin
    Uint16 GPIO63:1;                    // 31 Pull-Up Disable control for this pin
};

union GPBPUD_REG {
    Uint32  all;
    struct  GPBPUD_BITS  bit;
};

struct GPBINV_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Input inversion control for this pin
    Uint16 GPIO33:1;                    // 1 Input inversion control for this pin
    Uint16 GPIO34:1;                    // 2 Input inversion control for this pin
    Uint16 GPIO35:1;                    // 3 Input inversion control for this pin
    Uint16 GPIO36:1;                    // 4 Input inversion control for this pin
    Uint16 GPIO37:1;                    // 5 Input inversion control for this pin
    Uint16 GPIO38:1;                    // 6 Input inversion control for this pin
    Uint16 GPIO39:1;                    // 7 Input inversion control for this pin
    Uint16 GPIO40:1;                    // 8 Input inversion control for this pin
    Uint16 GPIO41:1;                    // 9 Input inversion control for this pin
    Uint16 GPIO42:1;                    // 10 Input inversion control for this pin
    Uint16 GPIO43:1;                    // 11 Input inversion control for this pin
    Uint16 GPIO44:1;                    // 12 Input inversion control for this pin
    Uint16 GPIO45:1;                    // 13 Input inversion control for this pin
    Uint16 GPIO46:1;                    // 14 Input inversion control for this pin
    Uint16 GPIO47:1;                    // 15 Input inversion control for this pin
    Uint16 GPIO48:1;                    // 16 Input inversion control for this pin
    Uint16 GPIO49:1;                    // 17 Input inversion control for this pin
    Uint16 GPIO50:1;                    // 18 Input inversion control for this pin
    Uint16 GPIO51:1;                    // 19 Input inversion control for this pin
    Uint16 GPIO52:1;                    // 20 Input inversion control for this pin
    Uint16 GPIO53:1;                    // 21 Input inversion control for this pin
    Uint16 GPIO54:1;                    // 22 Input inversion control for this pin
    Uint16 GPIO55:1;                    // 23 Input inversion control for this pin
    Uint16 GPIO56:1;                    // 24 Input inversion control for this pin
    Uint16 GPIO57:1;                    // 25 Input inversion control for this pin
    Uint16 GPIO58:1;                    // 26 Input inversion control for this pin
    Uint16 GPIO59:1;                    // 27 Input inversion control for this pin
    Uint16 GPIO60:1;                    // 28 Input inversion control for this pin
    Uint16 GPIO61:1;                    // 29 Input inversion control for this pin
    Uint16 GPIO62:1;                    // 30 Input inversion control for this pin
    Uint16 GPIO63:1;                    // 31 Input inversion control for this pin
};

union GPBINV_REG {
    Uint32  all;
    struct  GPBINV_BITS  bit;
};

struct GPBODR_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO33:1;                    // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO34:1;                    // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO35:1;                    // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO36:1;                    // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO37:1;                    // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO38:1;                    // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO39:1;                    // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO40:1;                    // 8 Outpout Open-Drain control for this pin
    Uint16 GPIO41:1;                    // 9 Outpout Open-Drain control for this pin
    Uint16 GPIO42:1;                    // 10 Outpout Open-Drain control for this pin
    Uint16 GPIO43:1;                    // 11 Outpout Open-Drain control for this pin
    Uint16 GPIO44:1;                    // 12 Outpout Open-Drain control for this pin
    Uint16 GPIO45:1;                    // 13 Outpout Open-Drain control for this pin
    Uint16 GPIO46:1;                    // 14 Outpout Open-Drain control for this pin
    Uint16 GPIO47:1;                    // 15 Outpout Open-Drain control for this pin
    Uint16 GPIO48:1;                    // 16 Outpout Open-Drain control for this pin
    Uint16 GPIO49:1;                    // 17 Outpout Open-Drain control for this pin
    Uint16 GPIO50:1;                    // 18 Outpout Open-Drain control for this pin
    Uint16 GPIO51:1;                    // 19 Outpout Open-Drain control for this pin
    Uint16 GPIO52:1;                    // 20 Outpout Open-Drain control for this pin
    Uint16 GPIO53:1;                    // 21 Outpout Open-Drain control for this pin
    Uint16 GPIO54:1;                    // 22 Outpout Open-Drain control for this pin
    Uint16 GPIO55:1;                    // 23 Outpout Open-Drain control for this pin
    Uint16 GPIO56:1;                    // 24 Outpout Open-Drain control for this pin
    Uint16 GPIO57:1;                    // 25 Outpout Open-Drain control for this pin
    Uint16 GPIO58:1;                    // 26 Outpout Open-Drain control for this pin
    Uint16 GPIO59:1;                    // 27 Outpout Open-Drain control for this pin
    Uint16 GPIO60:1;                    // 28 Outpout Open-Drain control for this pin
    Uint16 GPIO61:1;                    // 29 Outpout Open-Drain control for this pin
    Uint16 GPIO62:1;                    // 30 Outpout Open-Drain control for this pin
    Uint16 GPIO63:1;                    // 31 Outpout Open-Drain control for this pin
};

union GPBODR_REG {
    Uint32  all;
    struct  GPBODR_BITS  bit;
};

struct GPBAMSEL_BITS {                  // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 rsvd4:1;                     // 3 Reserved
    Uint16 rsvd5:1;                     // 4 Reserved
    Uint16 rsvd6:1;                     // 5 Reserved
    Uint16 rsvd7:1;                     // 6 Reserved
    Uint16 rsvd8:1;                     // 7 Reserved
    Uint16 rsvd9:1;                     // 8 Reserved
    Uint16 rsvd10:1;                    // 9 Reserved
    Uint16 GPIO42:1;                    // 10 Analog Mode select for this pin
    Uint16 GPIO43:1;                    // 11 Analog Mode select for this pin
    Uint16 rsvd11:1;                    // 12 Reserved
    Uint16 rsvd12:1;                    // 13 Reserved
    Uint16 rsvd13:1;                    // 14 Reserved
    Uint16 rsvd14:1;                    // 15 Reserved
    Uint16 rsvd15:1;                    // 16 Reserved
    Uint16 rsvd16:1;                    // 17 Reserved
    Uint16 rsvd17:1;                    // 18 Reserved
    Uint16 rsvd18:1;                    // 19 Reserved
    Uint16 rsvd19:1;                    // 20 Reserved
    Uint16 rsvd20:1;                    // 21 Reserved
    Uint16 rsvd21:1;                    // 22 Reserved
    Uint16 rsvd22:1;                    // 23 Reserved
    Uint16 rsvd23:1;                    // 24 Reserved
    Uint16 rsvd24:1;                    // 25 Reserved
    Uint16 rsvd25:1;                    // 26 Reserved
    Uint16 rsvd26:1;                    // 27 Reserved
    Uint16 rsvd27:1;                    // 28 Reserved
    Uint16 rsvd28:1;                    // 29 Reserved
    Uint16 rsvd29:1;                    // 30 Reserved
    Uint16 rsvd30:1;                    // 31 Reserved
};

union GPBAMSEL_REG {
    Uint32  all;
    struct  GPBAMSEL_BITS  bit;
};

struct GPBGMUX1_BITS {                  // bits description
    Uint16 GPIO32:2;                    // 1:0 Defines pin-muxing selection for GPIO32
    Uint16 GPIO33:2;                    // 3:2 Defines pin-muxing selection for GPIO33
    Uint16 GPIO34:2;                    // 5:4 Defines pin-muxing selection for GPIO34
    Uint16 GPIO35:2;                    // 7:6 Defines pin-muxing selection for GPIO35
    Uint16 GPIO36:2;                    // 9:8 Defines pin-muxing selection for GPIO36
    Uint16 GPIO37:2;                    // 11:10 Defines pin-muxing selection for GPIO37
    Uint16 GPIO38:2;                    // 13:12 Defines pin-muxing selection for GPIO38
    Uint16 GPIO39:2;                    // 15:14 Defines pin-muxing selection for GPIO39
    Uint16 GPIO40:2;                    // 17:16 Defines pin-muxing selection for GPIO40
    Uint16 GPIO41:2;                    // 19:18 Defines pin-muxing selection for GPIO41
    Uint16 GPIO42:2;                    // 21:20 Defines pin-muxing selection for GPIO42
    Uint16 GPIO43:2;                    // 23:22 Defines pin-muxing selection for GPIO43
    Uint16 GPIO44:2;                    // 25:24 Defines pin-muxing selection for GPIO44
    Uint16 GPIO45:2;                    // 27:26 Defines pin-muxing selection for GPIO45
    Uint16 GPIO46:2;                    // 29:28 Defines pin-muxing selection for GPIO46
    Uint16 GPIO47:2;                    // 31:30 Defines pin-muxing selection for GPIO47
};

union GPBGMUX1_REG {
    Uint32  all;
    struct  GPBGMUX1_BITS  bit;
};

struct GPBGMUX2_BITS {                  // bits description
    Uint16 GPIO48:2;                    // 1:0 Defines pin-muxing selection for GPIO48
    Uint16 GPIO49:2;                    // 3:2 Defines pin-muxing selection for GPIO49
    Uint16 GPIO50:2;                    // 5:4 Defines pin-muxing selection for GPIO50
    Uint16 GPIO51:2;                    // 7:6 Defines pin-muxing selection for GPIO51
    Uint16 GPIO52:2;                    // 9:8 Defines pin-muxing selection for GPIO52
    Uint16 GPIO53:2;                    // 11:10 Defines pin-muxing selection for GPIO53
    Uint16 GPIO54:2;                    // 13:12 Defines pin-muxing selection for GPIO54
    Uint16 GPIO55:2;                    // 15:14 Defines pin-muxing selection for GPIO55
    Uint16 GPIO56:2;                    // 17:16 Defines pin-muxing selection for GPIO56
    Uint16 GPIO57:2;                    // 19:18 Defines pin-muxing selection for GPIO57
    Uint16 GPIO58:2;                    // 21:20 Defines pin-muxing selection for GPIO58
    Uint16 GPIO59:2;                    // 23:22 Defines pin-muxing selection for GPIO59
    Uint16 GPIO60:2;                    // 25:24 Defines pin-muxing selection for GPIO60
    Uint16 GPIO61:2;                    // 27:26 Defines pin-muxing selection for GPIO61
    Uint16 GPIO62:2;                    // 29:28 Defines pin-muxing selection for GPIO62
    Uint16 GPIO63:2;                    // 31:30 Defines pin-muxing selection for GPIO63
};

union GPBGMUX2_REG {
    Uint32  all;
    struct  GPBGMUX2_BITS  bit;
};

struct GPBCSEL1_BITS {                  // bits description
    Uint16 GPIO32:4;                    // 3:0 GPIO32 Master CPU Select
    Uint16 GPIO33:4;                    // 7:4 GPIO33 Master CPU Select
    Uint16 GPIO34:4;                    // 11:8 GPIO34 Master CPU Select
    Uint16 GPIO35:4;                    // 15:12 GPIO35 Master CPU Select
    Uint16 GPIO36:4;                    // 19:16 GPIO36 Master CPU Select
    Uint16 GPIO37:4;                    // 23:20 GPIO37 Master CPU Select
    Uint16 GPIO38:4;                    // 27:24 GPIO38 Master CPU Select
    Uint16 GPIO39:4;                    // 31:28 GPIO39 Master CPU Select
};

union GPBCSEL1_REG {
    Uint32  all;
    struct  GPBCSEL1_BITS  bit;
};

struct GPBCSEL2_BITS {                  // bits description
    Uint16 GPIO40:4;                    // 3:0 GPIO40 Master CPU Select
    Uint16 GPIO41:4;                    // 7:4 GPIO41 Master CPU Select
    Uint16 GPIO42:4;                    // 11:8 GPIO42 Master CPU Select
    Uint16 GPIO43:4;                    // 15:12 GPIO43 Master CPU Select
    Uint16 GPIO44:4;                    // 19:16 GPIO44 Master CPU Select
    Uint16 GPIO45:4;                    // 23:20 GPIO45 Master CPU Select
    Uint16 GPIO46:4;                    // 27:24 GPIO46 Master CPU Select
    Uint16 GPIO47:4;                    // 31:28 GPIO47 Master CPU Select
};

union GPBCSEL2_REG {
    Uint32  all;
    struct  GPBCSEL2_BITS  bit;
};

struct GPBCSEL3_BITS {                  // bits description
    Uint16 GPIO48:4;                    // 3:0 GPIO48 Master CPU Select
    Uint16 GPIO49:4;                    // 7:4 GPIO49 Master CPU Select
    Uint16 GPIO50:4;                    // 11:8 GPIO50 Master CPU Select
    Uint16 GPIO51:4;                    // 15:12 GPIO51 Master CPU Select
    Uint16 GPIO52:4;                    // 19:16 GPIO52 Master CPU Select
    Uint16 GPIO53:4;                    // 23:20 GPIO53 Master CPU Select
    Uint16 GPIO54:4;                    // 27:24 GPIO54 Master CPU Select
    Uint16 GPIO55:4;                    // 31:28 GPIO55 Master CPU Select
};

union GPBCSEL3_REG {
    Uint32  all;
    struct  GPBCSEL3_BITS  bit;
};

struct GPBCSEL4_BITS {                  // bits description
    Uint16 GPIO56:4;                    // 3:0 GPIO56 Master CPU Select
    Uint16 GPIO57:4;                    // 7:4 GPIO57 Master CPU Select
    Uint16 GPIO58:4;                    // 11:8 GPIO58 Master CPU Select
    Uint16 GPIO59:4;                    // 15:12 GPIO59 Master CPU Select
    Uint16 GPIO60:4;                    // 19:16 GPIO60 Master CPU Select
    Uint16 GPIO61:4;                    // 23:20 GPIO61 Master CPU Select
    Uint16 GPIO62:4;                    // 27:24 GPIO62 Master CPU Select
    Uint16 GPIO63:4;                    // 31:28 GPIO63 Master CPU Select
};

union GPBCSEL4_REG {
    Uint32  all;
    struct  GPBCSEL4_BITS  bit;
};

struct GPBLOCK_BITS {                   // bits description
    Uint16 GPIO32:1;                    // 0 Configuration Lock bit for this pin
    Uint16 GPIO33:1;                    // 1 Configuration Lock bit for this pin
    Uint16 GPIO34:1;                    // 2 Configuration Lock bit for this pin
    Uint16 GPIO35:1;                    // 3 Configuration Lock bit for this pin
    Uint16 GPIO36:1;                    // 4 Configuration Lock bit for this pin
    Uint16 GPIO37:1;                    // 5 Configuration Lock bit for this pin
    Uint16 GPIO38:1;                    // 6 Configuration Lock bit for this pin
    Uint16 GPIO39:1;                    // 7 Configuration Lock bit for this pin
    Uint16 GPIO40:1;                    // 8 Configuration Lock bit for this pin
    Uint16 GPIO41:1;                    // 9 Configuration Lock bit for this pin
    Uint16 GPIO42:1;                    // 10 Configuration Lock bit for this pin
    Uint16 GPIO43:1;                    // 11 Configuration Lock bit for this pin
    Uint16 GPIO44:1;                    // 12 Configuration Lock bit for this pin
    Uint16 GPIO45:1;                    // 13 Configuration Lock bit for this pin
    Uint16 GPIO46:1;                    // 14 Configuration Lock bit for this pin
    Uint16 GPIO47:1;                    // 15 Configuration Lock bit for this pin
    Uint16 GPIO48:1;                    // 16 Configuration Lock bit for this pin
    Uint16 GPIO49:1;                    // 17 Configuration Lock bit for this pin
    Uint16 GPIO50:1;                    // 18 Configuration Lock bit for this pin
    Uint16 GPIO51:1;                    // 19 Configuration Lock bit for this pin
    Uint16 GPIO52:1;                    // 20 Configuration Lock bit for this pin
    Uint16 GPIO53:1;                    // 21 Configuration Lock bit for this pin
    Uint16 GPIO54:1;                    // 22 Configuration Lock bit for this pin
    Uint16 GPIO55:1;                    // 23 Configuration Lock bit for this pin
    Uint16 GPIO56:1;                    // 24 Configuration Lock bit for this pin
    Uint16 GPIO57:1;                    // 25 Configuration Lock bit for this pin
    Uint16 GPIO58:1;                    // 26 Configuration Lock bit for this pin
    Uint16 GPIO59:1;                    // 27 Configuration Lock bit for this pin
    Uint16 GPIO60:1;                    // 28 Configuration Lock bit for this pin
    Uint16 GPIO61:1;                    // 29 Configuration Lock bit for this pin
    Uint16 GPIO62:1;                    // 30 Configuration Lock bit for this pin
    Uint16 GPIO63:1;                    // 31 Configuration Lock bit for this pin
};

union GPBLOCK_REG {
    Uint32  all;
    struct  GPBLOCK_BITS  bit;
};

struct GPBCR_BITS {                     // bits description
    Uint16 GPIO32:1;                    // 0 Configuration lock commit bit for this pin
    Uint16 GPIO33:1;                    // 1 Configuration lock commit bit for this pin
    Uint16 GPIO34:1;                    // 2 Configuration lock commit bit for this pin
    Uint16 GPIO35:1;                    // 3 Configuration lock commit bit for this pin
    Uint16 GPIO36:1;                    // 4 Configuration lock commit bit for this pin
    Uint16 GPIO37:1;                    // 5 Configuration lock commit bit for this pin
    Uint16 GPIO38:1;                    // 6 Configuration lock commit bit for this pin
    Uint16 GPIO39:1;                    // 7 Configuration lock commit bit for this pin
    Uint16 GPIO40:1;                    // 8 Configuration lock commit bit for this pin
    Uint16 GPIO41:1;                    // 9 Configuration lock commit bit for this pin
    Uint16 GPIO42:1;                    // 10 Configuration lock commit bit for this pin
    Uint16 GPIO43:1;                    // 11 Configuration lock commit bit for this pin
    Uint16 GPIO44:1;                    // 12 Configuration lock commit bit for this pin
    Uint16 GPIO45:1;                    // 13 Configuration lock commit bit for this pin
    Uint16 GPIO46:1;                    // 14 Configuration lock commit bit for this pin
    Uint16 GPIO47:1;                    // 15 Configuration lock commit bit for this pin
    Uint16 GPIO48:1;                    // 16 Configuration lock commit bit for this pin
    Uint16 GPIO49:1;                    // 17 Configuration lock commit bit for this pin
    Uint16 GPIO50:1;                    // 18 Configuration lock commit bit for this pin
    Uint16 GPIO51:1;                    // 19 Configuration lock commit bit for this pin
    Uint16 GPIO52:1;                    // 20 Configuration lock commit bit for this pin
    Uint16 GPIO53:1;                    // 21 Configuration lock commit bit for this pin
    Uint16 GPIO54:1;                    // 22 Configuration lock commit bit for this pin
    Uint16 GPIO55:1;                    // 23 Configuration lock commit bit for this pin
    Uint16 GPIO56:1;                    // 24 Configuration lock commit bit for this pin
    Uint16 GPIO57:1;                    // 25 Configuration lock commit bit for this pin
    Uint16 GPIO58:1;                    // 26 Configuration lock commit bit for this pin
    Uint16 GPIO59:1;                    // 27 Configuration lock commit bit for this pin
    Uint16 GPIO60:1;                    // 28 Configuration lock commit bit for this pin
    Uint16 GPIO61:1;                    // 29 Configuration lock commit bit for this pin
    Uint16 GPIO62:1;                    // 30 Configuration lock commit bit for this pin
    Uint16 GPIO63:1;                    // 31 Configuration lock commit bit for this pin
};

union GPBCR_REG {
    Uint32  all;
    struct  GPBCR_BITS  bit;
};

struct GPCCTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO64 to GPIO71
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO72 to GPIO79
    Uint16 QUALPRD2:8;                  // 23:16 Qualification sampling period for GPIO80 to GPIO87
    Uint16 QUALPRD3:8;                  // 31:24 Qualification sampling period for GPIO88 to GPIO95
};

union GPCCTRL_REG {
    Uint32  all;
    struct  GPCCTRL_BITS  bit;
};

struct GPCQSEL1_BITS {                  // bits description
    Uint16 GPIO64:2;                    // 1:0 Select input qualification type for GPIO64
    Uint16 GPIO65:2;                    // 3:2 Select input qualification type for GPIO65
    Uint16 GPIO66:2;                    // 5:4 Select input qualification type for GPIO66
    Uint16 GPIO67:2;                    // 7:6 Select input qualification type for GPIO67
    Uint16 GPIO68:2;                    // 9:8 Select input qualification type for GPIO68
    Uint16 GPIO69:2;                    // 11:10 Select input qualification type for GPIO69
    Uint16 GPIO70:2;                    // 13:12 Select input qualification type for GPIO70
    Uint16 GPIO71:2;                    // 15:14 Select input qualification type for GPIO71
    Uint16 GPIO72:2;                    // 17:16 Select input qualification type for GPIO72
    Uint16 GPIO73:2;                    // 19:18 Select input qualification type for GPIO73
    Uint16 GPIO74:2;                    // 21:20 Select input qualification type for GPIO74
    Uint16 GPIO75:2;                    // 23:22 Select input qualification type for GPIO75
    Uint16 GPIO76:2;                    // 25:24 Select input qualification type for GPIO76
    Uint16 GPIO77:2;                    // 27:26 Select input qualification type for GPIO77
    Uint16 GPIO78:2;                    // 29:28 Select input qualification type for GPIO78
    Uint16 GPIO79:2;                    // 31:30 Select input qualification type for GPIO79
};

union GPCQSEL1_REG {
    Uint32  all;
    struct  GPCQSEL1_BITS  bit;
};

struct GPCQSEL2_BITS {                  // bits description
    Uint16 GPIO80:2;                    // 1:0 Select input qualification type for GPIO80
    Uint16 GPIO81:2;                    // 3:2 Select input qualification type for GPIO81
    Uint16 GPIO82:2;                    // 5:4 Select input qualification type for GPIO82
    Uint16 GPIO83:2;                    // 7:6 Select input qualification type for GPIO83
    Uint16 GPIO84:2;                    // 9:8 Select input qualification type for GPIO84
    Uint16 GPIO85:2;                    // 11:10 Select input qualification type for GPIO85
    Uint16 GPIO86:2;                    // 13:12 Select input qualification type for GPIO86
    Uint16 GPIO87:2;                    // 15:14 Select input qualification type for GPIO87
    Uint16 GPIO88:2;                    // 17:16 Select input qualification type for GPIO88
    Uint16 GPIO89:2;                    // 19:18 Select input qualification type for GPIO89
    Uint16 GPIO90:2;                    // 21:20 Select input qualification type for GPIO90
    Uint16 GPIO91:2;                    // 23:22 Select input qualification type for GPIO91
    Uint16 GPIO92:2;                    // 25:24 Select input qualification type for GPIO92
    Uint16 GPIO93:2;                    // 27:26 Select input qualification type for GPIO93
    Uint16 GPIO94:2;                    // 29:28 Select input qualification type for GPIO94
    Uint16 GPIO95:2;                    // 31:30 Select input qualification type for GPIO95
};

union GPCQSEL2_REG {
    Uint32  all;
    struct  GPCQSEL2_BITS  bit;
};

struct GPCMUX1_BITS {                   // bits description
    Uint16 GPIO64:2;                    // 1:0 Defines pin-muxing selection for GPIO64
    Uint16 GPIO65:2;                    // 3:2 Defines pin-muxing selection for GPIO65
    Uint16 GPIO66:2;                    // 5:4 Defines pin-muxing selection for GPIO66
    Uint16 GPIO67:2;                    // 7:6 Defines pin-muxing selection for GPIO67
    Uint16 GPIO68:2;                    // 9:8 Defines pin-muxing selection for GPIO68
    Uint16 GPIO69:2;                    // 11:10 Defines pin-muxing selection for GPIO69
    Uint16 GPIO70:2;                    // 13:12 Defines pin-muxing selection for GPIO70
    Uint16 GPIO71:2;                    // 15:14 Defines pin-muxing selection for GPIO71
    Uint16 GPIO72:2;                    // 17:16 Defines pin-muxing selection for GPIO72
    Uint16 GPIO73:2;                    // 19:18 Defines pin-muxing selection for GPIO73
    Uint16 GPIO74:2;                    // 21:20 Defines pin-muxing selection for GPIO74
    Uint16 GPIO75:2;                    // 23:22 Defines pin-muxing selection for GPIO75
    Uint16 GPIO76:2;                    // 25:24 Defines pin-muxing selection for GPIO76
    Uint16 GPIO77:2;                    // 27:26 Defines pin-muxing selection for GPIO77
    Uint16 GPIO78:2;                    // 29:28 Defines pin-muxing selection for GPIO78
    Uint16 GPIO79:2;                    // 31:30 Defines pin-muxing selection for GPIO79
};

union GPCMUX1_REG {
    Uint32  all;
    struct  GPCMUX1_BITS  bit;
};

struct GPCMUX2_BITS {                   // bits description
    Uint16 GPIO80:2;                    // 1:0 Defines pin-muxing selection for GPIO80
    Uint16 GPIO81:2;                    // 3:2 Defines pin-muxing selection for GPIO81
    Uint16 GPIO82:2;                    // 5:4 Defines pin-muxing selection for GPIO82
    Uint16 GPIO83:2;                    // 7:6 Defines pin-muxing selection for GPIO83
    Uint16 GPIO84:2;                    // 9:8 Defines pin-muxing selection for GPIO84
    Uint16 GPIO85:2;                    // 11:10 Defines pin-muxing selection for GPIO85
    Uint16 GPIO86:2;                    // 13:12 Defines pin-muxing selection for GPIO86
    Uint16 GPIO87:2;                    // 15:14 Defines pin-muxing selection for GPIO87
    Uint16 GPIO88:2;                    // 17:16 Defines pin-muxing selection for GPIO88
    Uint16 GPIO89:2;                    // 19:18 Defines pin-muxing selection for GPIO89
    Uint16 GPIO90:2;                    // 21:20 Defines pin-muxing selection for GPIO90
    Uint16 GPIO91:2;                    // 23:22 Defines pin-muxing selection for GPIO91
    Uint16 GPIO92:2;                    // 25:24 Defines pin-muxing selection for GPIO92
    Uint16 GPIO93:2;                    // 27:26 Defines pin-muxing selection for GPIO93
    Uint16 GPIO94:2;                    // 29:28 Defines pin-muxing selection for GPIO94
    Uint16 GPIO95:2;                    // 31:30 Defines pin-muxing selection for GPIO95
};

union GPCMUX2_REG {
    Uint32  all;
    struct  GPCMUX2_BITS  bit;
};

struct GPCDIR_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO65:1;                    // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO66:1;                    // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO67:1;                    // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO68:1;                    // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO69:1;                    // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO70:1;                    // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO71:1;                    // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO72:1;                    // 8 Defines direction for this pin in GPIO mode
    Uint16 GPIO73:1;                    // 9 Defines direction for this pin in GPIO mode
    Uint16 GPIO74:1;                    // 10 Defines direction for this pin in GPIO mode
    Uint16 GPIO75:1;                    // 11 Defines direction for this pin in GPIO mode
    Uint16 GPIO76:1;                    // 12 Defines direction for this pin in GPIO mode
    Uint16 GPIO77:1;                    // 13 Defines direction for this pin in GPIO mode
    Uint16 GPIO78:1;                    // 14 Defines direction for this pin in GPIO mode
    Uint16 GPIO79:1;                    // 15 Defines direction for this pin in GPIO mode
    Uint16 GPIO80:1;                    // 16 Defines direction for this pin in GPIO mode
    Uint16 GPIO81:1;                    // 17 Defines direction for this pin in GPIO mode
    Uint16 GPIO82:1;                    // 18 Defines direction for this pin in GPIO mode
    Uint16 GPIO83:1;                    // 19 Defines direction for this pin in GPIO mode
    Uint16 GPIO84:1;                    // 20 Defines direction for this pin in GPIO mode
    Uint16 GPIO85:1;                    // 21 Defines direction for this pin in GPIO mode
    Uint16 GPIO86:1;                    // 22 Defines direction for this pin in GPIO mode
    Uint16 GPIO87:1;                    // 23 Defines direction for this pin in GPIO mode
    Uint16 GPIO88:1;                    // 24 Defines direction for this pin in GPIO mode
    Uint16 GPIO89:1;                    // 25 Defines direction for this pin in GPIO mode
    Uint16 GPIO90:1;                    // 26 Defines direction for this pin in GPIO mode
    Uint16 GPIO91:1;                    // 27 Defines direction for this pin in GPIO mode
    Uint16 GPIO92:1;                    // 28 Defines direction for this pin in GPIO mode
    Uint16 GPIO93:1;                    // 29 Defines direction for this pin in GPIO mode
    Uint16 GPIO94:1;                    // 30 Defines direction for this pin in GPIO mode
    Uint16 GPIO95:1;                    // 31 Defines direction for this pin in GPIO mode
};

union GPCDIR_REG {
    Uint32  all;
    struct  GPCDIR_BITS  bit;
};

struct GPCPUD_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Pull-Up Disable control for this pin
    Uint16 GPIO65:1;                    // 1 Pull-Up Disable control for this pin
    Uint16 GPIO66:1;                    // 2 Pull-Up Disable control for this pin
    Uint16 GPIO67:1;                    // 3 Pull-Up Disable control for this pin
    Uint16 GPIO68:1;                    // 4 Pull-Up Disable control for this pin
    Uint16 GPIO69:1;                    // 5 Pull-Up Disable control for this pin
    Uint16 GPIO70:1;                    // 6 Pull-Up Disable control for this pin
    Uint16 GPIO71:1;                    // 7 Pull-Up Disable control for this pin
    Uint16 GPIO72:1;                    // 8 Pull-Up Disable control for this pin
    Uint16 GPIO73:1;                    // 9 Pull-Up Disable control for this pin
    Uint16 GPIO74:1;                    // 10 Pull-Up Disable control for this pin
    Uint16 GPIO75:1;                    // 11 Pull-Up Disable control for this pin
    Uint16 GPIO76:1;                    // 12 Pull-Up Disable control for this pin
    Uint16 GPIO77:1;                    // 13 Pull-Up Disable control for this pin
    Uint16 GPIO78:1;                    // 14 Pull-Up Disable control for this pin
    Uint16 GPIO79:1;                    // 15 Pull-Up Disable control for this pin
    Uint16 GPIO80:1;                    // 16 Pull-Up Disable control for this pin
    Uint16 GPIO81:1;                    // 17 Pull-Up Disable control for this pin
    Uint16 GPIO82:1;                    // 18 Pull-Up Disable control for this pin
    Uint16 GPIO83:1;                    // 19 Pull-Up Disable control for this pin
    Uint16 GPIO84:1;                    // 20 Pull-Up Disable control for this pin
    Uint16 GPIO85:1;                    // 21 Pull-Up Disable control for this pin
    Uint16 GPIO86:1;                    // 22 Pull-Up Disable control for this pin
    Uint16 GPIO87:1;                    // 23 Pull-Up Disable control for this pin
    Uint16 GPIO88:1;                    // 24 Pull-Up Disable control for this pin
    Uint16 GPIO89:1;                    // 25 Pull-Up Disable control for this pin
    Uint16 GPIO90:1;                    // 26 Pull-Up Disable control for this pin
    Uint16 GPIO91:1;                    // 27 Pull-Up Disable control for this pin
    Uint16 GPIO92:1;                    // 28 Pull-Up Disable control for this pin
    Uint16 GPIO93:1;                    // 29 Pull-Up Disable control for this pin
    Uint16 GPIO94:1;                    // 30 Pull-Up Disable control for this pin
    Uint16 GPIO95:1;                    // 31 Pull-Up Disable control for this pin
};

union GPCPUD_REG {
    Uint32  all;
    struct  GPCPUD_BITS  bit;
};

struct GPCINV_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Input inversion control for this pin
    Uint16 GPIO65:1;                    // 1 Input inversion control for this pin
    Uint16 GPIO66:1;                    // 2 Input inversion control for this pin
    Uint16 GPIO67:1;                    // 3 Input inversion control for this pin
    Uint16 GPIO68:1;                    // 4 Input inversion control for this pin
    Uint16 GPIO69:1;                    // 5 Input inversion control for this pin
    Uint16 GPIO70:1;                    // 6 Input inversion control for this pin
    Uint16 GPIO71:1;                    // 7 Input inversion control for this pin
    Uint16 GPIO72:1;                    // 8 Input inversion control for this pin
    Uint16 GPIO73:1;                    // 9 Input inversion control for this pin
    Uint16 GPIO74:1;                    // 10 Input inversion control for this pin
    Uint16 GPIO75:1;                    // 11 Input inversion control for this pin
    Uint16 GPIO76:1;                    // 12 Input inversion control for this pin
    Uint16 GPIO77:1;                    // 13 Input inversion control for this pin
    Uint16 GPIO78:1;                    // 14 Input inversion control for this pin
    Uint16 GPIO79:1;                    // 15 Input inversion control for this pin
    Uint16 GPIO80:1;                    // 16 Input inversion control for this pin
    Uint16 GPIO81:1;                    // 17 Input inversion control for this pin
    Uint16 GPIO82:1;                    // 18 Input inversion control for this pin
    Uint16 GPIO83:1;                    // 19 Input inversion control for this pin
    Uint16 GPIO84:1;                    // 20 Input inversion control for this pin
    Uint16 GPIO85:1;                    // 21 Input inversion control for this pin
    Uint16 GPIO86:1;                    // 22 Input inversion control for this pin
    Uint16 GPIO87:1;                    // 23 Input inversion control for this pin
    Uint16 GPIO88:1;                    // 24 Input inversion control for this pin
    Uint16 GPIO89:1;                    // 25 Input inversion control for this pin
    Uint16 GPIO90:1;                    // 26 Input inversion control for this pin
    Uint16 GPIO91:1;                    // 27 Input inversion control for this pin
    Uint16 GPIO92:1;                    // 28 Input inversion control for this pin
    Uint16 GPIO93:1;                    // 29 Input inversion control for this pin
    Uint16 GPIO94:1;                    // 30 Input inversion control for this pin
    Uint16 GPIO95:1;                    // 31 Input inversion control for this pin
};

union GPCINV_REG {
    Uint32  all;
    struct  GPCINV_BITS  bit;
};

struct GPCODR_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO65:1;                    // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO66:1;                    // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO67:1;                    // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO68:1;                    // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO69:1;                    // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO70:1;                    // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO71:1;                    // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO72:1;                    // 8 Outpout Open-Drain control for this pin
    Uint16 GPIO73:1;                    // 9 Outpout Open-Drain control for this pin
    Uint16 GPIO74:1;                    // 10 Outpout Open-Drain control for this pin
    Uint16 GPIO75:1;                    // 11 Outpout Open-Drain control for this pin
    Uint16 GPIO76:1;                    // 12 Outpout Open-Drain control for this pin
    Uint16 GPIO77:1;                    // 13 Outpout Open-Drain control for this pin
    Uint16 GPIO78:1;                    // 14 Outpout Open-Drain control for this pin
    Uint16 GPIO79:1;                    // 15 Outpout Open-Drain control for this pin
    Uint16 GPIO80:1;                    // 16 Outpout Open-Drain control for this pin
    Uint16 GPIO81:1;                    // 17 Outpout Open-Drain control for this pin
    Uint16 GPIO82:1;                    // 18 Outpout Open-Drain control for this pin
    Uint16 GPIO83:1;                    // 19 Outpout Open-Drain control for this pin
    Uint16 GPIO84:1;                    // 20 Outpout Open-Drain control for this pin
    Uint16 GPIO85:1;                    // 21 Outpout Open-Drain control for this pin
    Uint16 GPIO86:1;                    // 22 Outpout Open-Drain control for this pin
    Uint16 GPIO87:1;                    // 23 Outpout Open-Drain control for this pin
    Uint16 GPIO88:1;                    // 24 Outpout Open-Drain control for this pin
    Uint16 GPIO89:1;                    // 25 Outpout Open-Drain control for this pin
    Uint16 GPIO90:1;                    // 26 Outpout Open-Drain control for this pin
    Uint16 GPIO91:1;                    // 27 Outpout Open-Drain control for this pin
    Uint16 GPIO92:1;                    // 28 Outpout Open-Drain control for this pin
    Uint16 GPIO93:1;                    // 29 Outpout Open-Drain control for this pin
    Uint16 GPIO94:1;                    // 30 Outpout Open-Drain control for this pin
    Uint16 GPIO95:1;                    // 31 Outpout Open-Drain control for this pin
};

union GPCODR_REG {
    Uint32  all;
    struct  GPCODR_BITS  bit;
};

struct GPCGMUX1_BITS {                  // bits description
    Uint16 GPIO64:2;                    // 1:0 Defines pin-muxing selection for GPIO64
    Uint16 GPIO65:2;                    // 3:2 Defines pin-muxing selection for GPIO65
    Uint16 GPIO66:2;                    // 5:4 Defines pin-muxing selection for GPIO66
    Uint16 GPIO67:2;                    // 7:6 Defines pin-muxing selection for GPIO67
    Uint16 GPIO68:2;                    // 9:8 Defines pin-muxing selection for GPIO68
    Uint16 GPIO69:2;                    // 11:10 Defines pin-muxing selection for GPIO69
    Uint16 GPIO70:2;                    // 13:12 Defines pin-muxing selection for GPIO70
    Uint16 GPIO71:2;                    // 15:14 Defines pin-muxing selection for GPIO71
    Uint16 GPIO72:2;                    // 17:16 Defines pin-muxing selection for GPIO72
    Uint16 GPIO73:2;                    // 19:18 Defines pin-muxing selection for GPIO73
    Uint16 GPIO74:2;                    // 21:20 Defines pin-muxing selection for GPIO74
    Uint16 GPIO75:2;                    // 23:22 Defines pin-muxing selection for GPIO75
    Uint16 GPIO76:2;                    // 25:24 Defines pin-muxing selection for GPIO76
    Uint16 GPIO77:2;                    // 27:26 Defines pin-muxing selection for GPIO77
    Uint16 GPIO78:2;                    // 29:28 Defines pin-muxing selection for GPIO78
    Uint16 GPIO79:2;                    // 31:30 Defines pin-muxing selection for GPIO79
};

union GPCGMUX1_REG {
    Uint32  all;
    struct  GPCGMUX1_BITS  bit;
};

struct GPCGMUX2_BITS {                  // bits description
    Uint16 GPIO80:2;                    // 1:0 Defines pin-muxing selection for GPIO80
    Uint16 GPIO81:2;                    // 3:2 Defines pin-muxing selection for GPIO81
    Uint16 GPIO82:2;                    // 5:4 Defines pin-muxing selection for GPIO82
    Uint16 GPIO83:2;                    // 7:6 Defines pin-muxing selection for GPIO83
    Uint16 GPIO84:2;                    // 9:8 Defines pin-muxing selection for GPIO84
    Uint16 GPIO85:2;                    // 11:10 Defines pin-muxing selection for GPIO85
    Uint16 GPIO86:2;                    // 13:12 Defines pin-muxing selection for GPIO86
    Uint16 GPIO87:2;                    // 15:14 Defines pin-muxing selection for GPIO87
    Uint16 GPIO88:2;                    // 17:16 Defines pin-muxing selection for GPIO88
    Uint16 GPIO89:2;                    // 19:18 Defines pin-muxing selection for GPIO89
    Uint16 GPIO90:2;                    // 21:20 Defines pin-muxing selection for GPIO90
    Uint16 GPIO91:2;                    // 23:22 Defines pin-muxing selection for GPIO91
    Uint16 GPIO92:2;                    // 25:24 Defines pin-muxing selection for GPIO92
    Uint16 GPIO93:2;                    // 27:26 Defines pin-muxing selection for GPIO93
    Uint16 GPIO94:2;                    // 29:28 Defines pin-muxing selection for GPIO94
    Uint16 GPIO95:2;                    // 31:30 Defines pin-muxing selection for GPIO95
};

union GPCGMUX2_REG {
    Uint32  all;
    struct  GPCGMUX2_BITS  bit;
};

struct GPCCSEL1_BITS {                  // bits description
    Uint16 GPIO64:4;                    // 3:0 GPIO64 Master CPU Select
    Uint16 GPIO65:4;                    // 7:4 GPIO65 Master CPU Select
    Uint16 GPIO66:4;                    // 11:8 GPIO66 Master CPU Select
    Uint16 GPIO67:4;                    // 15:12 GPIO67 Master CPU Select
    Uint16 GPIO68:4;                    // 19:16 GPIO68 Master CPU Select
    Uint16 GPIO69:4;                    // 23:20 GPIO69 Master CPU Select
    Uint16 GPIO70:4;                    // 27:24 GPIO70 Master CPU Select
    Uint16 GPIO71:4;                    // 31:28 GPIO71 Master CPU Select
};

union GPCCSEL1_REG {
    Uint32  all;
    struct  GPCCSEL1_BITS  bit;
};

struct GPCCSEL2_BITS {                  // bits description
    Uint16 GPIO72:4;                    // 3:0 GPIO72 Master CPU Select
    Uint16 GPIO73:4;                    // 7:4 GPIO73 Master CPU Select
    Uint16 GPIO74:4;                    // 11:8 GPIO74 Master CPU Select
    Uint16 GPIO75:4;                    // 15:12 GPIO75 Master CPU Select
    Uint16 GPIO76:4;                    // 19:16 GPIO76 Master CPU Select
    Uint16 GPIO77:4;                    // 23:20 GPIO77 Master CPU Select
    Uint16 GPIO78:4;                    // 27:24 GPIO78 Master CPU Select
    Uint16 GPIO79:4;                    // 31:28 GPIO79 Master CPU Select
};

union GPCCSEL2_REG {
    Uint32  all;
    struct  GPCCSEL2_BITS  bit;
};

struct GPCCSEL3_BITS {                  // bits description
    Uint16 GPIO80:4;                    // 3:0 GPIO80 Master CPU Select
    Uint16 GPIO81:4;                    // 7:4 GPIO81 Master CPU Select
    Uint16 GPIO82:4;                    // 11:8 GPIO82 Master CPU Select
    Uint16 GPIO83:4;                    // 15:12 GPIO83 Master CPU Select
    Uint16 GPIO84:4;                    // 19:16 GPIO84 Master CPU Select
    Uint16 GPIO85:4;                    // 23:20 GPIO85 Master CPU Select
    Uint16 GPIO86:4;                    // 27:24 GPIO86 Master CPU Select
    Uint16 GPIO87:4;                    // 31:28 GPIO87 Master CPU Select
};

union GPCCSEL3_REG {
    Uint32  all;
    struct  GPCCSEL3_BITS  bit;
};

struct GPCCSEL4_BITS {                  // bits description
    Uint16 GPIO88:4;                    // 3:0 GPIO88 Master CPU Select
    Uint16 GPIO89:4;                    // 7:4 GPIO89 Master CPU Select
    Uint16 GPIO90:4;                    // 11:8 GPIO90 Master CPU Select
    Uint16 GPIO91:4;                    // 15:12 GPIO91 Master CPU Select
    Uint16 GPIO92:4;                    // 19:16 GPIO92 Master CPU Select
    Uint16 GPIO93:4;                    // 23:20 GPIO93 Master CPU Select
    Uint16 GPIO94:4;                    // 27:24 GPIO94 Master CPU Select
    Uint16 GPIO95:4;                    // 31:28 GPIO95 Master CPU Select
};

union GPCCSEL4_REG {
    Uint32  all;
    struct  GPCCSEL4_BITS  bit;
};

struct GPCLOCK_BITS {                   // bits description
    Uint16 GPIO64:1;                    // 0 Configuration Lock bit for this pin
    Uint16 GPIO65:1;                    // 1 Configuration Lock bit for this pin
    Uint16 GPIO66:1;                    // 2 Configuration Lock bit for this pin
    Uint16 GPIO67:1;                    // 3 Configuration Lock bit for this pin
    Uint16 GPIO68:1;                    // 4 Configuration Lock bit for this pin
    Uint16 GPIO69:1;                    // 5 Configuration Lock bit for this pin
    Uint16 GPIO70:1;                    // 6 Configuration Lock bit for this pin
    Uint16 GPIO71:1;                    // 7 Configuration Lock bit for this pin
    Uint16 GPIO72:1;                    // 8 Configuration Lock bit for this pin
    Uint16 GPIO73:1;                    // 9 Configuration Lock bit for this pin
    Uint16 GPIO74:1;                    // 10 Configuration Lock bit for this pin
    Uint16 GPIO75:1;                    // 11 Configuration Lock bit for this pin
    Uint16 GPIO76:1;                    // 12 Configuration Lock bit for this pin
    Uint16 GPIO77:1;                    // 13 Configuration Lock bit for this pin
    Uint16 GPIO78:1;                    // 14 Configuration Lock bit for this pin
    Uint16 GPIO79:1;                    // 15 Configuration Lock bit for this pin
    Uint16 GPIO80:1;                    // 16 Configuration Lock bit for this pin
    Uint16 GPIO81:1;                    // 17 Configuration Lock bit for this pin
    Uint16 GPIO82:1;                    // 18 Configuration Lock bit for this pin
    Uint16 GPIO83:1;                    // 19 Configuration Lock bit for this pin
    Uint16 GPIO84:1;                    // 20 Configuration Lock bit for this pin
    Uint16 GPIO85:1;                    // 21 Configuration Lock bit for this pin
    Uint16 GPIO86:1;                    // 22 Configuration Lock bit for this pin
    Uint16 GPIO87:1;                    // 23 Configuration Lock bit for this pin
    Uint16 GPIO88:1;                    // 24 Configuration Lock bit for this pin
    Uint16 GPIO89:1;                    // 25 Configuration Lock bit for this pin
    Uint16 GPIO90:1;                    // 26 Configuration Lock bit for this pin
    Uint16 GPIO91:1;                    // 27 Configuration Lock bit for this pin
    Uint16 GPIO92:1;                    // 28 Configuration Lock bit for this pin
    Uint16 GPIO93:1;                    // 29 Configuration Lock bit for this pin
    Uint16 GPIO94:1;                    // 30 Configuration Lock bit for this pin
    Uint16 GPIO95:1;                    // 31 Configuration Lock bit for this pin
};

union GPCLOCK_REG {
    Uint32  all;
    struct  GPCLOCK_BITS  bit;
};

struct GPCCR_BITS {                     // bits description
    Uint16 GPIO64:1;                    // 0 Configuration lock commit bit for this pin
    Uint16 GPIO65:1;                    // 1 Configuration lock commit bit for this pin
    Uint16 GPIO66:1;                    // 2 Configuration lock commit bit for this pin
    Uint16 GPIO67:1;                    // 3 Configuration lock commit bit for this pin
    Uint16 GPIO68:1;                    // 4 Configuration lock commit bit for this pin
    Uint16 GPIO69:1;                    // 5 Configuration lock commit bit for this pin
    Uint16 GPIO70:1;                    // 6 Configuration lock commit bit for this pin
    Uint16 GPIO71:1;                    // 7 Configuration lock commit bit for this pin
    Uint16 GPIO72:1;                    // 8 Configuration lock commit bit for this pin
    Uint16 GPIO73:1;                    // 9 Configuration lock commit bit for this pin
    Uint16 GPIO74:1;                    // 10 Configuration lock commit bit for this pin
    Uint16 GPIO75:1;                    // 11 Configuration lock commit bit for this pin
    Uint16 GPIO76:1;                    // 12 Configuration lock commit bit for this pin
    Uint16 GPIO77:1;                    // 13 Configuration lock commit bit for this pin
    Uint16 GPIO78:1;                    // 14 Configuration lock commit bit for this pin
    Uint16 GPIO79:1;                    // 15 Configuration lock commit bit for this pin
    Uint16 GPIO80:1;                    // 16 Configuration lock commit bit for this pin
    Uint16 GPIO81:1;                    // 17 Configuration lock commit bit for this pin
    Uint16 GPIO82:1;                    // 18 Configuration lock commit bit for this pin
    Uint16 GPIO83:1;                    // 19 Configuration lock commit bit for this pin
    Uint16 GPIO84:1;                    // 20 Configuration lock commit bit for this pin
    Uint16 GPIO85:1;                    // 21 Configuration lock commit bit for this pin
    Uint16 GPIO86:1;                    // 22 Configuration lock commit bit for this pin
    Uint16 GPIO87:1;                    // 23 Configuration lock commit bit for this pin
    Uint16 GPIO88:1;                    // 24 Configuration lock commit bit for this pin
    Uint16 GPIO89:1;                    // 25 Configuration lock commit bit for this pin
    Uint16 GPIO90:1;                    // 26 Configuration lock commit bit for this pin
    Uint16 GPIO91:1;                    // 27 Configuration lock commit bit for this pin
    Uint16 GPIO92:1;                    // 28 Configuration lock commit bit for this pin
    Uint16 GPIO93:1;                    // 29 Configuration lock commit bit for this pin
    Uint16 GPIO94:1;                    // 30 Configuration lock commit bit for this pin
    Uint16 GPIO95:1;                    // 31 Configuration lock commit bit for this pin
};

union GPCCR_REG {
    Uint32  all;
    struct  GPCCR_BITS  bit;
};

struct GPDCTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO96 to GPIO103
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO104 to GPIO111
    Uint16 QUALPRD2:8;                  // 23:16 Qualification sampling period for GPIO112 to GPIO119
    Uint16 QUALPRD3:8;                  // 31:24 Qualification sampling period for GPIO120 to GPIO127
};

union GPDCTRL_REG {
    Uint32  all;
    struct  GPDCTRL_BITS  bit;
};

struct GPDQSEL1_BITS {                  // bits description
    Uint16 GPIO96:2;                    // 1:0 Select input qualification type for GPIO96
    Uint16 GPIO97:2;                    // 3:2 Select input qualification type for GPIO97
    Uint16 GPIO98:2;                    // 5:4 Select input qualification type for GPIO98
    Uint16 GPIO99:2;                    // 7:6 Select input qualification type for GPIO99
    Uint16 GPIO100:2;                   // 9:8 Select input qualification type for GPIO100
    Uint16 GPIO101:2;                   // 11:10 Select input qualification type for GPIO101
    Uint16 GPIO102:2;                   // 13:12 Select input qualification type for GPIO102
    Uint16 GPIO103:2;                   // 15:14 Select input qualification type for GPIO103
    Uint16 GPIO104:2;                   // 17:16 Select input qualification type for GPIO104
    Uint16 GPIO105:2;                   // 19:18 Select input qualification type for GPIO105
    Uint16 GPIO106:2;                   // 21:20 Select input qualification type for GPIO106
    Uint16 GPIO107:2;                   // 23:22 Select input qualification type for GPIO107
    Uint16 GPIO108:2;                   // 25:24 Select input qualification type for GPIO108
    Uint16 GPIO109:2;                   // 27:26 Select input qualification type for GPIO109
    Uint16 GPIO110:2;                   // 29:28 Select input qualification type for GPIO110
    Uint16 GPIO111:2;                   // 31:30 Select input qualification type for GPIO111
};

union GPDQSEL1_REG {
    Uint32  all;
    struct  GPDQSEL1_BITS  bit;
};

struct GPDQSEL2_BITS {                  // bits description
    Uint16 GPIO112:2;                   // 1:0 Select input qualification type for GPIO112
    Uint16 GPIO113:2;                   // 3:2 Select input qualification type for GPIO113
    Uint16 GPIO114:2;                   // 5:4 Select input qualification type for GPIO114
    Uint16 GPIO115:2;                   // 7:6 Select input qualification type for GPIO115
    Uint16 GPIO116:2;                   // 9:8 Select input qualification type for GPIO116
    Uint16 GPIO117:2;                   // 11:10 Select input qualification type for GPIO117
    Uint16 GPIO118:2;                   // 13:12 Select input qualification type for GPIO118
    Uint16 GPIO119:2;                   // 15:14 Select input qualification type for GPIO119
    Uint16 GPIO120:2;                   // 17:16 Select input qualification type for GPIO120
    Uint16 GPIO121:2;                   // 19:18 Select input qualification type for GPIO121
    Uint16 GPIO122:2;                   // 21:20 Select input qualification type for GPIO122
    Uint16 GPIO123:2;                   // 23:22 Select input qualification type for GPIO123
    Uint16 GPIO124:2;                   // 25:24 Select input qualification type for GPIO124
    Uint16 GPIO125:2;                   // 27:26 Select input qualification type for GPIO125
    Uint16 GPIO126:2;                   // 29:28 Select input qualification type for GPIO126
    Uint16 GPIO127:2;                   // 31:30 Select input qualification type for GPIO127
};

union GPDQSEL2_REG {
    Uint32  all;
    struct  GPDQSEL2_BITS  bit;
};

struct GPDMUX1_BITS {                   // bits description
    Uint16 GPIO96:2;                    // 1:0 Defines pin-muxing selection for GPIO96
    Uint16 GPIO97:2;                    // 3:2 Defines pin-muxing selection for GPIO97
    Uint16 GPIO98:2;                    // 5:4 Defines pin-muxing selection for GPIO98
    Uint16 GPIO99:2;                    // 7:6 Defines pin-muxing selection for GPIO99
    Uint16 GPIO100:2;                   // 9:8 Defines pin-muxing selection for GPIO100
    Uint16 GPIO101:2;                   // 11:10 Defines pin-muxing selection for GPIO101
    Uint16 GPIO102:2;                   // 13:12 Defines pin-muxing selection for GPIO102
    Uint16 GPIO103:2;                   // 15:14 Defines pin-muxing selection for GPIO103
    Uint16 GPIO104:2;                   // 17:16 Defines pin-muxing selection for GPIO104
    Uint16 GPIO105:2;                   // 19:18 Defines pin-muxing selection for GPIO105
    Uint16 GPIO106:2;                   // 21:20 Defines pin-muxing selection for GPIO106
    Uint16 GPIO107:2;                   // 23:22 Defines pin-muxing selection for GPIO107
    Uint16 GPIO108:2;                   // 25:24 Defines pin-muxing selection for GPIO108
    Uint16 GPIO109:2;                   // 27:26 Defines pin-muxing selection for GPIO109
    Uint16 GPIO110:2;                   // 29:28 Defines pin-muxing selection for GPIO110
    Uint16 GPIO111:2;                   // 31:30 Defines pin-muxing selection for GPIO111
};

union GPDMUX1_REG {
    Uint32  all;
    struct  GPDMUX1_BITS  bit;
};

struct GPDMUX2_BITS {                   // bits description
    Uint16 GPIO112:2;                   // 1:0 Defines pin-muxing selection for GPIO112
    Uint16 GPIO113:2;                   // 3:2 Defines pin-muxing selection for GPIO113
    Uint16 GPIO114:2;                   // 5:4 Defines pin-muxing selection for GPIO114
    Uint16 GPIO115:2;                   // 7:6 Defines pin-muxing selection for GPIO115
    Uint16 GPIO116:2;                   // 9:8 Defines pin-muxing selection for GPIO116
    Uint16 GPIO117:2;                   // 11:10 Defines pin-muxing selection for GPIO117
    Uint16 GPIO118:2;                   // 13:12 Defines pin-muxing selection for GPIO118
    Uint16 GPIO119:2;                   // 15:14 Defines pin-muxing selection for GPIO119
    Uint16 GPIO120:2;                   // 17:16 Defines pin-muxing selection for GPIO120
    Uint16 GPIO121:2;                   // 19:18 Defines pin-muxing selection for GPIO121
    Uint16 GPIO122:2;                   // 21:20 Defines pin-muxing selection for GPIO122
    Uint16 GPIO123:2;                   // 23:22 Defines pin-muxing selection for GPIO123
    Uint16 GPIO124:2;                   // 25:24 Defines pin-muxing selection for GPIO124
    Uint16 GPIO125:2;                   // 27:26 Defines pin-muxing selection for GPIO125
    Uint16 GPIO126:2;                   // 29:28 Defines pin-muxing selection for GPIO126
    Uint16 GPIO127:2;                   // 31:30 Defines pin-muxing selection for GPIO127
};

union GPDMUX2_REG {
    Uint32  all;
    struct  GPDMUX2_BITS  bit;
};

struct GPDDIR_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO97:1;                    // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO98:1;                    // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO99:1;                    // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO100:1;                   // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO101:1;                   // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO102:1;                   // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO103:1;                   // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO104:1;                   // 8 Defines direction for this pin in GPIO mode
    Uint16 GPIO105:1;                   // 9 Defines direction for this pin in GPIO mode
    Uint16 GPIO106:1;                   // 10 Defines direction for this pin in GPIO mode
    Uint16 GPIO107:1;                   // 11 Defines direction for this pin in GPIO mode
    Uint16 GPIO108:1;                   // 12 Defines direction for this pin in GPIO mode
    Uint16 GPIO109:1;                   // 13 Defines direction for this pin in GPIO mode
    Uint16 GPIO110:1;                   // 14 Defines direction for this pin in GPIO mode
    Uint16 GPIO111:1;                   // 15 Defines direction for this pin in GPIO mode
    Uint16 GPIO112:1;                   // 16 Defines direction for this pin in GPIO mode
    Uint16 GPIO113:1;                   // 17 Defines direction for this pin in GPIO mode
    Uint16 GPIO114:1;                   // 18 Defines direction for this pin in GPIO mode
    Uint16 GPIO115:1;                   // 19 Defines direction for this pin in GPIO mode
    Uint16 GPIO116:1;                   // 20 Defines direction for this pin in GPIO mode
    Uint16 GPIO117:1;                   // 21 Defines direction for this pin in GPIO mode
    Uint16 GPIO118:1;                   // 22 Defines direction for this pin in GPIO mode
    Uint16 GPIO119:1;                   // 23 Defines direction for this pin in GPIO mode
    Uint16 GPIO120:1;                   // 24 Defines direction for this pin in GPIO mode
    Uint16 GPIO121:1;                   // 25 Defines direction for this pin in GPIO mode
    Uint16 GPIO122:1;                   // 26 Defines direction for this pin in GPIO mode
    Uint16 GPIO123:1;                   // 27 Defines direction for this pin in GPIO mode
    Uint16 GPIO124:1;                   // 28 Defines direction for this pin in GPIO mode
    Uint16 GPIO125:1;                   // 29 Defines direction for this pin in GPIO mode
    Uint16 GPIO126:1;                   // 30 Defines direction for this pin in GPIO mode
    Uint16 GPIO127:1;                   // 31 Defines direction for this pin in GPIO mode
};

union GPDDIR_REG {
    Uint32  all;
    struct  GPDDIR_BITS  bit;
};

struct GPDPUD_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Pull-Up Disable control for this pin
    Uint16 GPIO97:1;                    // 1 Pull-Up Disable control for this pin
    Uint16 GPIO98:1;                    // 2 Pull-Up Disable control for this pin
    Uint16 GPIO99:1;                    // 3 Pull-Up Disable control for this pin
    Uint16 GPIO100:1;                   // 4 Pull-Up Disable control for this pin
    Uint16 GPIO101:1;                   // 5 Pull-Up Disable control for this pin
    Uint16 GPIO102:1;                   // 6 Pull-Up Disable control for this pin
    Uint16 GPIO103:1;                   // 7 Pull-Up Disable control for this pin
    Uint16 GPIO104:1;                   // 8 Pull-Up Disable control for this pin
    Uint16 GPIO105:1;                   // 9 Pull-Up Disable control for this pin
    Uint16 GPIO106:1;                   // 10 Pull-Up Disable control for this pin
    Uint16 GPIO107:1;                   // 11 Pull-Up Disable control for this pin
    Uint16 GPIO108:1;                   // 12 Pull-Up Disable control for this pin
    Uint16 GPIO109:1;                   // 13 Pull-Up Disable control for this pin
    Uint16 GPIO110:1;                   // 14 Pull-Up Disable control for this pin
    Uint16 GPIO111:1;                   // 15 Pull-Up Disable control for this pin
    Uint16 GPIO112:1;                   // 16 Pull-Up Disable control for this pin
    Uint16 GPIO113:1;                   // 17 Pull-Up Disable control for this pin
    Uint16 GPIO114:1;                   // 18 Pull-Up Disable control for this pin
    Uint16 GPIO115:1;                   // 19 Pull-Up Disable control for this pin
    Uint16 GPIO116:1;                   // 20 Pull-Up Disable control for this pin
    Uint16 GPIO117:1;                   // 21 Pull-Up Disable control for this pin
    Uint16 GPIO118:1;                   // 22 Pull-Up Disable control for this pin
    Uint16 GPIO119:1;                   // 23 Pull-Up Disable control for this pin
    Uint16 GPIO120:1;                   // 24 Pull-Up Disable control for this pin
    Uint16 GPIO121:1;                   // 25 Pull-Up Disable control for this pin
    Uint16 GPIO122:1;                   // 26 Pull-Up Disable control for this pin
    Uint16 GPIO123:1;                   // 27 Pull-Up Disable control for this pin
    Uint16 GPIO124:1;                   // 28 Pull-Up Disable control for this pin
    Uint16 GPIO125:1;                   // 29 Pull-Up Disable control for this pin
    Uint16 GPIO126:1;                   // 30 Pull-Up Disable control for this pin
    Uint16 GPIO127:1;                   // 31 Pull-Up Disable control for this pin
};

union GPDPUD_REG {
    Uint32  all;
    struct  GPDPUD_BITS  bit;
};

struct GPDINV_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Input inversion control for this pin
    Uint16 GPIO97:1;                    // 1 Input inversion control for this pin
    Uint16 GPIO98:1;                    // 2 Input inversion control for this pin
    Uint16 GPIO99:1;                    // 3 Input inversion control for this pin
    Uint16 GPIO100:1;                   // 4 Input inversion control for this pin
    Uint16 GPIO101:1;                   // 5 Input inversion control for this pin
    Uint16 GPIO102:1;                   // 6 Input inversion control for this pin
    Uint16 GPIO103:1;                   // 7 Input inversion control for this pin
    Uint16 GPIO104:1;                   // 8 Input inversion control for this pin
    Uint16 GPIO105:1;                   // 9 Input inversion control for this pin
    Uint16 GPIO106:1;                   // 10 Input inversion control for this pin
    Uint16 GPIO107:1;                   // 11 Input inversion control for this pin
    Uint16 GPIO108:1;                   // 12 Input inversion control for this pin
    Uint16 GPIO109:1;                   // 13 Input inversion control for this pin
    Uint16 GPIO110:1;                   // 14 Input inversion control for this pin
    Uint16 GPIO111:1;                   // 15 Input inversion control for this pin
    Uint16 GPIO112:1;                   // 16 Input inversion control for this pin
    Uint16 GPIO113:1;                   // 17 Input inversion control for this pin
    Uint16 GPIO114:1;                   // 18 Input inversion control for this pin
    Uint16 GPIO115:1;                   // 19 Input inversion control for this pin
    Uint16 GPIO116:1;                   // 20 Input inversion control for this pin
    Uint16 GPIO117:1;                   // 21 Input inversion control for this pin
    Uint16 GPIO118:1;                   // 22 Input inversion control for this pin
    Uint16 GPIO119:1;                   // 23 Input inversion control for this pin
    Uint16 GPIO120:1;                   // 24 Input inversion control for this pin
    Uint16 GPIO121:1;                   // 25 Input inversion control for this pin
    Uint16 GPIO122:1;                   // 26 Input inversion control for this pin
    Uint16 GPIO123:1;                   // 27 Input inversion control for this pin
    Uint16 GPIO124:1;                   // 28 Input inversion control for this pin
    Uint16 GPIO125:1;                   // 29 Input inversion control for this pin
    Uint16 GPIO126:1;                   // 30 Input inversion control for this pin
    Uint16 GPIO127:1;                   // 31 Input inversion control for this pin
};

union GPDINV_REG {
    Uint32  all;
    struct  GPDINV_BITS  bit;
};

struct GPDODR_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO97:1;                    // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO98:1;                    // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO99:1;                    // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO100:1;                   // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO101:1;                   // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO102:1;                   // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO103:1;                   // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO104:1;                   // 8 Outpout Open-Drain control for this pin
    Uint16 GPIO105:1;                   // 9 Outpout Open-Drain control for this pin
    Uint16 GPIO106:1;                   // 10 Outpout Open-Drain control for this pin
    Uint16 GPIO107:1;                   // 11 Outpout Open-Drain control for this pin
    Uint16 GPIO108:1;                   // 12 Outpout Open-Drain control for this pin
    Uint16 GPIO109:1;                   // 13 Outpout Open-Drain control for this pin
    Uint16 GPIO110:1;                   // 14 Outpout Open-Drain control for this pin
    Uint16 GPIO111:1;                   // 15 Outpout Open-Drain control for this pin
    Uint16 GPIO112:1;                   // 16 Outpout Open-Drain control for this pin
    Uint16 GPIO113:1;                   // 17 Outpout Open-Drain control for this pin
    Uint16 GPIO114:1;                   // 18 Outpout Open-Drain control for this pin
    Uint16 GPIO115:1;                   // 19 Outpout Open-Drain control for this pin
    Uint16 GPIO116:1;                   // 20 Outpout Open-Drain control for this pin
    Uint16 GPIO117:1;                   // 21 Outpout Open-Drain control for this pin
    Uint16 GPIO118:1;                   // 22 Outpout Open-Drain control for this pin
    Uint16 GPIO119:1;                   // 23 Outpout Open-Drain control for this pin
    Uint16 GPIO120:1;                   // 24 Outpout Open-Drain control for this pin
    Uint16 GPIO121:1;                   // 25 Outpout Open-Drain control for this pin
    Uint16 GPIO122:1;                   // 26 Outpout Open-Drain control for this pin
    Uint16 GPIO123:1;                   // 27 Outpout Open-Drain control for this pin
    Uint16 GPIO124:1;                   // 28 Outpout Open-Drain control for this pin
    Uint16 GPIO125:1;                   // 29 Outpout Open-Drain control for this pin
    Uint16 GPIO126:1;                   // 30 Outpout Open-Drain control for this pin
    Uint16 GPIO127:1;                   // 31 Outpout Open-Drain control for this pin
};

union GPDODR_REG {
    Uint32  all;
    struct  GPDODR_BITS  bit;
};

struct GPDGMUX1_BITS {                  // bits description
    Uint16 GPIO96:2;                    // 1:0 Defines pin-muxing selection for GPIO96
    Uint16 GPIO97:2;                    // 3:2 Defines pin-muxing selection for GPIO97
    Uint16 GPIO98:2;                    // 5:4 Defines pin-muxing selection for GPIO98
    Uint16 GPIO99:2;                    // 7:6 Defines pin-muxing selection for GPIO99
    Uint16 GPIO100:2;                   // 9:8 Defines pin-muxing selection for GPIO100
    Uint16 GPIO101:2;                   // 11:10 Defines pin-muxing selection for GPIO101
    Uint16 GPIO102:2;                   // 13:12 Defines pin-muxing selection for GPIO102
    Uint16 GPIO103:2;                   // 15:14 Defines pin-muxing selection for GPIO103
    Uint16 GPIO104:2;                   // 17:16 Defines pin-muxing selection for GPIO104
    Uint16 GPIO105:2;                   // 19:18 Defines pin-muxing selection for GPIO105
    Uint16 GPIO106:2;                   // 21:20 Defines pin-muxing selection for GPIO106
    Uint16 GPIO107:2;                   // 23:22 Defines pin-muxing selection for GPIO107
    Uint16 GPIO108:2;                   // 25:24 Defines pin-muxing selection for GPIO108
    Uint16 GPIO109:2;                   // 27:26 Defines pin-muxing selection for GPIO109
    Uint16 GPIO110:2;                   // 29:28 Defines pin-muxing selection for GPIO110
    Uint16 GPIO111:2;                   // 31:30 Defines pin-muxing selection for GPIO111
};

union GPDGMUX1_REG {
    Uint32  all;
    struct  GPDGMUX1_BITS  bit;
};

struct GPDGMUX2_BITS {                  // bits description
    Uint16 GPIO112:2;                   // 1:0 Defines pin-muxing selection for GPIO112
    Uint16 GPIO113:2;                   // 3:2 Defines pin-muxing selection for GPIO113
    Uint16 GPIO114:2;                   // 5:4 Defines pin-muxing selection for GPIO114
    Uint16 GPIO115:2;                   // 7:6 Defines pin-muxing selection for GPIO115
    Uint16 GPIO116:2;                   // 9:8 Defines pin-muxing selection for GPIO116
    Uint16 GPIO117:2;                   // 11:10 Defines pin-muxing selection for GPIO117
    Uint16 GPIO118:2;                   // 13:12 Defines pin-muxing selection for GPIO118
    Uint16 GPIO119:2;                   // 15:14 Defines pin-muxing selection for GPIO119
    Uint16 GPIO120:2;                   // 17:16 Defines pin-muxing selection for GPIO120
    Uint16 GPIO121:2;                   // 19:18 Defines pin-muxing selection for GPIO121
    Uint16 GPIO122:2;                   // 21:20 Defines pin-muxing selection for GPIO122
    Uint16 GPIO123:2;                   // 23:22 Defines pin-muxing selection for GPIO123
    Uint16 GPIO124:2;                   // 25:24 Defines pin-muxing selection for GPIO124
    Uint16 GPIO125:2;                   // 27:26 Defines pin-muxing selection for GPIO125
    Uint16 GPIO126:2;                   // 29:28 Defines pin-muxing selection for GPIO126
    Uint16 GPIO127:2;                   // 31:30 Defines pin-muxing selection for GPIO127
};

union GPDGMUX2_REG {
    Uint32  all;
    struct  GPDGMUX2_BITS  bit;
};

struct GPDCSEL1_BITS {                  // bits description
    Uint16 GPIO96:4;                    // 3:0 GPIO96 Master CPU Select
    Uint16 GPIO97:4;                    // 7:4 GPIO97 Master CPU Select
    Uint16 GPIO98:4;                    // 11:8 GPIO98 Master CPU Select
    Uint16 GPIO99:4;                    // 15:12 GPIO99 Master CPU Select
    Uint16 GPIO100:4;                   // 19:16 GPIO100 Master CPU Select
    Uint16 GPIO101:4;                   // 23:20 GPIO101 Master CPU Select
    Uint16 GPIO102:4;                   // 27:24 GPIO102 Master CPU Select
    Uint16 GPIO103:4;                   // 31:28 GPIO103 Master CPU Select
};

union GPDCSEL1_REG {
    Uint32  all;
    struct  GPDCSEL1_BITS  bit;
};

struct GPDCSEL2_BITS {                  // bits description
    Uint16 GPIO104:4;                   // 3:0 GPIO104 Master CPU Select
    Uint16 GPIO105:4;                   // 7:4 GPIO105 Master CPU Select
    Uint16 GPIO106:4;                   // 11:8 GPIO106 Master CPU Select
    Uint16 GPIO107:4;                   // 15:12 GPIO107 Master CPU Select
    Uint16 GPIO108:4;                   // 19:16 GPIO108 Master CPU Select
    Uint16 GPIO109:4;                   // 23:20 GPIO109 Master CPU Select
    Uint16 GPIO110:4;                   // 27:24 GPIO110 Master CPU Select
    Uint16 GPIO111:4;                   // 31:28 GPIO111 Master CPU Select
};

union GPDCSEL2_REG {
    Uint32  all;
    struct  GPDCSEL2_BITS  bit;
};

struct GPDCSEL3_BITS {                  // bits description
    Uint16 GPIO112:4;                   // 3:0 GPIO112 Master CPU Select
    Uint16 GPIO113:4;                   // 7:4 GPIO113 Master CPU Select
    Uint16 GPIO114:4;                   // 11:8 GPIO114 Master CPU Select
    Uint16 GPIO115:4;                   // 15:12 GPIO115 Master CPU Select
    Uint16 GPIO116:4;                   // 19:16 GPIO116 Master CPU Select
    Uint16 GPIO117:4;                   // 23:20 GPIO117 Master CPU Select
    Uint16 GPIO118:4;                   // 27:24 GPIO118 Master CPU Select
    Uint16 GPIO119:4;                   // 31:28 GPIO119 Master CPU Select
};

union GPDCSEL3_REG {
    Uint32  all;
    struct  GPDCSEL3_BITS  bit;
};

struct GPDCSEL4_BITS {                  // bits description
    Uint16 GPIO120:4;                   // 3:0 GPIO120 Master CPU Select
    Uint16 GPIO121:4;                   // 7:4 GPIO121 Master CPU Select
    Uint16 GPIO122:4;                   // 11:8 GPIO122 Master CPU Select
    Uint16 GPIO123:4;                   // 15:12 GPIO123 Master CPU Select
    Uint16 GPIO124:4;                   // 19:16 GPIO124 Master CPU Select
    Uint16 GPIO125:4;                   // 23:20 GPIO125 Master CPU Select
    Uint16 GPIO126:4;                   // 27:24 GPIO126 Master CPU Select
    Uint16 GPIO127:4;                   // 31:28 GPIO127 Master CPU Select
};

union GPDCSEL4_REG {
    Uint32  all;
    struct  GPDCSEL4_BITS  bit;
};

struct GPDLOCK_BITS {                   // bits description
    Uint16 GPIO96:1;                    // 0 Configuration Lock bit for this pin
    Uint16 GPIO97:1;                    // 1 Configuration Lock bit for this pin
    Uint16 GPIO98:1;                    // 2 Configuration Lock bit for this pin
    Uint16 GPIO99:1;                    // 3 Configuration Lock bit for this pin
    Uint16 GPIO100:1;                   // 4 Configuration Lock bit for this pin
    Uint16 GPIO101:1;                   // 5 Configuration Lock bit for this pin
    Uint16 GPIO102:1;                   // 6 Configuration Lock bit for this pin
    Uint16 GPIO103:1;                   // 7 Configuration Lock bit for this pin
    Uint16 GPIO104:1;                   // 8 Configuration Lock bit for this pin
    Uint16 GPIO105:1;                   // 9 Configuration Lock bit for this pin
    Uint16 GPIO106:1;                   // 10 Configuration Lock bit for this pin
    Uint16 GPIO107:1;                   // 11 Configuration Lock bit for this pin
    Uint16 GPIO108:1;                   // 12 Configuration Lock bit for this pin
    Uint16 GPIO109:1;                   // 13 Configuration Lock bit for this pin
    Uint16 GPIO110:1;                   // 14 Configuration Lock bit for this pin
    Uint16 GPIO111:1;                   // 15 Configuration Lock bit for this pin
    Uint16 GPIO112:1;                   // 16 Configuration Lock bit for this pin
    Uint16 GPIO113:1;                   // 17 Configuration Lock bit for this pin
    Uint16 GPIO114:1;                   // 18 Configuration Lock bit for this pin
    Uint16 GPIO115:1;                   // 19 Configuration Lock bit for this pin
    Uint16 GPIO116:1;                   // 20 Configuration Lock bit for this pin
    Uint16 GPIO117:1;                   // 21 Configuration Lock bit for this pin
    Uint16 GPIO118:1;                   // 22 Configuration Lock bit for this pin
    Uint16 GPIO119:1;                   // 23 Configuration Lock bit for this pin
    Uint16 GPIO120:1;                   // 24 Configuration Lock bit for this pin
    Uint16 GPIO121:1;                   // 25 Configuration Lock bit for this pin
    Uint16 GPIO122:1;                   // 26 Configuration Lock bit for this pin
    Uint16 GPIO123:1;                   // 27 Configuration Lock bit for this pin
    Uint16 GPIO124:1;                   // 28 Configuration Lock bit for this pin
    Uint16 GPIO125:1;                   // 29 Configuration Lock bit for this pin
    Uint16 GPIO126:1;                   // 30 Configuration Lock bit for this pin
    Uint16 GPIO127:1;                   // 31 Configuration Lock bit for this pin
};

union GPDLOCK_REG {
    Uint32  all;
    struct  GPDLOCK_BITS  bit;
};

struct GPDCR_BITS {                     // bits description
    Uint16 GPIO96:1;                    // 0 Configuration lock commit bit for this pin
    Uint16 GPIO97:1;                    // 1 Configuration lock commit bit for this pin
    Uint16 GPIO98:1;                    // 2 Configuration lock commit bit for this pin
    Uint16 GPIO99:1;                    // 3 Configuration lock commit bit for this pin
    Uint16 GPIO100:1;                   // 4 Configuration lock commit bit for this pin
    Uint16 GPIO101:1;                   // 5 Configuration lock commit bit for this pin
    Uint16 GPIO102:1;                   // 6 Configuration lock commit bit for this pin
    Uint16 GPIO103:1;                   // 7 Configuration lock commit bit for this pin
    Uint16 GPIO104:1;                   // 8 Configuration lock commit bit for this pin
    Uint16 GPIO105:1;                   // 9 Configuration lock commit bit for this pin
    Uint16 GPIO106:1;                   // 10 Configuration lock commit bit for this pin
    Uint16 GPIO107:1;                   // 11 Configuration lock commit bit for this pin
    Uint16 GPIO108:1;                   // 12 Configuration lock commit bit for this pin
    Uint16 GPIO109:1;                   // 13 Configuration lock commit bit for this pin
    Uint16 GPIO110:1;                   // 14 Configuration lock commit bit for this pin
    Uint16 GPIO111:1;                   // 15 Configuration lock commit bit for this pin
    Uint16 GPIO112:1;                   // 16 Configuration lock commit bit for this pin
    Uint16 GPIO113:1;                   // 17 Configuration lock commit bit for this pin
    Uint16 GPIO114:1;                   // 18 Configuration lock commit bit for this pin
    Uint16 GPIO115:1;                   // 19 Configuration lock commit bit for this pin
    Uint16 GPIO116:1;                   // 20 Configuration lock commit bit for this pin
    Uint16 GPIO117:1;                   // 21 Configuration lock commit bit for this pin
    Uint16 GPIO118:1;                   // 22 Configuration lock commit bit for this pin
    Uint16 GPIO119:1;                   // 23 Configuration lock commit bit for this pin
    Uint16 GPIO120:1;                   // 24 Configuration lock commit bit for this pin
    Uint16 GPIO121:1;                   // 25 Configuration lock commit bit for this pin
    Uint16 GPIO122:1;                   // 26 Configuration lock commit bit for this pin
    Uint16 GPIO123:1;                   // 27 Configuration lock commit bit for this pin
    Uint16 GPIO124:1;                   // 28 Configuration lock commit bit for this pin
    Uint16 GPIO125:1;                   // 29 Configuration lock commit bit for this pin
    Uint16 GPIO126:1;                   // 30 Configuration lock commit bit for this pin
    Uint16 GPIO127:1;                   // 31 Configuration lock commit bit for this pin
};

union GPDCR_REG {
    Uint32  all;
    struct  GPDCR_BITS  bit;
};

struct GPECTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO128 to GPIO135
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO136 to GPIO143
    Uint16 QUALPRD2:8;                  // 23:16 Qualification sampling period for GPIO144 to GPIO151
    Uint16 QUALPRD3:8;                  // 31:24 Qualification sampling period for GPIO152 to GPIO159
};

union GPECTRL_REG {
    Uint32  all;
    struct  GPECTRL_BITS  bit;
};

struct GPEQSEL1_BITS {                  // bits description
    Uint16 GPIO128:2;                   // 1:0 Select input qualification type for GPIO128
    Uint16 GPIO129:2;                   // 3:2 Select input qualification type for GPIO129
    Uint16 GPIO130:2;                   // 5:4 Select input qualification type for GPIO130
    Uint16 GPIO131:2;                   // 7:6 Select input qualification type for GPIO131
    Uint16 GPIO132:2;                   // 9:8 Select input qualification type for GPIO132
    Uint16 GPIO133:2;                   // 11:10 Select input qualification type for GPIO133
    Uint16 GPIO134:2;                   // 13:12 Select input qualification type for GPIO134
    Uint16 GPIO135:2;                   // 15:14 Select input qualification type for GPIO135
    Uint16 GPIO136:2;                   // 17:16 Select input qualification type for GPIO136
    Uint16 GPIO137:2;                   // 19:18 Select input qualification type for GPIO137
    Uint16 GPIO138:2;                   // 21:20 Select input qualification type for GPIO138
    Uint16 GPIO139:2;                   // 23:22 Select input qualification type for GPIO139
    Uint16 GPIO140:2;                   // 25:24 Select input qualification type for GPIO140
    Uint16 GPIO141:2;                   // 27:26 Select input qualification type for GPIO141
    Uint16 GPIO142:2;                   // 29:28 Select input qualification type for GPIO142
    Uint16 GPIO143:2;                   // 31:30 Select input qualification type for GPIO143
};

union GPEQSEL1_REG {
    Uint32  all;
    struct  GPEQSEL1_BITS  bit;
};

struct GPEQSEL2_BITS {                  // bits description
    Uint16 GPIO144:2;                   // 1:0 Select input qualification type for GPIO144
    Uint16 GPIO145:2;                   // 3:2 Select input qualification type for GPIO145
    Uint16 GPIO146:2;                   // 5:4 Select input qualification type for GPIO146
    Uint16 GPIO147:2;                   // 7:6 Select input qualification type for GPIO147
    Uint16 GPIO148:2;                   // 9:8 Select input qualification type for GPIO148
    Uint16 GPIO149:2;                   // 11:10 Select input qualification type for GPIO149
    Uint16 GPIO150:2;                   // 13:12 Select input qualification type for GPIO150
    Uint16 GPIO151:2;                   // 15:14 Select input qualification type for GPIO151
    Uint16 GPIO152:2;                   // 17:16 Select input qualification type for GPIO152
    Uint16 GPIO153:2;                   // 19:18 Select input qualification type for GPIO153
    Uint16 GPIO154:2;                   // 21:20 Select input qualification type for GPIO154
    Uint16 GPIO155:2;                   // 23:22 Select input qualification type for GPIO155
    Uint16 GPIO156:2;                   // 25:24 Select input qualification type for GPIO156
    Uint16 GPIO157:2;                   // 27:26 Select input qualification type for GPIO157
    Uint16 GPIO158:2;                   // 29:28 Select input qualification type for GPIO158
    Uint16 GPIO159:2;                   // 31:30 Select input qualification type for GPIO159
};

union GPEQSEL2_REG {
    Uint32  all;
    struct  GPEQSEL2_BITS  bit;
};

struct GPEMUX1_BITS {                   // bits description
    Uint16 GPIO128:2;                   // 1:0 Defines pin-muxing selection for GPIO128
    Uint16 GPIO129:2;                   // 3:2 Defines pin-muxing selection for GPIO129
    Uint16 GPIO130:2;                   // 5:4 Defines pin-muxing selection for GPIO130
    Uint16 GPIO131:2;                   // 7:6 Defines pin-muxing selection for GPIO131
    Uint16 GPIO132:2;                   // 9:8 Defines pin-muxing selection for GPIO132
    Uint16 GPIO133:2;                   // 11:10 Defines pin-muxing selection for GPIO133
    Uint16 GPIO134:2;                   // 13:12 Defines pin-muxing selection for GPIO134
    Uint16 GPIO135:2;                   // 15:14 Defines pin-muxing selection for GPIO135
    Uint16 GPIO136:2;                   // 17:16 Defines pin-muxing selection for GPIO136
    Uint16 GPIO137:2;                   // 19:18 Defines pin-muxing selection for GPIO137
    Uint16 GPIO138:2;                   // 21:20 Defines pin-muxing selection for GPIO138
    Uint16 GPIO139:2;                   // 23:22 Defines pin-muxing selection for GPIO139
    Uint16 GPIO140:2;                   // 25:24 Defines pin-muxing selection for GPIO140
    Uint16 GPIO141:2;                   // 27:26 Defines pin-muxing selection for GPIO141
    Uint16 GPIO142:2;                   // 29:28 Defines pin-muxing selection for GPIO142
    Uint16 GPIO143:2;                   // 31:30 Defines pin-muxing selection for GPIO143
};

union GPEMUX1_REG {
    Uint32  all;
    struct  GPEMUX1_BITS  bit;
};

struct GPEMUX2_BITS {                   // bits description
    Uint16 GPIO144:2;                   // 1:0 Defines pin-muxing selection for GPIO144
    Uint16 GPIO145:2;                   // 3:2 Defines pin-muxing selection for GPIO145
    Uint16 GPIO146:2;                   // 5:4 Defines pin-muxing selection for GPIO146
    Uint16 GPIO147:2;                   // 7:6 Defines pin-muxing selection for GPIO147
    Uint16 GPIO148:2;                   // 9:8 Defines pin-muxing selection for GPIO148
    Uint16 GPIO149:2;                   // 11:10 Defines pin-muxing selection for GPIO149
    Uint16 GPIO150:2;                   // 13:12 Defines pin-muxing selection for GPIO150
    Uint16 GPIO151:2;                   // 15:14 Defines pin-muxing selection for GPIO151
    Uint16 GPIO152:2;                   // 17:16 Defines pin-muxing selection for GPIO152
    Uint16 GPIO153:2;                   // 19:18 Defines pin-muxing selection for GPIO153
    Uint16 GPIO154:2;                   // 21:20 Defines pin-muxing selection for GPIO154
    Uint16 GPIO155:2;                   // 23:22 Defines pin-muxing selection for GPIO155
    Uint16 GPIO156:2;                   // 25:24 Defines pin-muxing selection for GPIO156
    Uint16 GPIO157:2;                   // 27:26 Defines pin-muxing selection for GPIO157
    Uint16 GPIO158:2;                   // 29:28 Defines pin-muxing selection for GPIO158
    Uint16 GPIO159:2;                   // 31:30 Defines pin-muxing selection for GPIO159
};

union GPEMUX2_REG {
    Uint32  all;
    struct  GPEMUX2_BITS  bit;
};

struct GPEDIR_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO129:1;                   // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO130:1;                   // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO131:1;                   // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO132:1;                   // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO133:1;                   // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO134:1;                   // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO135:1;                   // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO136:1;                   // 8 Defines direction for this pin in GPIO mode
    Uint16 GPIO137:1;                   // 9 Defines direction for this pin in GPIO mode
    Uint16 GPIO138:1;                   // 10 Defines direction for this pin in GPIO mode
    Uint16 GPIO139:1;                   // 11 Defines direction for this pin in GPIO mode
    Uint16 GPIO140:1;                   // 12 Defines direction for this pin in GPIO mode
    Uint16 GPIO141:1;                   // 13 Defines direction for this pin in GPIO mode
    Uint16 GPIO142:1;                   // 14 Defines direction for this pin in GPIO mode
    Uint16 GPIO143:1;                   // 15 Defines direction for this pin in GPIO mode
    Uint16 GPIO144:1;                   // 16 Defines direction for this pin in GPIO mode
    Uint16 GPIO145:1;                   // 17 Defines direction for this pin in GPIO mode
    Uint16 GPIO146:1;                   // 18 Defines direction for this pin in GPIO mode
    Uint16 GPIO147:1;                   // 19 Defines direction for this pin in GPIO mode
    Uint16 GPIO148:1;                   // 20 Defines direction for this pin in GPIO mode
    Uint16 GPIO149:1;                   // 21 Defines direction for this pin in GPIO mode
    Uint16 GPIO150:1;                   // 22 Defines direction for this pin in GPIO mode
    Uint16 GPIO151:1;                   // 23 Defines direction for this pin in GPIO mode
    Uint16 GPIO152:1;                   // 24 Defines direction for this pin in GPIO mode
    Uint16 GPIO153:1;                   // 25 Defines direction for this pin in GPIO mode
    Uint16 GPIO154:1;                   // 26 Defines direction for this pin in GPIO mode
    Uint16 GPIO155:1;                   // 27 Defines direction for this pin in GPIO mode
    Uint16 GPIO156:1;                   // 28 Defines direction for this pin in GPIO mode
    Uint16 GPIO157:1;                   // 29 Defines direction for this pin in GPIO mode
    Uint16 GPIO158:1;                   // 30 Defines direction for this pin in GPIO mode
    Uint16 GPIO159:1;                   // 31 Defines direction for this pin in GPIO mode
};

union GPEDIR_REG {
    Uint32  all;
    struct  GPEDIR_BITS  bit;
};

struct GPEPUD_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Pull-Up Disable control for this pin
    Uint16 GPIO129:1;                   // 1 Pull-Up Disable control for this pin
    Uint16 GPIO130:1;                   // 2 Pull-Up Disable control for this pin
    Uint16 GPIO131:1;                   // 3 Pull-Up Disable control for this pin
    Uint16 GPIO132:1;                   // 4 Pull-Up Disable control for this pin
    Uint16 GPIO133:1;                   // 5 Pull-Up Disable control for this pin
    Uint16 GPIO134:1;                   // 6 Pull-Up Disable control for this pin
    Uint16 GPIO135:1;                   // 7 Pull-Up Disable control for this pin
    Uint16 GPIO136:1;                   // 8 Pull-Up Disable control for this pin
    Uint16 GPIO137:1;                   // 9 Pull-Up Disable control for this pin
    Uint16 GPIO138:1;                   // 10 Pull-Up Disable control for this pin
    Uint16 GPIO139:1;                   // 11 Pull-Up Disable control for this pin
    Uint16 GPIO140:1;                   // 12 Pull-Up Disable control for this pin
    Uint16 GPIO141:1;                   // 13 Pull-Up Disable control for this pin
    Uint16 GPIO142:1;                   // 14 Pull-Up Disable control for this pin
    Uint16 GPIO143:1;                   // 15 Pull-Up Disable control for this pin
    Uint16 GPIO144:1;                   // 16 Pull-Up Disable control for this pin
    Uint16 GPIO145:1;                   // 17 Pull-Up Disable control for this pin
    Uint16 GPIO146:1;                   // 18 Pull-Up Disable control for this pin
    Uint16 GPIO147:1;                   // 19 Pull-Up Disable control for this pin
    Uint16 GPIO148:1;                   // 20 Pull-Up Disable control for this pin
    Uint16 GPIO149:1;                   // 21 Pull-Up Disable control for this pin
    Uint16 GPIO150:1;                   // 22 Pull-Up Disable control for this pin
    Uint16 GPIO151:1;                   // 23 Pull-Up Disable control for this pin
    Uint16 GPIO152:1;                   // 24 Pull-Up Disable control for this pin
    Uint16 GPIO153:1;                   // 25 Pull-Up Disable control for this pin
    Uint16 GPIO154:1;                   // 26 Pull-Up Disable control for this pin
    Uint16 GPIO155:1;                   // 27 Pull-Up Disable control for this pin
    Uint16 GPIO156:1;                   // 28 Pull-Up Disable control for this pin
    Uint16 GPIO157:1;                   // 29 Pull-Up Disable control for this pin
    Uint16 GPIO158:1;                   // 30 Pull-Up Disable control for this pin
    Uint16 GPIO159:1;                   // 31 Pull-Up Disable control for this pin
};

union GPEPUD_REG {
    Uint32  all;
    struct  GPEPUD_BITS  bit;
};

struct GPEINV_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Input inversion control for this pin
    Uint16 GPIO129:1;                   // 1 Input inversion control for this pin
    Uint16 GPIO130:1;                   // 2 Input inversion control for this pin
    Uint16 GPIO131:1;                   // 3 Input inversion control for this pin
    Uint16 GPIO132:1;                   // 4 Input inversion control for this pin
    Uint16 GPIO133:1;                   // 5 Input inversion control for this pin
    Uint16 GPIO134:1;                   // 6 Input inversion control for this pin
    Uint16 GPIO135:1;                   // 7 Input inversion control for this pin
    Uint16 GPIO136:1;                   // 8 Input inversion control for this pin
    Uint16 GPIO137:1;                   // 9 Input inversion control for this pin
    Uint16 GPIO138:1;                   // 10 Input inversion control for this pin
    Uint16 GPIO139:1;                   // 11 Input inversion control for this pin
    Uint16 GPIO140:1;                   // 12 Input inversion control for this pin
    Uint16 GPIO141:1;                   // 13 Input inversion control for this pin
    Uint16 GPIO142:1;                   // 14 Input inversion control for this pin
    Uint16 GPIO143:1;                   // 15 Input inversion control for this pin
    Uint16 GPIO144:1;                   // 16 Input inversion control for this pin
    Uint16 GPIO145:1;                   // 17 Input inversion control for this pin
    Uint16 GPIO146:1;                   // 18 Input inversion control for this pin
    Uint16 GPIO147:1;                   // 19 Input inversion control for this pin
    Uint16 GPIO148:1;                   // 20 Input inversion control for this pin
    Uint16 GPIO149:1;                   // 21 Input inversion control for this pin
    Uint16 GPIO150:1;                   // 22 Input inversion control for this pin
    Uint16 GPIO151:1;                   // 23 Input inversion control for this pin
    Uint16 GPIO152:1;                   // 24 Input inversion control for this pin
    Uint16 GPIO153:1;                   // 25 Input inversion control for this pin
    Uint16 GPIO154:1;                   // 26 Input inversion control for this pin
    Uint16 GPIO155:1;                   // 27 Input inversion control for this pin
    Uint16 GPIO156:1;                   // 28 Input inversion control for this pin
    Uint16 GPIO157:1;                   // 29 Input inversion control for this pin
    Uint16 GPIO158:1;                   // 30 Input inversion control for this pin
    Uint16 GPIO159:1;                   // 31 Input inversion control for this pin
};

union GPEINV_REG {
    Uint32  all;
    struct  GPEINV_BITS  bit;
};

struct GPEODR_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO129:1;                   // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO130:1;                   // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO131:1;                   // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO132:1;                   // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO133:1;                   // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO134:1;                   // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO135:1;                   // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO136:1;                   // 8 Outpout Open-Drain control for this pin
    Uint16 GPIO137:1;                   // 9 Outpout Open-Drain control for this pin
    Uint16 GPIO138:1;                   // 10 Outpout Open-Drain control for this pin
    Uint16 GPIO139:1;                   // 11 Outpout Open-Drain control for this pin
    Uint16 GPIO140:1;                   // 12 Outpout Open-Drain control for this pin
    Uint16 GPIO141:1;                   // 13 Outpout Open-Drain control for this pin
    Uint16 GPIO142:1;                   // 14 Outpout Open-Drain control for this pin
    Uint16 GPIO143:1;                   // 15 Outpout Open-Drain control for this pin
    Uint16 GPIO144:1;                   // 16 Outpout Open-Drain control for this pin
    Uint16 GPIO145:1;                   // 17 Outpout Open-Drain control for this pin
    Uint16 GPIO146:1;                   // 18 Outpout Open-Drain control for this pin
    Uint16 GPIO147:1;                   // 19 Outpout Open-Drain control for this pin
    Uint16 GPIO148:1;                   // 20 Outpout Open-Drain control for this pin
    Uint16 GPIO149:1;                   // 21 Outpout Open-Drain control for this pin
    Uint16 GPIO150:1;                   // 22 Outpout Open-Drain control for this pin
    Uint16 GPIO151:1;                   // 23 Outpout Open-Drain control for this pin
    Uint16 GPIO152:1;                   // 24 Outpout Open-Drain control for this pin
    Uint16 GPIO153:1;                   // 25 Outpout Open-Drain control for this pin
    Uint16 GPIO154:1;                   // 26 Outpout Open-Drain control for this pin
    Uint16 GPIO155:1;                   // 27 Outpout Open-Drain control for this pin
    Uint16 GPIO156:1;                   // 28 Outpout Open-Drain control for this pin
    Uint16 GPIO157:1;                   // 29 Outpout Open-Drain control for this pin
    Uint16 GPIO158:1;                   // 30 Outpout Open-Drain control for this pin
    Uint16 GPIO159:1;                   // 31 Outpout Open-Drain control for this pin
};

union GPEODR_REG {
    Uint32  all;
    struct  GPEODR_BITS  bit;
};

struct GPEGMUX1_BITS {                  // bits description
    Uint16 GPIO128:2;                   // 1:0 Defines pin-muxing selection for GPIO128
    Uint16 GPIO129:2;                   // 3:2 Defines pin-muxing selection for GPIO129
    Uint16 GPIO130:2;                   // 5:4 Defines pin-muxing selection for GPIO130
    Uint16 GPIO131:2;                   // 7:6 Defines pin-muxing selection for GPIO131
    Uint16 GPIO132:2;                   // 9:8 Defines pin-muxing selection for GPIO132
    Uint16 GPIO133:2;                   // 11:10 Defines pin-muxing selection for GPIO133
    Uint16 GPIO134:2;                   // 13:12 Defines pin-muxing selection for GPIO134
    Uint16 GPIO135:2;                   // 15:14 Defines pin-muxing selection for GPIO135
    Uint16 GPIO136:2;                   // 17:16 Defines pin-muxing selection for GPIO136
    Uint16 GPIO137:2;                   // 19:18 Defines pin-muxing selection for GPIO137
    Uint16 GPIO138:2;                   // 21:20 Defines pin-muxing selection for GPIO138
    Uint16 GPIO139:2;                   // 23:22 Defines pin-muxing selection for GPIO139
    Uint16 GPIO140:2;                   // 25:24 Defines pin-muxing selection for GPIO140
    Uint16 GPIO141:2;                   // 27:26 Defines pin-muxing selection for GPIO141
    Uint16 GPIO142:2;                   // 29:28 Defines pin-muxing selection for GPIO142
    Uint16 GPIO143:2;                   // 31:30 Defines pin-muxing selection for GPIO143
};

union GPEGMUX1_REG {
    Uint32  all;
    struct  GPEGMUX1_BITS  bit;
};

struct GPEGMUX2_BITS {                  // bits description
    Uint16 GPIO144:2;                   // 1:0 Defines pin-muxing selection for GPIO144
    Uint16 GPIO145:2;                   // 3:2 Defines pin-muxing selection for GPIO145
    Uint16 GPIO146:2;                   // 5:4 Defines pin-muxing selection for GPIO146
    Uint16 GPIO147:2;                   // 7:6 Defines pin-muxing selection for GPIO147
    Uint16 GPIO148:2;                   // 9:8 Defines pin-muxing selection for GPIO148
    Uint16 GPIO149:2;                   // 11:10 Defines pin-muxing selection for GPIO149
    Uint16 GPIO150:2;                   // 13:12 Defines pin-muxing selection for GPIO150
    Uint16 GPIO151:2;                   // 15:14 Defines pin-muxing selection for GPIO151
    Uint16 GPIO152:2;                   // 17:16 Defines pin-muxing selection for GPIO152
    Uint16 GPIO153:2;                   // 19:18 Defines pin-muxing selection for GPIO153
    Uint16 GPIO154:2;                   // 21:20 Defines pin-muxing selection for GPIO154
    Uint16 GPIO155:2;                   // 23:22 Defines pin-muxing selection for GPIO155
    Uint16 GPIO156:2;                   // 25:24 Defines pin-muxing selection for GPIO156
    Uint16 GPIO157:2;                   // 27:26 Defines pin-muxing selection for GPIO157
    Uint16 GPIO158:2;                   // 29:28 Defines pin-muxing selection for GPIO158
    Uint16 GPIO159:2;                   // 31:30 Defines pin-muxing selection for GPIO159
};

union GPEGMUX2_REG {
    Uint32  all;
    struct  GPEGMUX2_BITS  bit;
};

struct GPECSEL1_BITS {                  // bits description
    Uint16 GPIO128:4;                   // 3:0 GPIO128 Master CPU Select
    Uint16 GPIO129:4;                   // 7:4 GPIO129 Master CPU Select
    Uint16 GPIO130:4;                   // 11:8 GPIO130 Master CPU Select
    Uint16 GPIO131:4;                   // 15:12 GPIO131 Master CPU Select
    Uint16 GPIO132:4;                   // 19:16 GPIO132 Master CPU Select
    Uint16 GPIO133:4;                   // 23:20 GPIO133 Master CPU Select
    Uint16 GPIO134:4;                   // 27:24 GPIO134 Master CPU Select
    Uint16 GPIO135:4;                   // 31:28 GPIO135 Master CPU Select
};

union GPECSEL1_REG {
    Uint32  all;
    struct  GPECSEL1_BITS  bit;
};

struct GPECSEL2_BITS {                  // bits description
    Uint16 GPIO136:4;                   // 3:0 GPIO136 Master CPU Select
    Uint16 GPIO137:4;                   // 7:4 GPIO137 Master CPU Select
    Uint16 GPIO138:4;                   // 11:8 GPIO138 Master CPU Select
    Uint16 GPIO139:4;                   // 15:12 GPIO139 Master CPU Select
    Uint16 GPIO140:4;                   // 19:16 GPIO140 Master CPU Select
    Uint16 GPIO141:4;                   // 23:20 GPIO141 Master CPU Select
    Uint16 GPIO142:4;                   // 27:24 GPIO142 Master CPU Select
    Uint16 GPIO143:4;                   // 31:28 GPIO143 Master CPU Select
};

union GPECSEL2_REG {
    Uint32  all;
    struct  GPECSEL2_BITS  bit;
};

struct GPECSEL3_BITS {                  // bits description
    Uint16 GPIO144:4;                   // 3:0 GPIO144 Master CPU Select
    Uint16 GPIO145:4;                   // 7:4 GPIO145 Master CPU Select
    Uint16 GPIO146:4;                   // 11:8 GPIO146 Master CPU Select
    Uint16 GPIO147:4;                   // 15:12 GPIO147 Master CPU Select
    Uint16 GPIO148:4;                   // 19:16 GPIO148 Master CPU Select
    Uint16 GPIO149:4;                   // 23:20 GPIO149 Master CPU Select
    Uint16 GPIO150:4;                   // 27:24 GPIO150 Master CPU Select
    Uint16 GPIO151:4;                   // 31:28 GPIO151 Master CPU Select
};

union GPECSEL3_REG {
    Uint32  all;
    struct  GPECSEL3_BITS  bit;
};

struct GPECSEL4_BITS {                  // bits description
    Uint16 GPIO152:4;                   // 3:0 GPIO152 Master CPU Select
    Uint16 GPIO153:4;                   // 7:4 GPIO153 Master CPU Select
    Uint16 GPIO154:4;                   // 11:8 GPIO154 Master CPU Select
    Uint16 GPIO155:4;                   // 15:12 GPIO155 Master CPU Select
    Uint16 GPIO156:4;                   // 19:16 GPIO156 Master CPU Select
    Uint16 GPIO157:4;                   // 23:20 GPIO157 Master CPU Select
    Uint16 GPIO158:4;                   // 27:24 GPIO158 Master CPU Select
    Uint16 GPIO159:4;                   // 31:28 GPIO159 Master CPU Select
};

union GPECSEL4_REG {
    Uint32  all;
    struct  GPECSEL4_BITS  bit;
};

struct GPELOCK_BITS {                   // bits description
    Uint16 GPIO128:1;                   // 0 Configuration Lock bit for this pin
    Uint16 GPIO129:1;                   // 1 Configuration Lock bit for this pin
    Uint16 GPIO130:1;                   // 2 Configuration Lock bit for this pin
    Uint16 GPIO131:1;                   // 3 Configuration Lock bit for this pin
    Uint16 GPIO132:1;                   // 4 Configuration Lock bit for this pin
    Uint16 GPIO133:1;                   // 5 Configuration Lock bit for this pin
    Uint16 GPIO134:1;                   // 6 Configuration Lock bit for this pin
    Uint16 GPIO135:1;                   // 7 Configuration Lock bit for this pin
    Uint16 GPIO136:1;                   // 8 Configuration Lock bit for this pin
    Uint16 GPIO137:1;                   // 9 Configuration Lock bit for this pin
    Uint16 GPIO138:1;                   // 10 Configuration Lock bit for this pin
    Uint16 GPIO139:1;                   // 11 Configuration Lock bit for this pin
    Uint16 GPIO140:1;                   // 12 Configuration Lock bit for this pin
    Uint16 GPIO141:1;                   // 13 Configuration Lock bit for this pin
    Uint16 GPIO142:1;                   // 14 Configuration Lock bit for this pin
    Uint16 GPIO143:1;                   // 15 Configuration Lock bit for this pin
    Uint16 GPIO144:1;                   // 16 Configuration Lock bit for this pin
    Uint16 GPIO145:1;                   // 17 Configuration Lock bit for this pin
    Uint16 GPIO146:1;                   // 18 Configuration Lock bit for this pin
    Uint16 GPIO147:1;                   // 19 Configuration Lock bit for this pin
    Uint16 GPIO148:1;                   // 20 Configuration Lock bit for this pin
    Uint16 GPIO149:1;                   // 21 Configuration Lock bit for this pin
    Uint16 GPIO150:1;                   // 22 Configuration Lock bit for this pin
    Uint16 GPIO151:1;                   // 23 Configuration Lock bit for this pin
    Uint16 GPIO152:1;                   // 24 Configuration Lock bit for this pin
    Uint16 GPIO153:1;                   // 25 Configuration Lock bit for this pin
    Uint16 GPIO154:1;                   // 26 Configuration Lock bit for this pin
    Uint16 GPIO155:1;                   // 27 Configuration Lock bit for this pin
    Uint16 GPIO156:1;                   // 28 Configuration Lock bit for this pin
    Uint16 GPIO157:1;                   // 29 Configuration Lock bit for this pin
    Uint16 GPIO158:1;                   // 30 Configuration Lock bit for this pin
    Uint16 GPIO159:1;                   // 31 Configuration Lock bit for this pin
};

union GPELOCK_REG {
    Uint32  all;
    struct  GPELOCK_BITS  bit;
};

struct GPECR_BITS {                     // bits description
    Uint16 GPIO128:1;                   // 0 Configuration lock commit bit for this pin
    Uint16 GPIO129:1;                   // 1 Configuration lock commit bit for this pin
    Uint16 GPIO130:1;                   // 2 Configuration lock commit bit for this pin
    Uint16 GPIO131:1;                   // 3 Configuration lock commit bit for this pin
    Uint16 GPIO132:1;                   // 4 Configuration lock commit bit for this pin
    Uint16 GPIO133:1;                   // 5 Configuration lock commit bit for this pin
    Uint16 GPIO134:1;                   // 6 Configuration lock commit bit for this pin
    Uint16 GPIO135:1;                   // 7 Configuration lock commit bit for this pin
    Uint16 GPIO136:1;                   // 8 Configuration lock commit bit for this pin
    Uint16 GPIO137:1;                   // 9 Configuration lock commit bit for this pin
    Uint16 GPIO138:1;                   // 10 Configuration lock commit bit for this pin
    Uint16 GPIO139:1;                   // 11 Configuration lock commit bit for this pin
    Uint16 GPIO140:1;                   // 12 Configuration lock commit bit for this pin
    Uint16 GPIO141:1;                   // 13 Configuration lock commit bit for this pin
    Uint16 GPIO142:1;                   // 14 Configuration lock commit bit for this pin
    Uint16 GPIO143:1;                   // 15 Configuration lock commit bit for this pin
    Uint16 GPIO144:1;                   // 16 Configuration lock commit bit for this pin
    Uint16 GPIO145:1;                   // 17 Configuration lock commit bit for this pin
    Uint16 GPIO146:1;                   // 18 Configuration lock commit bit for this pin
    Uint16 GPIO147:1;                   // 19 Configuration lock commit bit for this pin
    Uint16 GPIO148:1;                   // 20 Configuration lock commit bit for this pin
    Uint16 GPIO149:1;                   // 21 Configuration lock commit bit for this pin
    Uint16 GPIO150:1;                   // 22 Configuration lock commit bit for this pin
    Uint16 GPIO151:1;                   // 23 Configuration lock commit bit for this pin
    Uint16 GPIO152:1;                   // 24 Configuration lock commit bit for this pin
    Uint16 GPIO153:1;                   // 25 Configuration lock commit bit for this pin
    Uint16 GPIO154:1;                   // 26 Configuration lock commit bit for this pin
    Uint16 GPIO155:1;                   // 27 Configuration lock commit bit for this pin
    Uint16 GPIO156:1;                   // 28 Configuration lock commit bit for this pin
    Uint16 GPIO157:1;                   // 29 Configuration lock commit bit for this pin
    Uint16 GPIO158:1;                   // 30 Configuration lock commit bit for this pin
    Uint16 GPIO159:1;                   // 31 Configuration lock commit bit for this pin
};

union GPECR_REG {
    Uint32  all;
    struct  GPECR_BITS  bit;
};

struct GPFCTRL_BITS {                   // bits description
    Uint16 QUALPRD0:8;                  // 7:0 Qualification sampling period for GPIO160 to GPIO167
    Uint16 QUALPRD1:8;                  // 15:8 Qualification sampling period for GPIO168
    Uint16 rsvd1:8;                     // 23:16 Reserved
    Uint16 rsvd2:8;                     // 31:24 Reserved
};

union GPFCTRL_REG {
    Uint32  all;
    struct  GPFCTRL_BITS  bit;
};

struct GPFQSEL1_BITS {                  // bits description
    Uint16 GPIO160:2;                   // 1:0 Select input qualification type for GPIO160
    Uint16 GPIO161:2;                   // 3:2 Select input qualification type for GPIO161
    Uint16 GPIO162:2;                   // 5:4 Select input qualification type for GPIO162
    Uint16 GPIO163:2;                   // 7:6 Select input qualification type for GPIO163
    Uint16 GPIO164:2;                   // 9:8 Select input qualification type for GPIO164
    Uint16 GPIO165:2;                   // 11:10 Select input qualification type for GPIO165
    Uint16 GPIO166:2;                   // 13:12 Select input qualification type for GPIO166
    Uint16 GPIO167:2;                   // 15:14 Select input qualification type for GPIO167
    Uint16 GPIO168:2;                   // 17:16 Select input qualification type for GPIO168
    Uint16 rsvd1:2;                     // 19:18 Reserved
    Uint16 rsvd2:2;                     // 21:20 Reserved
    Uint16 rsvd3:2;                     // 23:22 Reserved
    Uint16 rsvd4:2;                     // 25:24 Reserved
    Uint16 rsvd5:2;                     // 27:26 Reserved
    Uint16 rsvd6:2;                     // 29:28 Reserved
    Uint16 rsvd7:2;                     // 31:30 Reserved
};

union GPFQSEL1_REG {
    Uint32  all;
    struct  GPFQSEL1_BITS  bit;
};

struct GPFMUX1_BITS {                   // bits description
    Uint16 GPIO160:2;                   // 1:0 Defines pin-muxing selection for GPIO160
    Uint16 GPIO161:2;                   // 3:2 Defines pin-muxing selection for GPIO161
    Uint16 GPIO162:2;                   // 5:4 Defines pin-muxing selection for GPIO162
    Uint16 GPIO163:2;                   // 7:6 Defines pin-muxing selection for GPIO163
    Uint16 GPIO164:2;                   // 9:8 Defines pin-muxing selection for GPIO164
    Uint16 GPIO165:2;                   // 11:10 Defines pin-muxing selection for GPIO165
    Uint16 GPIO166:2;                   // 13:12 Defines pin-muxing selection for GPIO166
    Uint16 GPIO167:2;                   // 15:14 Defines pin-muxing selection for GPIO167
    Uint16 GPIO168:2;                   // 17:16 Defines pin-muxing selection for GPIO168
    Uint16 rsvd1:2;                     // 19:18 Reserved
    Uint16 rsvd2:2;                     // 21:20 Reserved
    Uint16 rsvd3:2;                     // 23:22 Reserved
    Uint16 rsvd4:2;                     // 25:24 Reserved
    Uint16 rsvd5:2;                     // 27:26 Reserved
    Uint16 rsvd6:2;                     // 29:28 Reserved
    Uint16 rsvd7:2;                     // 31:30 Reserved
};

union GPFMUX1_REG {
    Uint32  all;
    struct  GPFMUX1_BITS  bit;
};

struct GPFDIR_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Defines direction for this pin in GPIO mode
    Uint16 GPIO161:1;                   // 1 Defines direction for this pin in GPIO mode
    Uint16 GPIO162:1;                   // 2 Defines direction for this pin in GPIO mode
    Uint16 GPIO163:1;                   // 3 Defines direction for this pin in GPIO mode
    Uint16 GPIO164:1;                   // 4 Defines direction for this pin in GPIO mode
    Uint16 GPIO165:1;                   // 5 Defines direction for this pin in GPIO mode
    Uint16 GPIO166:1;                   // 6 Defines direction for this pin in GPIO mode
    Uint16 GPIO167:1;                   // 7 Defines direction for this pin in GPIO mode
    Uint16 GPIO168:1;                   // 8 Defines direction for this pin in GPIO mode
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFDIR_REG {
    Uint32  all;
    struct  GPFDIR_BITS  bit;
};

struct GPFPUD_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Pull-Up Disable control for this pin
    Uint16 GPIO161:1;                   // 1 Pull-Up Disable control for this pin
    Uint16 GPIO162:1;                   // 2 Pull-Up Disable control for this pin
    Uint16 GPIO163:1;                   // 3 Pull-Up Disable control for this pin
    Uint16 GPIO164:1;                   // 4 Pull-Up Disable control for this pin
    Uint16 GPIO165:1;                   // 5 Pull-Up Disable control for this pin
    Uint16 GPIO166:1;                   // 6 Pull-Up Disable control for this pin
    Uint16 GPIO167:1;                   // 7 Pull-Up Disable control for this pin
    Uint16 GPIO168:1;                   // 8 Pull-Up Disable control for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFPUD_REG {
    Uint32  all;
    struct  GPFPUD_BITS  bit;
};

struct GPFINV_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Input inversion control for this pin
    Uint16 GPIO161:1;                   // 1 Input inversion control for this pin
    Uint16 GPIO162:1;                   // 2 Input inversion control for this pin
    Uint16 GPIO163:1;                   // 3 Input inversion control for this pin
    Uint16 GPIO164:1;                   // 4 Input inversion control for this pin
    Uint16 GPIO165:1;                   // 5 Input inversion control for this pin
    Uint16 GPIO166:1;                   // 6 Input inversion control for this pin
    Uint16 GPIO167:1;                   // 7 Input inversion control for this pin
    Uint16 GPIO168:1;                   // 8 Input inversion control for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFINV_REG {
    Uint32  all;
    struct  GPFINV_BITS  bit;
};

struct GPFODR_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Outpout Open-Drain control for this pin
    Uint16 GPIO161:1;                   // 1 Outpout Open-Drain control for this pin
    Uint16 GPIO162:1;                   // 2 Outpout Open-Drain control for this pin
    Uint16 GPIO163:1;                   // 3 Outpout Open-Drain control for this pin
    Uint16 GPIO164:1;                   // 4 Outpout Open-Drain control for this pin
    Uint16 GPIO165:1;                   // 5 Outpout Open-Drain control for this pin
    Uint16 GPIO166:1;                   // 6 Outpout Open-Drain control for this pin
    Uint16 GPIO167:1;                   // 7 Outpout Open-Drain control for this pin
    Uint16 GPIO168:1;                   // 8 Outpout Open-Drain control for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFODR_REG {
    Uint32  all;
    struct  GPFODR_BITS  bit;
};

struct GPFGMUX1_BITS {                  // bits description
    Uint16 GPIO160:2;                   // 1:0 Defines pin-muxing selection for GPIO160
    Uint16 GPIO161:2;                   // 3:2 Defines pin-muxing selection for GPIO161
    Uint16 GPIO162:2;                   // 5:4 Defines pin-muxing selection for GPIO162
    Uint16 GPIO163:2;                   // 7:6 Defines pin-muxing selection for GPIO163
    Uint16 GPIO164:2;                   // 9:8 Defines pin-muxing selection for GPIO164
    Uint16 GPIO165:2;                   // 11:10 Defines pin-muxing selection for GPIO165
    Uint16 GPIO166:2;                   // 13:12 Defines pin-muxing selection for GPIO166
    Uint16 GPIO167:2;                   // 15:14 Defines pin-muxing selection for GPIO167
    Uint16 GPIO168:2;                   // 17:16 Defines pin-muxing selection for GPIO168
    Uint16 rsvd1:2;                     // 19:18 Reserved
    Uint16 rsvd2:2;                     // 21:20 Reserved
    Uint16 rsvd3:2;                     // 23:22 Reserved
    Uint16 rsvd4:2;                     // 25:24 Reserved
    Uint16 rsvd5:2;                     // 27:26 Reserved
    Uint16 rsvd6:2;                     // 29:28 Reserved
    Uint16 rsvd7:2;                     // 31:30 Reserved
};

union GPFGMUX1_REG {
    Uint32  all;
    struct  GPFGMUX1_BITS  bit;
};

struct GPFCSEL1_BITS {                  // bits description
    Uint16 GPIO160:4;                   // 3:0 GPIO160 Master CPU Select
    Uint16 GPIO161:4;                   // 7:4 GPIO161 Master CPU Select
    Uint16 GPIO162:4;                   // 11:8 GPIO162 Master CPU Select
    Uint16 GPIO163:4;                   // 15:12 GPIO163 Master CPU Select
    Uint16 GPIO164:4;                   // 19:16 GPIO164 Master CPU Select
    Uint16 GPIO165:4;                   // 23:20 GPIO165 Master CPU Select
    Uint16 GPIO166:4;                   // 27:24 GPIO166 Master CPU Select
    Uint16 GPIO167:4;                   // 31:28 GPIO167 Master CPU Select
};

union GPFCSEL1_REG {
    Uint32  all;
    struct  GPFCSEL1_BITS  bit;
};

struct GPFCSEL2_BITS {                  // bits description
    Uint16 GPIO168:4;                   // 3:0 GPIO168 Master CPU Select
    Uint16 rsvd1:4;                     // 7:4 Reserved
    Uint16 rsvd2:4;                     // 11:8 Reserved
    Uint16 rsvd3:4;                     // 15:12 Reserved
    Uint16 rsvd4:4;                     // 19:16 Reserved
    Uint16 rsvd5:4;                     // 23:20 Reserved
    Uint16 rsvd6:4;                     // 27:24 Reserved
    Uint16 rsvd7:4;                     // 31:28 Reserved
};

union GPFCSEL2_REG {
    Uint32  all;
    struct  GPFCSEL2_BITS  bit;
};

struct GPFLOCK_BITS {                   // bits description
    Uint16 GPIO160:1;                   // 0 Configuration Lock bit for this pin
    Uint16 GPIO161:1;                   // 1 Configuration Lock bit for this pin
    Uint16 GPIO162:1;                   // 2 Configuration Lock bit for this pin
    Uint16 GPIO163:1;                   // 3 Configuration Lock bit for this pin
    Uint16 GPIO164:1;                   // 4 Configuration Lock bit for this pin
    Uint16 GPIO165:1;                   // 5 Configuration Lock bit for this pin
    Uint16 GPIO166:1;                   // 6 Configuration Lock bit for this pin
    Uint16 GPIO167:1;                   // 7 Configuration Lock bit for this pin
    Uint16 GPIO168:1;                   // 8 Configuration Lock bit for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFLOCK_REG {
    Uint32  all;
    struct  GPFLOCK_BITS  bit;
};

struct GPFCR_BITS {                     // bits description
    Uint16 GPIO160:1;                   // 0 Configuration lock commit bit for this pin
    Uint16 GPIO161:1;                   // 1 Configuration lock commit bit for this pin
    Uint16 GPIO162:1;                   // 2 Configuration lock commit bit for this pin
    Uint16 GPIO163:1;                   // 3 Configuration lock commit bit for this pin
    Uint16 GPIO164:1;                   // 4 Configuration lock commit bit for this pin
    Uint16 GPIO165:1;                   // 5 Configuration lock commit bit for this pin
    Uint16 GPIO166:1;                   // 6 Configuration lock commit bit for this pin
    Uint16 GPIO167:1;                   // 7 Configuration lock commit bit for this pin
    Uint16 GPIO168:1;                   // 8 Configuration lock commit bit for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFCR_REG {
    Uint32  all;
    struct  GPFCR_BITS  bit;
};

struct GPIO_CTRL_REGS {
    union   GPACTRL_REG                      GPACTRL;                      // GPIO A Qualification Sampling Period Control (GPIO0 to 31)
    union   GPAQSEL1_REG                     GPAQSEL1;                     // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
    union   GPAQSEL2_REG                     GPAQSEL2;                     // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
    union   GPAMUX1_REG                      GPAMUX1;                      // GPIO A Mux 1 Register (GPIO0 to 15)
    union   GPAMUX2_REG                      GPAMUX2;                      // GPIO A Mux 2 Register (GPIO16 to 31)
    union   GPADIR_REG                       GPADIR;                       // GPIO A Direction Register (GPIO0 to 31)
    union   GPAPUD_REG                       GPAPUD;                       // GPIO A Pull Up Disable Register (GPIO0 to 31) 
    Uint16                                   rsvd1[2];                     // Reserved
    union   GPAINV_REG                       GPAINV;                       // GPIO A Input Polarity Invert Registers (GPIO0 to 31)
    union   GPAODR_REG                       GPAODR;                       // GPIO A Open Drain Output Register (GPIO0 to GPIO31)
    Uint16                                   rsvd2[12];                    // Reserved
    union   GPAGMUX1_REG                     GPAGMUX1;                     // GPIO A Peripheral Group Mux (GPIO0 to 15)
    union   GPAGMUX2_REG                     GPAGMUX2;                     // GPIO A Peripheral Group Mux (GPIO16 to 31)
    Uint16                                   rsvd3[4];                     // Reserved
    union   GPACSEL1_REG                     GPACSEL1;                     // GPIO A Core Select Register (GPIO0 to 7)
    union   GPACSEL2_REG                     GPACSEL2;                     // GPIO A Core Select Register (GPIO8 to 15)
    union   GPACSEL3_REG                     GPACSEL3;                     // GPIO A Core Select Register (GPIO16 to 23)
    union   GPACSEL4_REG                     GPACSEL4;                     // GPIO A Core Select Register (GPIO24 to 31)
    Uint16                                   rsvd4[12];                    // Reserved
    union   GPALOCK_REG                      GPALOCK;                      // GPIO A Lock Configuration Register (GPIO0 to 31)
    union   GPACR_REG                        GPACR;                        // GPIO A Lock Commit Register (GPIO0 to 31)
    union   GPBCTRL_REG                      GPBCTRL;                      // GPIO B Qualification Sampling Period Control (GPIO32 to 63)
    union   GPBQSEL1_REG                     GPBQSEL1;                     // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
    union   GPBQSEL2_REG                     GPBQSEL2;                     // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
    union   GPBMUX1_REG                      GPBMUX1;                      // GPIO B Mux 1 Register (GPIO32 to 47)
    union   GPBMUX2_REG                      GPBMUX2;                      // GPIO B Mux 2 Register (GPIO48 to 63)
    union   GPBDIR_REG                       GPBDIR;                       // GPIO B Direction Register (GPIO32 to 63)
    union   GPBPUD_REG                       GPBPUD;                       // GPIO B Pull Up Disable Register (GPIO32 to 63) 
    Uint16                                   rsvd5[2];                     // Reserved
    union   GPBINV_REG                       GPBINV;                       // GPIO B Input Polarity Invert Registers (GPIO32 to 63)
    union   GPBODR_REG                       GPBODR;                       // GPIO B Open Drain Output Register (GPIO32 to GPIO63)
    union   GPBAMSEL_REG                     GPBAMSEL;                     // GPIO B Analog Mode Select register (GPIO32 to GPIO63)
    Uint16                                   rsvd6[10];                    // Reserved
    union   GPBGMUX1_REG                     GPBGMUX1;                     // GPIO B Peripheral Group Mux (GPIO32 to 47)
    union   GPBGMUX2_REG                     GPBGMUX2;                     // GPIO B Peripheral Group Mux (GPIO48 to 63)
    Uint16                                   rsvd7[4];                     // Reserved
    union   GPBCSEL1_REG                     GPBCSEL1;                     // GPIO B Core Select Register (GPIO32 to 39)
    union   GPBCSEL2_REG                     GPBCSEL2;                     // GPIO B Core Select Register (GPIO40 to 47)
    union   GPBCSEL3_REG                     GPBCSEL3;                     // GPIO B Core Select Register (GPIO48 to 55)
    union   GPBCSEL4_REG                     GPBCSEL4;                     // GPIO B Core Select Register (GPIO56 to 63)
    Uint16                                   rsvd8[12];                    // Reserved
    union   GPBLOCK_REG                      GPBLOCK;                      // GPIO B Lock Configuration Register (GPIO32 to 63)
    union   GPBCR_REG                        GPBCR;                        // GPIO B Lock Commit Register (GPIO32 to 63)
    union   GPCCTRL_REG                      GPCCTRL;                      // GPIO C Qualification Sampling Period Control (GPIO64 to 95)
    union   GPCQSEL1_REG                     GPCQSEL1;                     // GPIO C Qualifier Select 1 Register (GPIO64 to 79)
    union   GPCQSEL2_REG                     GPCQSEL2;                     // GPIO C Qualifier Select 2 Register (GPIO80  to 95)
    union   GPCMUX1_REG                      GPCMUX1;                      // GPIO C Mux 1 Register (GPIO64 to 79)
    union   GPCMUX2_REG                      GPCMUX2;                      // GPIO C Mux 2 Register (GPIO80  to 95)
    union   GPCDIR_REG                       GPCDIR;                       // GPIO C Direction Register (GPIO64 to 95)
    union   GPCPUD_REG                       GPCPUD;                       // GPIO C Pull Up Disable Register (GPIO64 to 95) 
    Uint16                                   rsvd9[2];                     // Reserved
    union   GPCINV_REG                       GPCINV;                       // GPIO C Input Polarity Invert Registers (GPIO64 to 95)
    union   GPCODR_REG                       GPCODR;                       // GPIO C Open Drain Output Register (GPIO64 to GPIO95)
    Uint16                                   rsvd10[12];                   // Reserved
    union   GPCGMUX1_REG                     GPCGMUX1;                     // GPIO C Peripheral Group Mux (GPIO64 to 79)
    union   GPCGMUX2_REG                     GPCGMUX2;                     // GPIO C Peripheral Group Mux (GPIO80  to 95)
    Uint16                                   rsvd11[4];                    // Reserved
    union   GPCCSEL1_REG                     GPCCSEL1;                     // GPIO C Core Select Register (GPIO64 to 71)
    union   GPCCSEL2_REG                     GPCCSEL2;                     // GPIO C Core Select Register (GPIO72 to 79)
    union   GPCCSEL3_REG                     GPCCSEL3;                     // GPIO C Core Select Register (GPIO80  to 87)
    union   GPCCSEL4_REG                     GPCCSEL4;                     // GPIO C Core Select Register (GPIO88 to 95)
    Uint16                                   rsvd12[12];                   // Reserved
    union   GPCLOCK_REG                      GPCLOCK;                      // GPIO C Lock Configuration Register (GPIO64 to 95)
    union   GPCCR_REG                        GPCCR;                        // GPIO C Lock Commit Register (GPIO64 to 95)
    union   GPDCTRL_REG                      GPDCTRL;                      // GPIO D Qualification Sampling Period Control (GPIO96 to 127)
    union   GPDQSEL1_REG                     GPDQSEL1;                     // GPIO D Qualifier Select 1 Register (GPIO96 to 111)
    union   GPDQSEL2_REG                     GPDQSEL2;                     // GPIO D Qualifier Select 2 Register (GPIO112 to 127)
    union   GPDMUX1_REG                      GPDMUX1;                      // GPIO D Mux 1 Register (GPIO96 to 111)
    union   GPDMUX2_REG                      GPDMUX2;                      // GPIO D Mux 2 Register (GPIO112 to 127)
    union   GPDDIR_REG                       GPDDIR;                       // GPIO D Direction Register (GPIO96 to 127)
    union   GPDPUD_REG                       GPDPUD;                       // GPIO D Pull Up Disable Register (GPIO96 to 127) 
    Uint16                                   rsvd13[2];                    // Reserved
    union   GPDINV_REG                       GPDINV;                       // GPIO D Input Polarity Invert Registers (GPIO96 to 127)
    union   GPDODR_REG                       GPDODR;                       // GPIO D Open Drain Output Register (GPIO96 to GPIO127)
    Uint16                                   rsvd14[12];                   // Reserved
    union   GPDGMUX1_REG                     GPDGMUX1;                     // GPIO D Peripheral Group Mux (GPIO96 to 111)
    union   GPDGMUX2_REG                     GPDGMUX2;                     // GPIO D Peripheral Group Mux (GPIO112 to 127)
    Uint16                                   rsvd15[4];                    // Reserved
    union   GPDCSEL1_REG                     GPDCSEL1;                     // GPIO D Core Select Register (GPIO96 to 103)
    union   GPDCSEL2_REG                     GPDCSEL2;                     // GPIO D Core Select Register (GPIO104 to 111)
    union   GPDCSEL3_REG                     GPDCSEL3;                     // GPIO D Core Select Register (GPIO112 to 119)
    union   GPDCSEL4_REG                     GPDCSEL4;                     // GPIO D Core Select Register (GPIO120 to 127)
    Uint16                                   rsvd16[12];                   // Reserved
    union   GPDLOCK_REG                      GPDLOCK;                      // GPIO D Lock Configuration Register (GPIO96 to 127)
    union   GPDCR_REG                        GPDCR;                        // GPIO D Lock Commit Register (GPIO96 to 127)
    union   GPECTRL_REG                      GPECTRL;                      // GPIO E Qualification Sampling Period Control (GPIO128 to 159)
    union   GPEQSEL1_REG                     GPEQSEL1;                     // GPIO E Qualifier Select 1 Register (GPIO128 to 143)
    union   GPEQSEL2_REG                     GPEQSEL2;                     // GPIO E Qualifier Select 2 Register (GPIO144  to 159)
    union   GPEMUX1_REG                      GPEMUX1;                      // GPIO E Mux 1 Register (GPIO128 to 143)
    union   GPEMUX2_REG                      GPEMUX2;                      // GPIO E Mux 2 Register (GPIO144  to 159)
    union   GPEDIR_REG                       GPEDIR;                       // GPIO E Direction Register (GPIO128 to 159)
    union   GPEPUD_REG                       GPEPUD;                       // GPIO E Pull Up Disable Register (GPIO128 to 159) 
    Uint16                                   rsvd17[2];                    // Reserved
    union   GPEINV_REG                       GPEINV;                       // GPIO E Input Polarity Invert Registers (GPIO128 to 159)
    union   GPEODR_REG                       GPEODR;                       // GPIO E Open Drain Output Register (GPIO128 to GPIO159)
    Uint16                                   rsvd18[12];                   // Reserved
    union   GPEGMUX1_REG                     GPEGMUX1;                     // GPIO E Peripheral Group Mux (GPIO128 to 143)
    union   GPEGMUX2_REG                     GPEGMUX2;                     // GPIO E Peripheral Group Mux (GPIO144  to 159)
    Uint16                                   rsvd19[4];                    // Reserved
    union   GPECSEL1_REG                     GPECSEL1;                     // GPIO E Core Select Register (GPIO128 to 135)
    union   GPECSEL2_REG                     GPECSEL2;                     // GPIO E Core Select Register (GPIO136 to 143)
    union   GPECSEL3_REG                     GPECSEL3;                     // GPIO E Core Select Register (GPIO144  to 151)
    union   GPECSEL4_REG                     GPECSEL4;                     // GPIO E Core Select Register (GPIO152 to 159)
    Uint16                                   rsvd20[12];                   // Reserved
    union   GPELOCK_REG                      GPELOCK;                      // GPIO E Lock Configuration Register (GPIO128 to 159)
    union   GPECR_REG                        GPECR;                        // GPIO E Lock Commit Register (GPIO128 to 159)
    union   GPFCTRL_REG                      GPFCTRL;                      // GPIO F Qualification Sampling Period Control (GPIO160 to 168)
    union   GPFQSEL1_REG                     GPFQSEL1;                     // GPIO F Qualifier Select 1 Register (GPIO160 to 168)
    Uint16                                   rsvd21[2];                    // Reserved
    union   GPFMUX1_REG                      GPFMUX1;                      // GPIO F Mux 1 Register (GPIO160 to 168)
    Uint16                                   rsvd22[2];                    // Reserved
    union   GPFDIR_REG                       GPFDIR;                       // GPIO F Direction Register (GPIO160 to 168)
    union   GPFPUD_REG                       GPFPUD;                       // GPIO F Pull Up Disable Register (GPIO160 to 168) 
    Uint16                                   rsvd23[2];                    // Reserved
    union   GPFINV_REG                       GPFINV;                       // GPIO F Input Polarity Invert Registers (GPIO160 to 168)
    union   GPFODR_REG                       GPFODR;                       // GPIO F Open Drain Output Register (GPIO160 to GPIO168)
    Uint16                                   rsvd24[12];                   // Reserved
    union   GPFGMUX1_REG                     GPFGMUX1;                     // GPIO F Peripheral Group Mux (GPIO160 to 168)
    Uint16                                   rsvd25[6];                    // Reserved
    union   GPFCSEL1_REG                     GPFCSEL1;                     // GPIO F Core Select Register (GPIO160 to 167)
    union   GPFCSEL2_REG                     GPFCSEL2;                     // GPIO F Core Select Register (GPIO168)
    Uint16                                   rsvd26[16];                   // Reserved
    union   GPFLOCK_REG                      GPFLOCK;                      // GPIO F Lock Configuration Register (GPIO160 to 168)
    union   GPFCR_REG                        GPFCR;                        // GPIO F Lock Commit Register (GPIO160 to 168)
};

struct GPADAT_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Data Register for this pin
    Uint16 GPIO1:1;                     // 1 Data Register for this pin
    Uint16 GPIO2:1;                     // 2 Data Register for this pin
    Uint16 GPIO3:1;                     // 3 Data Register for this pin
    Uint16 GPIO4:1;                     // 4 Data Register for this pin
    Uint16 GPIO5:1;                     // 5 Data Register for this pin
    Uint16 GPIO6:1;                     // 6 Data Register for this pin
    Uint16 GPIO7:1;                     // 7 Data Register for this pin
    Uint16 GPIO8:1;                     // 8 Data Register for this pin
    Uint16 GPIO9:1;                     // 9 Data Register for this pin
    Uint16 GPIO10:1;                    // 10 Data Register for this pin
    Uint16 GPIO11:1;                    // 11 Data Register for this pin
    Uint16 GPIO12:1;                    // 12 Data Register for this pin
    Uint16 GPIO13:1;                    // 13 Data Register for this pin
    Uint16 GPIO14:1;                    // 14 Data Register for this pin
    Uint16 GPIO15:1;                    // 15 Data Register for this pin
    Uint16 GPIO16:1;                    // 16 Data Register for this pin
    Uint16 GPIO17:1;                    // 17 Data Register for this pin
    Uint16 GPIO18:1;                    // 18 Data Register for this pin
    Uint16 GPIO19:1;                    // 19 Data Register for this pin
    Uint16 GPIO20:1;                    // 20 Data Register for this pin
    Uint16 GPIO21:1;                    // 21 Data Register for this pin
    Uint16 GPIO22:1;                    // 22 Data Register for this pin
    Uint16 GPIO23:1;                    // 23 Data Register for this pin
    Uint16 GPIO24:1;                    // 24 Data Register for this pin
    Uint16 GPIO25:1;                    // 25 Data Register for this pin
    Uint16 GPIO26:1;                    // 26 Data Register for this pin
    Uint16 GPIO27:1;                    // 27 Data Register for this pin
    Uint16 GPIO28:1;                    // 28 Data Register for this pin
    Uint16 GPIO29:1;                    // 29 Data Register for this pin
    Uint16 GPIO30:1;                    // 30 Data Register for this pin
    Uint16 GPIO31:1;                    // 31 Data Register for this pin
};

union GPADAT_REG {
    Uint32  all;
    struct  GPADAT_BITS  bit;
};

struct GPASET_BITS {                    // bits description
    Uint16 GPIO0:1;                     // 0 Output Set bit for this pin
    Uint16 GPIO1:1;                     // 1 Output Set bit for this pin
    Uint16 GPIO2:1;                     // 2 Output Set bit for this pin
    Uint16 GPIO3:1;                     // 3 Output Set bit for this pin
    Uint16 GPIO4:1;                     // 4 Output Set bit for this pin
    Uint16 GPIO5:1;                     // 5 Output Set bit for this pin
    Uint16 GPIO6:1;                     // 6 Output Set bit for this pin
    Uint16 GPIO7:1;                     // 7 Output Set bit for this pin
    Uint16 GPIO8:1;                     // 8 Output Set bit for this pin
    Uint16 GPIO9:1;                     // 9 Output Set bit for this pin
    Uint16 GPIO10:1;                    // 10 Output Set bit for this pin
    Uint16 GPIO11:1;                    // 11 Output Set bit for this pin
    Uint16 GPIO12:1;                    // 12 Output Set bit for this pin
    Uint16 GPIO13:1;                    // 13 Output Set bit for this pin
    Uint16 GPIO14:1;                    // 14 Output Set bit for this pin
    Uint16 GPIO15:1;                    // 15 Output Set bit for this pin
    Uint16 GPIO16:1;                    // 16 Output Set bit for this pin
    Uint16 GPIO17:1;                    // 17 Output Set bit for this pin
    Uint16 GPIO18:1;                    // 18 Output Set bit for this pin
    Uint16 GPIO19:1;                    // 19 Output Set bit for this pin
    Uint16 GPIO20:1;                    // 20 Output Set bit for this pin
    Uint16 GPIO21:1;                    // 21 Output Set bit for this pin
    Uint16 GPIO22:1;                    // 22 Output Set bit for this pin
    Uint16 GPIO23:1;                    // 23 Output Set bit for this pin
    Uint16 GPIO24:1;                    // 24 Output Set bit for this pin
    Uint16 GPIO25:1;                    // 25 Output Set bit for this pin
    Uint16 GPIO26:1;                    // 26 Output Set bit for this pin
    Uint16 GPIO27:1;                    // 27 Output Set bit for this pin
    Uint16 GPIO28:1;                    // 28 Output Set bit for this pin
    Uint16 GPIO29:1;                    // 29 Output Set bit for this pin
    Uint16 GPIO30:1;                    // 30 Output Set bit for this pin
    Uint16 GPIO31:1;                    // 31 Output Set bit for this pin
};

union GPASET_REG {
    Uint32  all;
    struct  GPASET_BITS  bit;
};

struct GPACLEAR_BITS {                  // bits description
    Uint16 GPIO0:1;                     // 0 Output Clear bit for this pin
    Uint16 GPIO1:1;                     // 1 Output Clear bit for this pin
    Uint16 GPIO2:1;                     // 2 Output Clear bit for this pin
    Uint16 GPIO3:1;                     // 3 Output Clear bit for this pin
    Uint16 GPIO4:1;                     // 4 Output Clear bit for this pin
    Uint16 GPIO5:1;                     // 5 Output Clear bit for this pin
    Uint16 GPIO6:1;                     // 6 Output Clear bit for this pin
    Uint16 GPIO7:1;                     // 7 Output Clear bit for this pin
    Uint16 GPIO8:1;                     // 8 Output Clear bit for this pin
    Uint16 GPIO9:1;                     // 9 Output Clear bit for this pin
    Uint16 GPIO10:1;                    // 10 Output Clear bit for this pin
    Uint16 GPIO11:1;                    // 11 Output Clear bit for this pin
    Uint16 GPIO12:1;                    // 12 Output Clear bit for this pin
    Uint16 GPIO13:1;                    // 13 Output Clear bit for this pin
    Uint16 GPIO14:1;                    // 14 Output Clear bit for this pin
    Uint16 GPIO15:1;                    // 15 Output Clear bit for this pin
    Uint16 GPIO16:1;                    // 16 Output Clear bit for this pin
    Uint16 GPIO17:1;                    // 17 Output Clear bit for this pin
    Uint16 GPIO18:1;                    // 18 Output Clear bit for this pin
    Uint16 GPIO19:1;                    // 19 Output Clear bit for this pin
    Uint16 GPIO20:1;                    // 20 Output Clear bit for this pin
    Uint16 GPIO21:1;                    // 21 Output Clear bit for this pin
    Uint16 GPIO22:1;                    // 22 Output Clear bit for this pin
    Uint16 GPIO23:1;                    // 23 Output Clear bit for this pin
    Uint16 GPIO24:1;                    // 24 Output Clear bit for this pin
    Uint16 GPIO25:1;                    // 25 Output Clear bit for this pin
    Uint16 GPIO26:1;                    // 26 Output Clear bit for this pin
    Uint16 GPIO27:1;                    // 27 Output Clear bit for this pin
    Uint16 GPIO28:1;                    // 28 Output Clear bit for this pin
    Uint16 GPIO29:1;                    // 29 Output Clear bit for this pin
    Uint16 GPIO30:1;                    // 30 Output Clear bit for this pin
    Uint16 GPIO31:1;                    // 31 Output Clear bit for this pin
};

union GPACLEAR_REG {
    Uint32  all;
    struct  GPACLEAR_BITS  bit;
};

struct GPATOGGLE_BITS {                 // bits description
    Uint16 GPIO0:1;                     // 0 Output Toggle bit for this pin
    Uint16 GPIO1:1;                     // 1 Output Toggle bit for this pin
    Uint16 GPIO2:1;                     // 2 Output Toggle bit for this pin
    Uint16 GPIO3:1;                     // 3 Output Toggle bit for this pin
    Uint16 GPIO4:1;                     // 4 Output Toggle bit for this pin
    Uint16 GPIO5:1;                     // 5 Output Toggle bit for this pin
    Uint16 GPIO6:1;                     // 6 Output Toggle bit for this pin
    Uint16 GPIO7:1;                     // 7 Output Toggle bit for this pin
    Uint16 GPIO8:1;                     // 8 Output Toggle bit for this pin
    Uint16 GPIO9:1;                     // 9 Output Toggle bit for this pin
    Uint16 GPIO10:1;                    // 10 Output Toggle bit for this pin
    Uint16 GPIO11:1;                    // 11 Output Toggle bit for this pin
    Uint16 GPIO12:1;                    // 12 Output Toggle bit for this pin
    Uint16 GPIO13:1;                    // 13 Output Toggle bit for this pin
    Uint16 GPIO14:1;                    // 14 Output Toggle bit for this pin
    Uint16 GPIO15:1;                    // 15 Output Toggle bit for this pin
    Uint16 GPIO16:1;                    // 16 Output Toggle bit for this pin
    Uint16 GPIO17:1;                    // 17 Output Toggle bit for this pin
    Uint16 GPIO18:1;                    // 18 Output Toggle bit for this pin
    Uint16 GPIO19:1;                    // 19 Output Toggle bit for this pin
    Uint16 GPIO20:1;                    // 20 Output Toggle bit for this pin
    Uint16 GPIO21:1;                    // 21 Output Toggle bit for this pin
    Uint16 GPIO22:1;                    // 22 Output Toggle bit for this pin
    Uint16 GPIO23:1;                    // 23 Output Toggle bit for this pin
    Uint16 GPIO24:1;                    // 24 Output Toggle bit for this pin
    Uint16 GPIO25:1;                    // 25 Output Toggle bit for this pin
    Uint16 GPIO26:1;                    // 26 Output Toggle bit for this pin
    Uint16 GPIO27:1;                    // 27 Output Toggle bit for this pin
    Uint16 GPIO28:1;                    // 28 Output Toggle bit for this pin
    Uint16 GPIO29:1;                    // 29 Output Toggle bit for this pin
    Uint16 GPIO30:1;                    // 30 Output Toggle bit for this pin
    Uint16 GPIO31:1;                    // 31 Output Toggle bit for this pin
};

union GPATOGGLE_REG {
    Uint32  all;
    struct  GPATOGGLE_BITS  bit;
};

struct GPBDAT_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Data Register for this pin
    Uint16 GPIO33:1;                    // 1 Data Register for this pin
    Uint16 GPIO34:1;                    // 2 Data Register for this pin
    Uint16 GPIO35:1;                    // 3 Data Register for this pin
    Uint16 GPIO36:1;                    // 4 Data Register for this pin
    Uint16 GPIO37:1;                    // 5 Data Register for this pin
    Uint16 GPIO38:1;                    // 6 Data Register for this pin
    Uint16 GPIO39:1;                    // 7 Data Register for this pin
    Uint16 GPIO40:1;                    // 8 Data Register for this pin
    Uint16 GPIO41:1;                    // 9 Data Register for this pin
    Uint16 GPIO42:1;                    // 10 Data Register for this pin
    Uint16 GPIO43:1;                    // 11 Data Register for this pin
    Uint16 GPIO44:1;                    // 12 Data Register for this pin
    Uint16 GPIO45:1;                    // 13 Data Register for this pin
    Uint16 GPIO46:1;                    // 14 Data Register for this pin
    Uint16 GPIO47:1;                    // 15 Data Register for this pin
    Uint16 GPIO48:1;                    // 16 Data Register for this pin
    Uint16 GPIO49:1;                    // 17 Data Register for this pin
    Uint16 GPIO50:1;                    // 18 Data Register for this pin
    Uint16 GPIO51:1;                    // 19 Data Register for this pin
    Uint16 GPIO52:1;                    // 20 Data Register for this pin
    Uint16 GPIO53:1;                    // 21 Data Register for this pin
    Uint16 GPIO54:1;                    // 22 Data Register for this pin
    Uint16 GPIO55:1;                    // 23 Data Register for this pin
    Uint16 GPIO56:1;                    // 24 Data Register for this pin
    Uint16 GPIO57:1;                    // 25 Data Register for this pin
    Uint16 GPIO58:1;                    // 26 Data Register for this pin
    Uint16 GPIO59:1;                    // 27 Data Register for this pin
    Uint16 GPIO60:1;                    // 28 Data Register for this pin
    Uint16 GPIO61:1;                    // 29 Data Register for this pin
    Uint16 GPIO62:1;                    // 30 Data Register for this pin
    Uint16 GPIO63:1;                    // 31 Data Register for this pin
};

union GPBDAT_REG {
    Uint32  all;
    struct  GPBDAT_BITS  bit;
};

struct GPBSET_BITS {                    // bits description
    Uint16 GPIO32:1;                    // 0 Output Set bit for this pin
    Uint16 GPIO33:1;                    // 1 Output Set bit for this pin
    Uint16 GPIO34:1;                    // 2 Output Set bit for this pin
    Uint16 GPIO35:1;                    // 3 Output Set bit for this pin
    Uint16 GPIO36:1;                    // 4 Output Set bit for this pin
    Uint16 GPIO37:1;                    // 5 Output Set bit for this pin
    Uint16 GPIO38:1;                    // 6 Output Set bit for this pin
    Uint16 GPIO39:1;                    // 7 Output Set bit for this pin
    Uint16 GPIO40:1;                    // 8 Output Set bit for this pin
    Uint16 GPIO41:1;                    // 9 Output Set bit for this pin
    Uint16 GPIO42:1;                    // 10 Output Set bit for this pin
    Uint16 GPIO43:1;                    // 11 Output Set bit for this pin
    Uint16 GPIO44:1;                    // 12 Output Set bit for this pin
    Uint16 GPIO45:1;                    // 13 Output Set bit for this pin
    Uint16 GPIO46:1;                    // 14 Output Set bit for this pin
    Uint16 GPIO47:1;                    // 15 Output Set bit for this pin
    Uint16 GPIO48:1;                    // 16 Output Set bit for this pin
    Uint16 GPIO49:1;                    // 17 Output Set bit for this pin
    Uint16 GPIO50:1;                    // 18 Output Set bit for this pin
    Uint16 GPIO51:1;                    // 19 Output Set bit for this pin
    Uint16 GPIO52:1;                    // 20 Output Set bit for this pin
    Uint16 GPIO53:1;                    // 21 Output Set bit for this pin
    Uint16 GPIO54:1;                    // 22 Output Set bit for this pin
    Uint16 GPIO55:1;                    // 23 Output Set bit for this pin
    Uint16 GPIO56:1;                    // 24 Output Set bit for this pin
    Uint16 GPIO57:1;                    // 25 Output Set bit for this pin
    Uint16 GPIO58:1;                    // 26 Output Set bit for this pin
    Uint16 GPIO59:1;                    // 27 Output Set bit for this pin
    Uint16 GPIO60:1;                    // 28 Output Set bit for this pin
    Uint16 GPIO61:1;                    // 29 Output Set bit for this pin
    Uint16 GPIO62:1;                    // 30 Output Set bit for this pin
    Uint16 GPIO63:1;                    // 31 Output Set bit for this pin
};

union GPBSET_REG {
    Uint32  all;
    struct  GPBSET_BITS  bit;
};

struct GPBCLEAR_BITS {                  // bits description
    Uint16 GPIO32:1;                    // 0 Output Clear bit for this pin
    Uint16 GPIO33:1;                    // 1 Output Clear bit for this pin
    Uint16 GPIO34:1;                    // 2 Output Clear bit for this pin
    Uint16 GPIO35:1;                    // 3 Output Clear bit for this pin
    Uint16 GPIO36:1;                    // 4 Output Clear bit for this pin
    Uint16 GPIO37:1;                    // 5 Output Clear bit for this pin
    Uint16 GPIO38:1;                    // 6 Output Clear bit for this pin
    Uint16 GPIO39:1;                    // 7 Output Clear bit for this pin
    Uint16 GPIO40:1;                    // 8 Output Clear bit for this pin
    Uint16 GPIO41:1;                    // 9 Output Clear bit for this pin
    Uint16 GPIO42:1;                    // 10 Output Clear bit for this pin
    Uint16 GPIO43:1;                    // 11 Output Clear bit for this pin
    Uint16 GPIO44:1;                    // 12 Output Clear bit for this pin
    Uint16 GPIO45:1;                    // 13 Output Clear bit for this pin
    Uint16 GPIO46:1;                    // 14 Output Clear bit for this pin
    Uint16 GPIO47:1;                    // 15 Output Clear bit for this pin
    Uint16 GPIO48:1;                    // 16 Output Clear bit for this pin
    Uint16 GPIO49:1;                    // 17 Output Clear bit for this pin
    Uint16 GPIO50:1;                    // 18 Output Clear bit for this pin
    Uint16 GPIO51:1;                    // 19 Output Clear bit for this pin
    Uint16 GPIO52:1;                    // 20 Output Clear bit for this pin
    Uint16 GPIO53:1;                    // 21 Output Clear bit for this pin
    Uint16 GPIO54:1;                    // 22 Output Clear bit for this pin
    Uint16 GPIO55:1;                    // 23 Output Clear bit for this pin
    Uint16 GPIO56:1;                    // 24 Output Clear bit for this pin
    Uint16 GPIO57:1;                    // 25 Output Clear bit for this pin
    Uint16 GPIO58:1;                    // 26 Output Clear bit for this pin
    Uint16 GPIO59:1;                    // 27 Output Clear bit for this pin
    Uint16 GPIO60:1;                    // 28 Output Clear bit for this pin
    Uint16 GPIO61:1;                    // 29 Output Clear bit for this pin
    Uint16 GPIO62:1;                    // 30 Output Clear bit for this pin
    Uint16 GPIO63:1;                    // 31 Output Clear bit for this pin
};

union GPBCLEAR_REG {
    Uint32  all;
    struct  GPBCLEAR_BITS  bit;
};

struct GPBTOGGLE_BITS {                 // bits description
    Uint16 GPIO32:1;                    // 0 Output Toggle bit for this pin
    Uint16 GPIO33:1;                    // 1 Output Toggle bit for this pin
    Uint16 GPIO34:1;                    // 2 Output Toggle bit for this pin
    Uint16 GPIO35:1;                    // 3 Output Toggle bit for this pin
    Uint16 GPIO36:1;                    // 4 Output Toggle bit for this pin
    Uint16 GPIO37:1;                    // 5 Output Toggle bit for this pin
    Uint16 GPIO38:1;                    // 6 Output Toggle bit for this pin
    Uint16 GPIO39:1;                    // 7 Output Toggle bit for this pin
    Uint16 GPIO40:1;                    // 8 Output Toggle bit for this pin
    Uint16 GPIO41:1;                    // 9 Output Toggle bit for this pin
    Uint16 GPIO42:1;                    // 10 Output Toggle bit for this pin
    Uint16 GPIO43:1;                    // 11 Output Toggle bit for this pin
    Uint16 GPIO44:1;                    // 12 Output Toggle bit for this pin
    Uint16 GPIO45:1;                    // 13 Output Toggle bit for this pin
    Uint16 GPIO46:1;                    // 14 Output Toggle bit for this pin
    Uint16 GPIO47:1;                    // 15 Output Toggle bit for this pin
    Uint16 GPIO48:1;                    // 16 Output Toggle bit for this pin
    Uint16 GPIO49:1;                    // 17 Output Toggle bit for this pin
    Uint16 GPIO50:1;                    // 18 Output Toggle bit for this pin
    Uint16 GPIO51:1;                    // 19 Output Toggle bit for this pin
    Uint16 GPIO52:1;                    // 20 Output Toggle bit for this pin
    Uint16 GPIO53:1;                    // 21 Output Toggle bit for this pin
    Uint16 GPIO54:1;                    // 22 Output Toggle bit for this pin
    Uint16 GPIO55:1;                    // 23 Output Toggle bit for this pin
    Uint16 GPIO56:1;                    // 24 Output Toggle bit for this pin
    Uint16 GPIO57:1;                    // 25 Output Toggle bit for this pin
    Uint16 GPIO58:1;                    // 26 Output Toggle bit for this pin
    Uint16 GPIO59:1;                    // 27 Output Toggle bit for this pin
    Uint16 GPIO60:1;                    // 28 Output Toggle bit for this pin
    Uint16 GPIO61:1;                    // 29 Output Toggle bit for this pin
    Uint16 GPIO62:1;                    // 30 Output Toggle bit for this pin
    Uint16 GPIO63:1;                    // 31 Output Toggle bit for this pin
};

union GPBTOGGLE_REG {
    Uint32  all;
    struct  GPBTOGGLE_BITS  bit;
};

struct GPCDAT_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Data Register for this pin
    Uint16 GPIO65:1;                    // 1 Data Register for this pin
    Uint16 GPIO66:1;                    // 2 Data Register for this pin
    Uint16 GPIO67:1;                    // 3 Data Register for this pin
    Uint16 GPIO68:1;                    // 4 Data Register for this pin
    Uint16 GPIO69:1;                    // 5 Data Register for this pin
    Uint16 GPIO70:1;                    // 6 Data Register for this pin
    Uint16 GPIO71:1;                    // 7 Data Register for this pin
    Uint16 GPIO72:1;                    // 8 Data Register for this pin
    Uint16 GPIO73:1;                    // 9 Data Register for this pin
    Uint16 GPIO74:1;                    // 10 Data Register for this pin
    Uint16 GPIO75:1;                    // 11 Data Register for this pin
    Uint16 GPIO76:1;                    // 12 Data Register for this pin
    Uint16 GPIO77:1;                    // 13 Data Register for this pin
    Uint16 GPIO78:1;                    // 14 Data Register for this pin
    Uint16 GPIO79:1;                    // 15 Data Register for this pin
    Uint16 GPIO80:1;                    // 16 Data Register for this pin
    Uint16 GPIO81:1;                    // 17 Data Register for this pin
    Uint16 GPIO82:1;                    // 18 Data Register for this pin
    Uint16 GPIO83:1;                    // 19 Data Register for this pin
    Uint16 GPIO84:1;                    // 20 Data Register for this pin
    Uint16 GPIO85:1;                    // 21 Data Register for this pin
    Uint16 GPIO86:1;                    // 22 Data Register for this pin
    Uint16 GPIO87:1;                    // 23 Data Register for this pin
    Uint16 GPIO88:1;                    // 24 Data Register for this pin
    Uint16 GPIO89:1;                    // 25 Data Register for this pin
    Uint16 GPIO90:1;                    // 26 Data Register for this pin
    Uint16 GPIO91:1;                    // 27 Data Register for this pin
    Uint16 GPIO92:1;                    // 28 Data Register for this pin
    Uint16 GPIO93:1;                    // 29 Data Register for this pin
    Uint16 GPIO94:1;                    // 30 Data Register for this pin
    Uint16 GPIO95:1;                    // 31 Data Register for this pin
};

union GPCDAT_REG {
    Uint32  all;
    struct  GPCDAT_BITS  bit;
};

struct GPCSET_BITS {                    // bits description
    Uint16 GPIO64:1;                    // 0 Output Set bit for this pin
    Uint16 GPIO65:1;                    // 1 Output Set bit for this pin
    Uint16 GPIO66:1;                    // 2 Output Set bit for this pin
    Uint16 GPIO67:1;                    // 3 Output Set bit for this pin
    Uint16 GPIO68:1;                    // 4 Output Set bit for this pin
    Uint16 GPIO69:1;                    // 5 Output Set bit for this pin
    Uint16 GPIO70:1;                    // 6 Output Set bit for this pin
    Uint16 GPIO71:1;                    // 7 Output Set bit for this pin
    Uint16 GPIO72:1;                    // 8 Output Set bit for this pin
    Uint16 GPIO73:1;                    // 9 Output Set bit for this pin
    Uint16 GPIO74:1;                    // 10 Output Set bit for this pin
    Uint16 GPIO75:1;                    // 11 Output Set bit for this pin
    Uint16 GPIO76:1;                    // 12 Output Set bit for this pin
    Uint16 GPIO77:1;                    // 13 Output Set bit for this pin
    Uint16 GPIO78:1;                    // 14 Output Set bit for this pin
    Uint16 GPIO79:1;                    // 15 Output Set bit for this pin
    Uint16 GPIO80:1;                    // 16 Output Set bit for this pin
    Uint16 GPIO81:1;                    // 17 Output Set bit for this pin
    Uint16 GPIO82:1;                    // 18 Output Set bit for this pin
    Uint16 GPIO83:1;                    // 19 Output Set bit for this pin
    Uint16 GPIO84:1;                    // 20 Output Set bit for this pin
    Uint16 GPIO85:1;                    // 21 Output Set bit for this pin
    Uint16 GPIO86:1;                    // 22 Output Set bit for this pin
    Uint16 GPIO87:1;                    // 23 Output Set bit for this pin
    Uint16 GPIO88:1;                    // 24 Output Set bit for this pin
    Uint16 GPIO89:1;                    // 25 Output Set bit for this pin
    Uint16 GPIO90:1;                    // 26 Output Set bit for this pin
    Uint16 GPIO91:1;                    // 27 Output Set bit for this pin
    Uint16 GPIO92:1;                    // 28 Output Set bit for this pin
    Uint16 GPIO93:1;                    // 29 Output Set bit for this pin
    Uint16 GPIO94:1;                    // 30 Output Set bit for this pin
    Uint16 GPIO95:1;                    // 31 Output Set bit for this pin
};

union GPCSET_REG {
    Uint32  all;
    struct  GPCSET_BITS  bit;
};

struct GPCCLEAR_BITS {                  // bits description
    Uint16 GPIO64:1;                    // 0 Output Clear bit for this pin
    Uint16 GPIO65:1;                    // 1 Output Clear bit for this pin
    Uint16 GPIO66:1;                    // 2 Output Clear bit for this pin
    Uint16 GPIO67:1;                    // 3 Output Clear bit for this pin
    Uint16 GPIO68:1;                    // 4 Output Clear bit for this pin
    Uint16 GPIO69:1;                    // 5 Output Clear bit for this pin
    Uint16 GPIO70:1;                    // 6 Output Clear bit for this pin
    Uint16 GPIO71:1;                    // 7 Output Clear bit for this pin
    Uint16 GPIO72:1;                    // 8 Output Clear bit for this pin
    Uint16 GPIO73:1;                    // 9 Output Clear bit for this pin
    Uint16 GPIO74:1;                    // 10 Output Clear bit for this pin
    Uint16 GPIO75:1;                    // 11 Output Clear bit for this pin
    Uint16 GPIO76:1;                    // 12 Output Clear bit for this pin
    Uint16 GPIO77:1;                    // 13 Output Clear bit for this pin
    Uint16 GPIO78:1;                    // 14 Output Clear bit for this pin
    Uint16 GPIO79:1;                    // 15 Output Clear bit for this pin
    Uint16 GPIO80:1;                    // 16 Output Clear bit for this pin
    Uint16 GPIO81:1;                    // 17 Output Clear bit for this pin
    Uint16 GPIO82:1;                    // 18 Output Clear bit for this pin
    Uint16 GPIO83:1;                    // 19 Output Clear bit for this pin
    Uint16 GPIO84:1;                    // 20 Output Clear bit for this pin
    Uint16 GPIO85:1;                    // 21 Output Clear bit for this pin
    Uint16 GPIO86:1;                    // 22 Output Clear bit for this pin
    Uint16 GPIO87:1;                    // 23 Output Clear bit for this pin
    Uint16 GPIO88:1;                    // 24 Output Clear bit for this pin
    Uint16 GPIO89:1;                    // 25 Output Clear bit for this pin
    Uint16 GPIO90:1;                    // 26 Output Clear bit for this pin
    Uint16 GPIO91:1;                    // 27 Output Clear bit for this pin
    Uint16 GPIO92:1;                    // 28 Output Clear bit for this pin
    Uint16 GPIO93:1;                    // 29 Output Clear bit for this pin
    Uint16 GPIO94:1;                    // 30 Output Clear bit for this pin
    Uint16 GPIO95:1;                    // 31 Output Clear bit for this pin
};

union GPCCLEAR_REG {
    Uint32  all;
    struct  GPCCLEAR_BITS  bit;
};

struct GPCTOGGLE_BITS {                 // bits description
    Uint16 GPIO64:1;                    // 0 Output Toggle bit for this pin
    Uint16 GPIO65:1;                    // 1 Output Toggle bit for this pin
    Uint16 GPIO66:1;                    // 2 Output Toggle bit for this pin
    Uint16 GPIO67:1;                    // 3 Output Toggle bit for this pin
    Uint16 GPIO68:1;                    // 4 Output Toggle bit for this pin
    Uint16 GPIO69:1;                    // 5 Output Toggle bit for this pin
    Uint16 GPIO70:1;                    // 6 Output Toggle bit for this pin
    Uint16 GPIO71:1;                    // 7 Output Toggle bit for this pin
    Uint16 GPIO72:1;                    // 8 Output Toggle bit for this pin
    Uint16 GPIO73:1;                    // 9 Output Toggle bit for this pin
    Uint16 GPIO74:1;                    // 10 Output Toggle bit for this pin
    Uint16 GPIO75:1;                    // 11 Output Toggle bit for this pin
    Uint16 GPIO76:1;                    // 12 Output Toggle bit for this pin
    Uint16 GPIO77:1;                    // 13 Output Toggle bit for this pin
    Uint16 GPIO78:1;                    // 14 Output Toggle bit for this pin
    Uint16 GPIO79:1;                    // 15 Output Toggle bit for this pin
    Uint16 GPIO80:1;                    // 16 Output Toggle bit for this pin
    Uint16 GPIO81:1;                    // 17 Output Toggle bit for this pin
    Uint16 GPIO82:1;                    // 18 Output Toggle bit for this pin
    Uint16 GPIO83:1;                    // 19 Output Toggle bit for this pin
    Uint16 GPIO84:1;                    // 20 Output Toggle bit for this pin
    Uint16 GPIO85:1;                    // 21 Output Toggle bit for this pin
    Uint16 GPIO86:1;                    // 22 Output Toggle bit for this pin
    Uint16 GPIO87:1;                    // 23 Output Toggle bit for this pin
    Uint16 GPIO88:1;                    // 24 Output Toggle bit for this pin
    Uint16 GPIO89:1;                    // 25 Output Toggle bit for this pin
    Uint16 GPIO90:1;                    // 26 Output Toggle bit for this pin
    Uint16 GPIO91:1;                    // 27 Output Toggle bit for this pin
    Uint16 GPIO92:1;                    // 28 Output Toggle bit for this pin
    Uint16 GPIO93:1;                    // 29 Output Toggle bit for this pin
    Uint16 GPIO94:1;                    // 30 Output Toggle bit for this pin
    Uint16 GPIO95:1;                    // 31 Output Toggle bit for this pin
};

union GPCTOGGLE_REG {
    Uint32  all;
    struct  GPCTOGGLE_BITS  bit;
};

struct GPDDAT_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Data Register for this pin
    Uint16 GPIO97:1;                    // 1 Data Register for this pin
    Uint16 GPIO98:1;                    // 2 Data Register for this pin
    Uint16 GPIO99:1;                    // 3 Data Register for this pin
    Uint16 GPIO100:1;                   // 4 Data Register for this pin
    Uint16 GPIO101:1;                   // 5 Data Register for this pin
    Uint16 GPIO102:1;                   // 6 Data Register for this pin
    Uint16 GPIO103:1;                   // 7 Data Register for this pin
    Uint16 GPIO104:1;                   // 8 Data Register for this pin
    Uint16 GPIO105:1;                   // 9 Data Register for this pin
    Uint16 GPIO106:1;                   // 10 Data Register for this pin
    Uint16 GPIO107:1;                   // 11 Data Register for this pin
    Uint16 GPIO108:1;                   // 12 Data Register for this pin
    Uint16 GPIO109:1;                   // 13 Data Register for this pin
    Uint16 GPIO110:1;                   // 14 Data Register for this pin
    Uint16 GPIO111:1;                   // 15 Data Register for this pin
    Uint16 GPIO112:1;                   // 16 Data Register for this pin
    Uint16 GPIO113:1;                   // 17 Data Register for this pin
    Uint16 GPIO114:1;                   // 18 Data Register for this pin
    Uint16 GPIO115:1;                   // 19 Data Register for this pin
    Uint16 GPIO116:1;                   // 20 Data Register for this pin
    Uint16 GPIO117:1;                   // 21 Data Register for this pin
    Uint16 GPIO118:1;                   // 22 Data Register for this pin
    Uint16 GPIO119:1;                   // 23 Data Register for this pin
    Uint16 GPIO120:1;                   // 24 Data Register for this pin
    Uint16 GPIO121:1;                   // 25 Data Register for this pin
    Uint16 GPIO122:1;                   // 26 Data Register for this pin
    Uint16 GPIO123:1;                   // 27 Data Register for this pin
    Uint16 GPIO124:1;                   // 28 Data Register for this pin
    Uint16 GPIO125:1;                   // 29 Data Register for this pin
    Uint16 GPIO126:1;                   // 30 Data Register for this pin
    Uint16 GPIO127:1;                   // 31 Data Register for this pin
};

union GPDDAT_REG {
    Uint32  all;
    struct  GPDDAT_BITS  bit;
};

struct GPDSET_BITS {                    // bits description
    Uint16 GPIO96:1;                    // 0 Output Set bit for this pin
    Uint16 GPIO97:1;                    // 1 Output Set bit for this pin
    Uint16 GPIO98:1;                    // 2 Output Set bit for this pin
    Uint16 GPIO99:1;                    // 3 Output Set bit for this pin
    Uint16 GPIO100:1;                   // 4 Output Set bit for this pin
    Uint16 GPIO101:1;                   // 5 Output Set bit for this pin
    Uint16 GPIO102:1;                   // 6 Output Set bit for this pin
    Uint16 GPIO103:1;                   // 7 Output Set bit for this pin
    Uint16 GPIO104:1;                   // 8 Output Set bit for this pin
    Uint16 GPIO105:1;                   // 9 Output Set bit for this pin
    Uint16 GPIO106:1;                   // 10 Output Set bit for this pin
    Uint16 GPIO107:1;                   // 11 Output Set bit for this pin
    Uint16 GPIO108:1;                   // 12 Output Set bit for this pin
    Uint16 GPIO109:1;                   // 13 Output Set bit for this pin
    Uint16 GPIO110:1;                   // 14 Output Set bit for this pin
    Uint16 GPIO111:1;                   // 15 Output Set bit for this pin
    Uint16 GPIO112:1;                   // 16 Output Set bit for this pin
    Uint16 GPIO113:1;                   // 17 Output Set bit for this pin
    Uint16 GPIO114:1;                   // 18 Output Set bit for this pin
    Uint16 GPIO115:1;                   // 19 Output Set bit for this pin
    Uint16 GPIO116:1;                   // 20 Output Set bit for this pin
    Uint16 GPIO117:1;                   // 21 Output Set bit for this pin
    Uint16 GPIO118:1;                   // 22 Output Set bit for this pin
    Uint16 GPIO119:1;                   // 23 Output Set bit for this pin
    Uint16 GPIO120:1;                   // 24 Output Set bit for this pin
    Uint16 GPIO121:1;                   // 25 Output Set bit for this pin
    Uint16 GPIO122:1;                   // 26 Output Set bit for this pin
    Uint16 GPIO123:1;                   // 27 Output Set bit for this pin
    Uint16 GPIO124:1;                   // 28 Output Set bit for this pin
    Uint16 GPIO125:1;                   // 29 Output Set bit for this pin
    Uint16 GPIO126:1;                   // 30 Output Set bit for this pin
    Uint16 GPIO127:1;                   // 31 Output Set bit for this pin
};

union GPDSET_REG {
    Uint32  all;
    struct  GPDSET_BITS  bit;
};

struct GPDCLEAR_BITS {                  // bits description
    Uint16 GPIO96:1;                    // 0 Output Clear bit for this pin
    Uint16 GPIO97:1;                    // 1 Output Clear bit for this pin
    Uint16 GPIO98:1;                    // 2 Output Clear bit for this pin
    Uint16 GPIO99:1;                    // 3 Output Clear bit for this pin
    Uint16 GPIO100:1;                   // 4 Output Clear bit for this pin
    Uint16 GPIO101:1;                   // 5 Output Clear bit for this pin
    Uint16 GPIO102:1;                   // 6 Output Clear bit for this pin
    Uint16 GPIO103:1;                   // 7 Output Clear bit for this pin
    Uint16 GPIO104:1;                   // 8 Output Clear bit for this pin
    Uint16 GPIO105:1;                   // 9 Output Clear bit for this pin
    Uint16 GPIO106:1;                   // 10 Output Clear bit for this pin
    Uint16 GPIO107:1;                   // 11 Output Clear bit for this pin
    Uint16 GPIO108:1;                   // 12 Output Clear bit for this pin
    Uint16 GPIO109:1;                   // 13 Output Clear bit for this pin
    Uint16 GPIO110:1;                   // 14 Output Clear bit for this pin
    Uint16 GPIO111:1;                   // 15 Output Clear bit for this pin
    Uint16 GPIO112:1;                   // 16 Output Clear bit for this pin
    Uint16 GPIO113:1;                   // 17 Output Clear bit for this pin
    Uint16 GPIO114:1;                   // 18 Output Clear bit for this pin
    Uint16 GPIO115:1;                   // 19 Output Clear bit for this pin
    Uint16 GPIO116:1;                   // 20 Output Clear bit for this pin
    Uint16 GPIO117:1;                   // 21 Output Clear bit for this pin
    Uint16 GPIO118:1;                   // 22 Output Clear bit for this pin
    Uint16 GPIO119:1;                   // 23 Output Clear bit for this pin
    Uint16 GPIO120:1;                   // 24 Output Clear bit for this pin
    Uint16 GPIO121:1;                   // 25 Output Clear bit for this pin
    Uint16 GPIO122:1;                   // 26 Output Clear bit for this pin
    Uint16 GPIO123:1;                   // 27 Output Clear bit for this pin
    Uint16 GPIO124:1;                   // 28 Output Clear bit for this pin
    Uint16 GPIO125:1;                   // 29 Output Clear bit for this pin
    Uint16 GPIO126:1;                   // 30 Output Clear bit for this pin
    Uint16 GPIO127:1;                   // 31 Output Clear bit for this pin
};

union GPDCLEAR_REG {
    Uint32  all;
    struct  GPDCLEAR_BITS  bit;
};

struct GPDTOGGLE_BITS {                 // bits description
    Uint16 GPIO96:1;                    // 0 Output Toggle bit for this pin
    Uint16 GPIO97:1;                    // 1 Output Toggle bit for this pin
    Uint16 GPIO98:1;                    // 2 Output Toggle bit for this pin
    Uint16 GPIO99:1;                    // 3 Output Toggle bit for this pin
    Uint16 GPIO100:1;                   // 4 Output Toggle bit for this pin
    Uint16 GPIO101:1;                   // 5 Output Toggle bit for this pin
    Uint16 GPIO102:1;                   // 6 Output Toggle bit for this pin
    Uint16 GPIO103:1;                   // 7 Output Toggle bit for this pin
    Uint16 GPIO104:1;                   // 8 Output Toggle bit for this pin
    Uint16 GPIO105:1;                   // 9 Output Toggle bit for this pin
    Uint16 GPIO106:1;                   // 10 Output Toggle bit for this pin
    Uint16 GPIO107:1;                   // 11 Output Toggle bit for this pin
    Uint16 GPIO108:1;                   // 12 Output Toggle bit for this pin
    Uint16 GPIO109:1;                   // 13 Output Toggle bit for this pin
    Uint16 GPIO110:1;                   // 14 Output Toggle bit for this pin
    Uint16 GPIO111:1;                   // 15 Output Toggle bit for this pin
    Uint16 GPIO112:1;                   // 16 Output Toggle bit for this pin
    Uint16 GPIO113:1;                   // 17 Output Toggle bit for this pin
    Uint16 GPIO114:1;                   // 18 Output Toggle bit for this pin
    Uint16 GPIO115:1;                   // 19 Output Toggle bit for this pin
    Uint16 GPIO116:1;                   // 20 Output Toggle bit for this pin
    Uint16 GPIO117:1;                   // 21 Output Toggle bit for this pin
    Uint16 GPIO118:1;                   // 22 Output Toggle bit for this pin
    Uint16 GPIO119:1;                   // 23 Output Toggle bit for this pin
    Uint16 GPIO120:1;                   // 24 Output Toggle bit for this pin
    Uint16 GPIO121:1;                   // 25 Output Toggle bit for this pin
    Uint16 GPIO122:1;                   // 26 Output Toggle bit for this pin
    Uint16 GPIO123:1;                   // 27 Output Toggle bit for this pin
    Uint16 GPIO124:1;                   // 28 Output Toggle bit for this pin
    Uint16 GPIO125:1;                   // 29 Output Toggle bit for this pin
    Uint16 GPIO126:1;                   // 30 Output Toggle bit for this pin
    Uint16 GPIO127:1;                   // 31 Output Toggle bit for this pin
};

union GPDTOGGLE_REG {
    Uint32  all;
    struct  GPDTOGGLE_BITS  bit;
};

struct GPEDAT_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Data Register for this pin
    Uint16 GPIO129:1;                   // 1 Data Register for this pin
    Uint16 GPIO130:1;                   // 2 Data Register for this pin
    Uint16 GPIO131:1;                   // 3 Data Register for this pin
    Uint16 GPIO132:1;                   // 4 Data Register for this pin
    Uint16 GPIO133:1;                   // 5 Data Register for this pin
    Uint16 GPIO134:1;                   // 6 Data Register for this pin
    Uint16 GPIO135:1;                   // 7 Data Register for this pin
    Uint16 GPIO136:1;                   // 8 Data Register for this pin
    Uint16 GPIO137:1;                   // 9 Data Register for this pin
    Uint16 GPIO138:1;                   // 10 Data Register for this pin
    Uint16 GPIO139:1;                   // 11 Data Register for this pin
    Uint16 GPIO140:1;                   // 12 Data Register for this pin
    Uint16 GPIO141:1;                   // 13 Data Register for this pin
    Uint16 GPIO142:1;                   // 14 Data Register for this pin
    Uint16 GPIO143:1;                   // 15 Data Register for this pin
    Uint16 GPIO144:1;                   // 16 Data Register for this pin
    Uint16 GPIO145:1;                   // 17 Data Register for this pin
    Uint16 GPIO146:1;                   // 18 Data Register for this pin
    Uint16 GPIO147:1;                   // 19 Data Register for this pin
    Uint16 GPIO148:1;                   // 20 Data Register for this pin
    Uint16 GPIO149:1;                   // 21 Data Register for this pin
    Uint16 GPIO150:1;                   // 22 Data Register for this pin
    Uint16 GPIO151:1;                   // 23 Data Register for this pin
    Uint16 GPIO152:1;                   // 24 Data Register for this pin
    Uint16 GPIO153:1;                   // 25 Data Register for this pin
    Uint16 GPIO154:1;                   // 26 Data Register for this pin
    Uint16 GPIO155:1;                   // 27 Data Register for this pin
    Uint16 GPIO156:1;                   // 28 Data Register for this pin
    Uint16 GPIO157:1;                   // 29 Data Register for this pin
    Uint16 GPIO158:1;                   // 30 Data Register for this pin
    Uint16 GPIO159:1;                   // 31 Data Register for this pin
};

union GPEDAT_REG {
    Uint32  all;
    struct  GPEDAT_BITS  bit;
};

struct GPESET_BITS {                    // bits description
    Uint16 GPIO128:1;                   // 0 Output Set bit for this pin
    Uint16 GPIO129:1;                   // 1 Output Set bit for this pin
    Uint16 GPIO130:1;                   // 2 Output Set bit for this pin
    Uint16 GPIO131:1;                   // 3 Output Set bit for this pin
    Uint16 GPIO132:1;                   // 4 Output Set bit for this pin
    Uint16 GPIO133:1;                   // 5 Output Set bit for this pin
    Uint16 GPIO134:1;                   // 6 Output Set bit for this pin
    Uint16 GPIO135:1;                   // 7 Output Set bit for this pin
    Uint16 GPIO136:1;                   // 8 Output Set bit for this pin
    Uint16 GPIO137:1;                   // 9 Output Set bit for this pin
    Uint16 GPIO138:1;                   // 10 Output Set bit for this pin
    Uint16 GPIO139:1;                   // 11 Output Set bit for this pin
    Uint16 GPIO140:1;                   // 12 Output Set bit for this pin
    Uint16 GPIO141:1;                   // 13 Output Set bit for this pin
    Uint16 GPIO142:1;                   // 14 Output Set bit for this pin
    Uint16 GPIO143:1;                   // 15 Output Set bit for this pin
    Uint16 GPIO144:1;                   // 16 Output Set bit for this pin
    Uint16 GPIO145:1;                   // 17 Output Set bit for this pin
    Uint16 GPIO146:1;                   // 18 Output Set bit for this pin
    Uint16 GPIO147:1;                   // 19 Output Set bit for this pin
    Uint16 GPIO148:1;                   // 20 Output Set bit for this pin
    Uint16 GPIO149:1;                   // 21 Output Set bit for this pin
    Uint16 GPIO150:1;                   // 22 Output Set bit for this pin
    Uint16 GPIO151:1;                   // 23 Output Set bit for this pin
    Uint16 GPIO152:1;                   // 24 Output Set bit for this pin
    Uint16 GPIO153:1;                   // 25 Output Set bit for this pin
    Uint16 GPIO154:1;                   // 26 Output Set bit for this pin
    Uint16 GPIO155:1;                   // 27 Output Set bit for this pin
    Uint16 GPIO156:1;                   // 28 Output Set bit for this pin
    Uint16 GPIO157:1;                   // 29 Output Set bit for this pin
    Uint16 GPIO158:1;                   // 30 Output Set bit for this pin
    Uint16 GPIO159:1;                   // 31 Output Set bit for this pin
};

union GPESET_REG {
    Uint32  all;
    struct  GPESET_BITS  bit;
};

struct GPECLEAR_BITS {                  // bits description
    Uint16 GPIO128:1;                   // 0 Output Clear bit for this pin
    Uint16 GPIO129:1;                   // 1 Output Clear bit for this pin
    Uint16 GPIO130:1;                   // 2 Output Clear bit for this pin
    Uint16 GPIO131:1;                   // 3 Output Clear bit for this pin
    Uint16 GPIO132:1;                   // 4 Output Clear bit for this pin
    Uint16 GPIO133:1;                   // 5 Output Clear bit for this pin
    Uint16 GPIO134:1;                   // 6 Output Clear bit for this pin
    Uint16 GPIO135:1;                   // 7 Output Clear bit for this pin
    Uint16 GPIO136:1;                   // 8 Output Clear bit for this pin
    Uint16 GPIO137:1;                   // 9 Output Clear bit for this pin
    Uint16 GPIO138:1;                   // 10 Output Clear bit for this pin
    Uint16 GPIO139:1;                   // 11 Output Clear bit for this pin
    Uint16 GPIO140:1;                   // 12 Output Clear bit for this pin
    Uint16 GPIO141:1;                   // 13 Output Clear bit for this pin
    Uint16 GPIO142:1;                   // 14 Output Clear bit for this pin
    Uint16 GPIO143:1;                   // 15 Output Clear bit for this pin
    Uint16 GPIO144:1;                   // 16 Output Clear bit for this pin
    Uint16 GPIO145:1;                   // 17 Output Clear bit for this pin
    Uint16 GPIO146:1;                   // 18 Output Clear bit for this pin
    Uint16 GPIO147:1;                   // 19 Output Clear bit for this pin
    Uint16 GPIO148:1;                   // 20 Output Clear bit for this pin
    Uint16 GPIO149:1;                   // 21 Output Clear bit for this pin
    Uint16 GPIO150:1;                   // 22 Output Clear bit for this pin
    Uint16 GPIO151:1;                   // 23 Output Clear bit for this pin
    Uint16 GPIO152:1;                   // 24 Output Clear bit for this pin
    Uint16 GPIO153:1;                   // 25 Output Clear bit for this pin
    Uint16 GPIO154:1;                   // 26 Output Clear bit for this pin
    Uint16 GPIO155:1;                   // 27 Output Clear bit for this pin
    Uint16 GPIO156:1;                   // 28 Output Clear bit for this pin
    Uint16 GPIO157:1;                   // 29 Output Clear bit for this pin
    Uint16 GPIO158:1;                   // 30 Output Clear bit for this pin
    Uint16 GPIO159:1;                   // 31 Output Clear bit for this pin
};

union GPECLEAR_REG {
    Uint32  all;
    struct  GPECLEAR_BITS  bit;
};

struct GPETOGGLE_BITS {                 // bits description
    Uint16 GPIO128:1;                   // 0 Output Toggle bit for this pin
    Uint16 GPIO129:1;                   // 1 Output Toggle bit for this pin
    Uint16 GPIO130:1;                   // 2 Output Toggle bit for this pin
    Uint16 GPIO131:1;                   // 3 Output Toggle bit for this pin
    Uint16 GPIO132:1;                   // 4 Output Toggle bit for this pin
    Uint16 GPIO133:1;                   // 5 Output Toggle bit for this pin
    Uint16 GPIO134:1;                   // 6 Output Toggle bit for this pin
    Uint16 GPIO135:1;                   // 7 Output Toggle bit for this pin
    Uint16 GPIO136:1;                   // 8 Output Toggle bit for this pin
    Uint16 GPIO137:1;                   // 9 Output Toggle bit for this pin
    Uint16 GPIO138:1;                   // 10 Output Toggle bit for this pin
    Uint16 GPIO139:1;                   // 11 Output Toggle bit for this pin
    Uint16 GPIO140:1;                   // 12 Output Toggle bit for this pin
    Uint16 GPIO141:1;                   // 13 Output Toggle bit for this pin
    Uint16 GPIO142:1;                   // 14 Output Toggle bit for this pin
    Uint16 GPIO143:1;                   // 15 Output Toggle bit for this pin
    Uint16 GPIO144:1;                   // 16 Output Toggle bit for this pin
    Uint16 GPIO145:1;                   // 17 Output Toggle bit for this pin
    Uint16 GPIO146:1;                   // 18 Output Toggle bit for this pin
    Uint16 GPIO147:1;                   // 19 Output Toggle bit for this pin
    Uint16 GPIO148:1;                   // 20 Output Toggle bit for this pin
    Uint16 GPIO149:1;                   // 21 Output Toggle bit for this pin
    Uint16 GPIO150:1;                   // 22 Output Toggle bit for this pin
    Uint16 GPIO151:1;                   // 23 Output Toggle bit for this pin
    Uint16 GPIO152:1;                   // 24 Output Toggle bit for this pin
    Uint16 GPIO153:1;                   // 25 Output Toggle bit for this pin
    Uint16 GPIO154:1;                   // 26 Output Toggle bit for this pin
    Uint16 GPIO155:1;                   // 27 Output Toggle bit for this pin
    Uint16 GPIO156:1;                   // 28 Output Toggle bit for this pin
    Uint16 GPIO157:1;                   // 29 Output Toggle bit for this pin
    Uint16 GPIO158:1;                   // 30 Output Toggle bit for this pin
    Uint16 GPIO159:1;                   // 31 Output Toggle bit for this pin
};

union GPETOGGLE_REG {
    Uint32  all;
    struct  GPETOGGLE_BITS  bit;
};

struct GPFDAT_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Data Register for this pin
    Uint16 GPIO161:1;                   // 1 Data Register for this pin
    Uint16 GPIO162:1;                   // 2 Data Register for this pin
    Uint16 GPIO163:1;                   // 3 Data Register for this pin
    Uint16 GPIO164:1;                   // 4 Data Register for this pin
    Uint16 GPIO165:1;                   // 5 Data Register for this pin
    Uint16 GPIO166:1;                   // 6 Data Register for this pin
    Uint16 GPIO167:1;                   // 7 Data Register for this pin
    Uint16 GPIO168:1;                   // 8 Data Register for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFDAT_REG {
    Uint32  all;
    struct  GPFDAT_BITS  bit;
};

struct GPFSET_BITS {                    // bits description
    Uint16 GPIO160:1;                   // 0 Output Set bit for this pin
    Uint16 GPIO161:1;                   // 1 Output Set bit for this pin
    Uint16 GPIO162:1;                   // 2 Output Set bit for this pin
    Uint16 GPIO163:1;                   // 3 Output Set bit for this pin
    Uint16 GPIO164:1;                   // 4 Output Set bit for this pin
    Uint16 GPIO165:1;                   // 5 Output Set bit for this pin
    Uint16 GPIO166:1;                   // 6 Output Set bit for this pin
    Uint16 GPIO167:1;                   // 7 Output Set bit for this pin
    Uint16 GPIO168:1;                   // 8 Output Set bit for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFSET_REG {
    Uint32  all;
    struct  GPFSET_BITS  bit;
};

struct GPFCLEAR_BITS {                  // bits description
    Uint16 GPIO160:1;                   // 0 Output Clear bit for this pin
    Uint16 GPIO161:1;                   // 1 Output Clear bit for this pin
    Uint16 GPIO162:1;                   // 2 Output Clear bit for this pin
    Uint16 GPIO163:1;                   // 3 Output Clear bit for this pin
    Uint16 GPIO164:1;                   // 4 Output Clear bit for this pin
    Uint16 GPIO165:1;                   // 5 Output Clear bit for this pin
    Uint16 GPIO166:1;                   // 6 Output Clear bit for this pin
    Uint16 GPIO167:1;                   // 7 Output Clear bit for this pin
    Uint16 GPIO168:1;                   // 8 Output Clear bit for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFCLEAR_REG {
    Uint32  all;
    struct  GPFCLEAR_BITS  bit;
};

struct GPFTOGGLE_BITS {                 // bits description
    Uint16 GPIO160:1;                   // 0 Output Toggle bit for this pin
    Uint16 GPIO161:1;                   // 1 Output Toggle bit for this pin
    Uint16 GPIO162:1;                   // 2 Output Toggle bit for this pin
    Uint16 GPIO163:1;                   // 3 Output Toggle bit for this pin
    Uint16 GPIO164:1;                   // 4 Output Toggle bit for this pin
    Uint16 GPIO165:1;                   // 5 Output Toggle bit for this pin
    Uint16 GPIO166:1;                   // 6 Output Toggle bit for this pin
    Uint16 GPIO167:1;                   // 7 Output Toggle bit for this pin
    Uint16 GPIO168:1;                   // 8 Output Toggle bit for this pin
    Uint16 rsvd1:1;                     // 9 Reserved
    Uint16 rsvd2:1;                     // 10 Reserved
    Uint16 rsvd3:1;                     // 11 Reserved
    Uint16 rsvd4:1;                     // 12 Reserved
    Uint16 rsvd5:1;                     // 13 Reserved
    Uint16 rsvd6:1;                     // 14 Reserved
    Uint16 rsvd7:1;                     // 15 Reserved
    Uint16 rsvd8:1;                     // 16 Reserved
    Uint16 rsvd9:1;                     // 17 Reserved
    Uint16 rsvd10:1;                    // 18 Reserved
    Uint16 rsvd11:1;                    // 19 Reserved
    Uint16 rsvd12:1;                    // 20 Reserved
    Uint16 rsvd13:1;                    // 21 Reserved
    Uint16 rsvd14:1;                    // 22 Reserved
    Uint16 rsvd15:1;                    // 23 Reserved
    Uint16 rsvd16:1;                    // 24 Reserved
    Uint16 rsvd17:1;                    // 25 Reserved
    Uint16 rsvd18:1;                    // 26 Reserved
    Uint16 rsvd19:1;                    // 27 Reserved
    Uint16 rsvd20:1;                    // 28 Reserved
    Uint16 rsvd21:1;                    // 29 Reserved
    Uint16 rsvd22:1;                    // 30 Reserved
    Uint16 rsvd23:1;                    // 31 Reserved
};

union GPFTOGGLE_REG {
    Uint32  all;
    struct  GPFTOGGLE_BITS  bit;
};

struct GPIO_DATA_REGS {
    union   GPADAT_REG                       GPADAT;                       // GPIO A Data Register (GPIO0 to 31)
    union   GPASET_REG                       GPASET;                       // GPIO A Data Set Register (GPIO0 to 31)
    union   GPACLEAR_REG                     GPACLEAR;                     // GPIO A Data Clear Register (GPIO0 to 31)
    union   GPATOGGLE_REG                    GPATOGGLE;                    // GPIO A Data Toggle Register (GPIO0 to 31) 
    union   GPBDAT_REG                       GPBDAT;                       // GPIO B Data Register (GPIO32 to 63)
    union   GPBSET_REG                       GPBSET;                       // GPIO B Data Set Register (GPIO32 to 63)
    union   GPBCLEAR_REG                     GPBCLEAR;                     // GPIO B Data Clear Register (GPIO32 to 63)
    union   GPBTOGGLE_REG                    GPBTOGGLE;                    // GPIO B Data Toggle Register (GPIO32 to 63) 
    union   GPCDAT_REG                       GPCDAT;                       // GPIO C Data Register (GPIO64 to 95)
    union   GPCSET_REG                       GPCSET;                       // GPIO C Data Set Register (GPIO64 to 95)
    union   GPCCLEAR_REG                     GPCCLEAR;                     // GPIO C Data Clear Register (GPIO64 to 95)
    union   GPCTOGGLE_REG                    GPCTOGGLE;                    // GPIO C Data Toggle Register (GPIO64 to 95) 
    union   GPDDAT_REG                       GPDDAT;                       // GPIO D Data Register (GPIO96 to 127)
    union   GPDSET_REG                       GPDSET;                       // GPIO D Data Set Register (GPIO96 to 127)
    union   GPDCLEAR_REG                     GPDCLEAR;                     // GPIO D Data Clear Register (GPIO96 to 127)
    union   GPDTOGGLE_REG                    GPDTOGGLE;                    // GPIO D Data Toggle Register (GPIO96 to 127) 
    union   GPEDAT_REG                       GPEDAT;                       // GPIO E Data Register (GPIO128 to 159)
    union   GPESET_REG                       GPESET;                       // GPIO E Data Set Register (GPIO128 to 159)
    union   GPECLEAR_REG                     GPECLEAR;                     // GPIO E Data Clear Register (GPIO128 to 159)
    union   GPETOGGLE_REG                    GPETOGGLE;                    // GPIO E Data Toggle Register (GPIO128 to 159) 
    union   GPFDAT_REG                       GPFDAT;                       // GPIO F Data Register (GPIO160 to 168)
    union   GPFSET_REG                       GPFSET;                       // GPIO F Data Set Register (GPIO160 to 168)
    union   GPFCLEAR_REG                     GPFCLEAR;                     // GPIO F Data Clear Register (GPIO160 to 168)
    union   GPFTOGGLE_REG                    GPFTOGGLE;                    // GPIO F Data Toggle Register (GPIO160 to 168) 
};

//---------------------------------------------------------------------------
// GPIO External References & Function Declarations:
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_i2c.h
//
// TITLE:   F2807x Device I2C Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// I2C Individual Register Bit Definitions:

struct I2COAR_BITS {                    // bits description
    Uint16 OAR:10;                      // 9:0 I2C Own address 
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union I2COAR_REG {
    Uint16  all;
    struct  I2COAR_BITS  bit;
};

struct I2CIER_BITS {                    // bits description
    Uint16 ARBL:1;                      // 0 Arbitration-lost interrupt enable
    Uint16 NACK:1;                      // 1 No-acknowledgment interrupt enable
    Uint16 ARDY:1;                      // 2 Register-access-ready interrupt enable
    Uint16 RRDY:1;                      // 3 Receive-data-ready interrupt enable
    Uint16 XRDY:1;                      // 4 Transmit-data-ready interrupt enable
    Uint16 SCD:1;                       // 5 Stop condition detected interrupt enable
    Uint16 AAS:1;                       // 6 Addressed as slave interrupt enable
    Uint16 rsvd1:9;                     // 15:7 Reserved
};

union I2CIER_REG {
    Uint16  all;
    struct  I2CIER_BITS  bit;
};

struct I2CSTR_BITS {                    // bits description
    Uint16 ARBL:1;                      // 0 Arbitration-lost interrupt flag bit
    Uint16 NACK:1;                      // 1 No-acknowledgment interrupt flag bit.
    Uint16 ARDY:1;                      // 2 Register-access-ready interrupt flag bit
    Uint16 RRDY:1;                      // 3 Receive-data-ready interrupt flag bit.
    Uint16 XRDY:1;                      // 4 Transmit-data-ready interrupt flag bit.
    Uint16 SCD:1;                       // 5 Stop condition detected bit.
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 AD0:1;                       // 8 Address 0 bits
    Uint16 AAS:1;                       // 9 Addressed-as-slave bit
    Uint16 XSMT:1;                      // 10 Transmit shift register empty bit.
    Uint16 RSFULL:1;                    // 11 Receive shift register full bit.
    Uint16 BB:1;                        // 12 Bus busy bit.
    Uint16 NACKSNT:1;                   // 13 NACK sent bit.
    Uint16 SDIR:1;                      // 14 Slave direction bit
    Uint16 rsvd2:1;                     // 15 Reserved
};

union I2CSTR_REG {
    Uint16  all;
    struct  I2CSTR_BITS  bit;
};

struct I2CDRR_BITS {                    // bits description
    Uint16 DATA:8;                      // 7:0 Receive data
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union I2CDRR_REG {
    Uint16  all;
    struct  I2CDRR_BITS  bit;
};

struct I2CSAR_BITS {                    // bits description
    Uint16 SAR:10;                      // 9:0 Slave Address
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union I2CSAR_REG {
    Uint16  all;
    struct  I2CSAR_BITS  bit;
};

struct I2CDXR_BITS {                    // bits description
    Uint16 DATA:8;                      // 7:0 Transmit data
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union I2CDXR_REG {
    Uint16  all;
    struct  I2CDXR_BITS  bit;
};

struct I2CMDR_BITS {                    // bits description
    Uint16 BC:3;                        // 2:0 Bit count bits.
    Uint16 FDF:1;                       // 3 Free Data Format 
    Uint16 STB:1;                       // 4 START Byte Mode
    Uint16 IRS:1;                       // 5 I2C Module Reset 
    Uint16 DLB:1;                       // 6 Digital Loopback Mode 
    Uint16 RM:1;                        // 7 Repeat Mode
    Uint16 XA:1;                        // 8 Expanded Address Mode 
    Uint16 TRX:1;                       // 9 Transmitter Mode 
    Uint16 MST:1;                       // 10 Master Mode 
    Uint16 STP:1;                       // 11 STOP Condition 
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 STT:1;                       // 13 START condition bit
    Uint16 FREE:1;                      // 14 Debug Action
    Uint16 NACKMOD:1;                   // 15 NACK mode bit
};

union I2CMDR_REG {
    Uint16  all;
    struct  I2CMDR_BITS  bit;
};

struct I2CISRC_BITS {                   // bits description
    Uint16 INTCODE:3;                   // 2:0 Interrupt code bits.
    Uint16 rsvd1:5;                     // 7:3 Reserved
    Uint16 WRITE_ZEROS:4;               // 11:8 Reserved
    Uint16 rsvd2:4;                     // 15:12 Reserved
};

union I2CISRC_REG {
    Uint16  all;
    struct  I2CISRC_BITS  bit;
};

struct I2CEMDR_BITS {                   // bits description
    Uint16 BC:1;                        // 0 Backwards compatibility mode
    Uint16 rsvd1:15;                    // 15:1 Reserved
};

union I2CEMDR_REG {
    Uint16  all;
    struct  I2CEMDR_BITS  bit;
};

struct I2CPSC_BITS {                    // bits description
    Uint16 IPSC:8;                      // 7:0 I2C Prescaler Divide Down 
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union I2CPSC_REG {
    Uint16  all;
    struct  I2CPSC_BITS  bit;
};

struct I2CFFTX_BITS {                   // bits description
    Uint16 TXFFIL:5;                    // 4:0 Transmit FIFO Interrupt Level 
    Uint16 TXFFIENA:1;                  // 5 Transmit FIFO Interrupt Enable
    Uint16 TXFFINTCLR:1;                // 6 Transmit FIFO Interrupt Flag Clear 
    Uint16 TXFFINT:1;                   // 7 Transmit FIFO Interrupt Flag
    Uint16 TXFFST:5;                    // 12:8 Transmit FIFO Status 
    Uint16 TXFFRST:1;                   // 13 Transmit FIFO Reset 
    Uint16 I2CFFEN:1;                   // 14 Transmit FIFO Enable 
    Uint16 rsvd1:1;                     // 15 Reserved
};

union I2CFFTX_REG {
    Uint16  all;
    struct  I2CFFTX_BITS  bit;
};

struct I2CFFRX_BITS {                   // bits description
    Uint16 RXFFIL:5;                    // 4:0 Receive FIFO Interrupt Level 
    Uint16 RXFFIENA:1;                  // 5 Receive FIFO Interrupt Enable 
    Uint16 RXFFINTCLR:1;                // 6 Receive FIFO Interrupt Flag Clear 
    Uint16 RXFFINT:1;                   // 7 Receive FIFO Interrupt Flag
    Uint16 RXFFST:5;                    // 12:8 Receive FIFO Status 
    Uint16 RXFFRST:1;                   // 13 Receive FIFO Reset 
    Uint16 rsvd1:2;                     // 15:14 Reserved
};

union I2CFFRX_REG {
    Uint16  all;
    struct  I2CFFRX_BITS  bit;
};

struct I2C_REGS {
    union   I2COAR_REG                       I2COAR;                       // I2C Own address 
    union   I2CIER_REG                       I2CIER;                       // I2C Interrupt Enable 
    union   I2CSTR_REG                       I2CSTR;                       // I2C Status
    Uint16                                   I2CCLKL;                      // I2C Clock low-time divider 
    Uint16                                   I2CCLKH;                      // I2C Clock high-time divider 
    Uint16                                   I2CCNT;                       // I2C Data count
    union   I2CDRR_REG                       I2CDRR;                       // I2C Data receive
    union   I2CSAR_REG                       I2CSAR;                       // I2C Slave address
    union   I2CDXR_REG                       I2CDXR;                       // I2C Data Transmit 
    union   I2CMDR_REG                       I2CMDR;                       // I2C Mode 
    union   I2CISRC_REG                      I2CISRC;                      // I2C Interrupt Source
    union   I2CEMDR_REG                      I2CEMDR;                      // I2C Extended Mode 
    union   I2CPSC_REG                       I2CPSC;                       // I2C Prescaler 
    Uint16                                   rsvd1[19];                    // Reserved
    union   I2CFFTX_REG                      I2CFFTX;                      // I2C FIFO Transmit 
    union   I2CFFRX_REG                      I2CFFRX;                      // I2C FIFO Receive 
};

//---------------------------------------------------------------------------
// I2C External References & Function Declarations:
//
extern volatile struct I2C_REGS I2caRegs;
extern volatile struct I2C_REGS I2cbRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_input_xbar.h
//
// TITLE:   F2807x Device INPUT_XBAR Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// INPUT_XBAR Individual Register Bit Definitions:

struct INPUTSELECTLOCK_BITS {           // bits description
    Uint16 INPUT1SELECT:1;              // 0 Lock bit for INPUT1SEL Register
    Uint16 INPUT2SELECT:1;              // 1 Lock bit for INPUT2SEL Register
    Uint16 INPUT3SELECT:1;              // 2 Lock bit for INPUT3SEL Register
    Uint16 INPUT4SELECT:1;              // 3 Lock bit for INPUT4SEL Register
    Uint16 INPUT5SELECT:1;              // 4 Lock bit for INPUT5SEL Register
    Uint16 INPUT6SELECT:1;              // 5 Lock bit for INPUT7SEL Register
    Uint16 INPUT7SELECT:1;              // 6 Lock bit for INPUT8SEL Register
    Uint16 INPUT8SELECT:1;              // 7 Lock bit for INPUT9SEL Register
    Uint16 INPUT9SELECT:1;              // 8 Lock bit for INPUT10SEL Register
    Uint16 INPUT10SELECT:1;             // 9 Lock bit for INPUT11SEL Register
    Uint16 INPUT11SELECT:1;             // 10 Lock bit for INPUT11SEL Register
    Uint16 INPUT12SELECT:1;             // 11 Lock bit for INPUT12SEL Register
    Uint16 INPUT13SELECT:1;             // 12 Lock bit for INPUT13SEL Register
    Uint16 INPUT14SELECT:1;             // 13 Lock bit for INPUT14SEL Register
    Uint16 INPUT15SELECT:1;             // 14 Lock bit for INPUT15SEL Register
    Uint16 INPUT16SELECT:1;             // 15 Lock bit for INPUT16SEL Register
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union INPUTSELECTLOCK_REG {
    Uint32  all;
    struct  INPUTSELECTLOCK_BITS  bit;
};

struct INPUT_XBAR_REGS {
    Uint16                                   INPUT1SELECT;                 // INPUT1 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT2SELECT;                 // INPUT2 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT3SELECT;                 // INPUT3 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT4SELECT;                 // INPUT4 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT5SELECT;                 // INPUT5 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT6SELECT;                 // INPUT6 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT7SELECT;                 // INPUT7 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT8SELECT;                 // INPUT8 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT9SELECT;                 // INPUT9 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT10SELECT;                // INPUT10 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT11SELECT;                // INPUT11 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT12SELECT;                // INPUT12 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT13SELECT;                // INPUT13 Input Select Register (GPIO0 to x)
    Uint16                                   INPUT14SELECT;                // INPUT14 Input Select Register (GPIO0 to x)
    Uint16                                   rsvd1[16];                    // Reserved
    union   INPUTSELECTLOCK_REG              INPUTSELECTLOCK;              // Input Select Lock Register
};

//---------------------------------------------------------------------------
// INPUT_XBAR External References & Function Declarations:
//
extern volatile struct INPUT_XBAR_REGS InputXbarRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_mcbsp.h
//
// TITLE:   F2807x Device MCBSP Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// MCBSP Individual Register Bit Definitions:

struct DRR2_BITS {                      // bits description
    Uint16 HWLB:8;                      // 7:0 High word low byte
    Uint16 HWHB:8;                      // 15:8 High word high byte
};

union DRR2_REG {
    Uint16  all;
    struct  DRR2_BITS  bit;
};

struct DRR1_BITS {                      // bits description
    Uint16 LWLB:8;                      // 7:0 Low word low byte
    Uint16 LWHB:8;                      // 15:8 Low word high byte
};

union DRR1_REG {
    Uint16  all;
    struct  DRR1_BITS  bit;
};

struct DXR2_BITS {                      // bits description
    Uint16 HWLB:8;                      // 7:0 High word low byte
    Uint16 HWHB:8;                      // 15:8 High word high byte
};

union DXR2_REG {
    Uint16  all;
    struct  DXR2_BITS  bit;
};

struct DXR1_BITS {                      // bits description
    Uint16 LWLB:8;                      // 7:0 Low word low byte
    Uint16 LWHB:8;                      // 15:8 Low word high byte
};

union DXR1_REG {
    Uint16  all;
    struct  DXR1_BITS  bit;
};

struct SPCR2_BITS {                     // bits description
    Uint16 XRST:1;                      // 0 Transmitter reset
    Uint16 XRDY:1;                      // 1 Transmitter ready
    Uint16 XEMPTY:1;                    // 2 Transmitter empty
    Uint16 XSYNCERR:1;                  // 3 Transmit sync error INT flag
    Uint16 XINTM:2;                     // 5:4 Transmit Interupt mode bits
    Uint16 GRST:1;                      // 6 Sample rate generator reset
    Uint16 FRST:1;                      // 7 Frame sync logic reset
    Uint16 SOFT:1;                      // 8 SOFT bit
    Uint16 FREE:1;                      // 9 FREE bit
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union SPCR2_REG {
    Uint16  all;
    struct  SPCR2_BITS  bit;
};

struct SPCR1_BITS {                     // bits description
    Uint16 RRST:1;                      // 0 Receiver reset
    Uint16 RRDY:1;                      // 1 Receiver ready
    Uint16 RFULL:1;                     // 2 Receiver full
    Uint16 RSYNCERR:1;                  // 3 Receive sync error INT flag
    Uint16 RINTM:2;                     // 5:4 Receive Interupt mode bits
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 DXENA:1;                     // 7 DX delay enable
    Uint16 rsvd2:3;                     // 10:8 Reserved
    Uint16 CLKSTP:2;                    // 12:11 Clock stop mode
    Uint16 RJUST:2;                     // 14:13 Rx sign extension and justification mode
    Uint16 DLB:1;                       // 15 Digital loopback
};

union SPCR1_REG {
    Uint16  all;
    struct  SPCR1_BITS  bit;
};

struct RCR2_BITS {                      // bits description
    Uint16 RDATDLY:2;                   // 1:0 Receive data delay
    Uint16 RFIG:1;                      // 2 Receive frame sync ignore
    Uint16 RCOMPAND:2;                  // 4:3 Receive Companding Mode selects
    Uint16 RWDLEN2:3;                   // 7:5 Receive word length 2
    Uint16 RFRLEN2:7;                   // 14:8 Receive Frame length 2
    Uint16 RPHASE:1;                    // 15 Receive Phase
};

union RCR2_REG {
    Uint16  all;
    struct  RCR2_BITS  bit;
};

struct RCR1_BITS {                      // bits description
    Uint16 rsvd1:5;                     // 4:0 Reserved
    Uint16 RWDLEN1:3;                   // 7:5 Receive word length 1
    Uint16 RFRLEN1:7;                   // 14:8 Receive Frame length 1
    Uint16 rsvd2:1;                     // 15 Reserved
};

union RCR1_REG {
    Uint16  all;
    struct  RCR1_BITS  bit;
};

struct XCR2_BITS {                      // bits description
    Uint16 XDATDLY:2;                   // 1:0 Transmit data delay
    Uint16 XFIG:1;                      // 2 Transmit frame sync ignore
    Uint16 XCOMPAND:2;                  // 4:3 Transmit Companding Mode selects
    Uint16 XWDLEN2:3;                   // 7:5 Transmit word length 2
    Uint16 XFRLEN2:7;                   // 14:8 Transmit Frame length 2
    Uint16 XPHASE:1;                    // 15 Transmit Phase
};

union XCR2_REG {
    Uint16  all;
    struct  XCR2_BITS  bit;
};

struct XCR1_BITS {                      // bits description
    Uint16 rsvd1:5;                     // 4:0 Reserved
    Uint16 XWDLEN1:3;                   // 7:5 Transmit word length 1
    Uint16 XFRLEN1:7;                   // 14:8 Transmit Frame length 1
    Uint16 rsvd2:1;                     // 15 Reserved
};

union XCR1_REG {
    Uint16  all;
    struct  XCR1_BITS  bit;
};

struct SRGR2_BITS {                     // bits description
    Uint16 FPER:12;                     // 11:0 Frame-sync period
    Uint16 FSGM:1;                      // 12 Frame sync generator mode
    Uint16 CLKSM:1;                     // 13 Sample rate generator mode
    Uint16 rsvd1:1;                     // 14 Reserved
    Uint16 GSYNC:1;                     // 15 CLKG sync
};

union SRGR2_REG {
    Uint16  all;
    struct  SRGR2_BITS  bit;
};

struct SRGR1_BITS {                     // bits description
    Uint16 CLKGDV:8;                    // 7:0 CLKG divider
    Uint16 FWID:8;                      // 15:8 Frame width
};

union SRGR1_REG {
    Uint16  all;
    struct  SRGR1_BITS  bit;
};

struct MCR2_BITS {                      // bits description
    Uint16 XMCM:2;                      // 1:0 Transmit data delay
    Uint16 XCBLK:3;                     // 4:2 Transmit frame sync ignore
    Uint16 XPABLK:2;                    // 6:5 Transmit Companding Mode selects
    Uint16 XPBBLK:2;                    // 8:7 Transmit word length 2
    Uint16 XMCME:1;                     // 9 Transmit Frame length 2
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union MCR2_REG {
    Uint16  all;
    struct  MCR2_BITS  bit;
};

struct MCR1_BITS {                      // bits description
    Uint16 RMCM:1;                      // 0 Receive multichannel mode
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 RCBLK:3;                     // 4:2 eceive current block
    Uint16 RPABLK:2;                    // 6:5 Receive partition A Block
    Uint16 RPBBLK:2;                    // 8:7 Receive partition B Block
    Uint16 RMCME:1;                     // 9 Receive multi-channel enhance mode
    Uint16 rsvd2:6;                     // 15:10 Reserved
};

union MCR1_REG {
    Uint16  all;
    struct  MCR1_BITS  bit;
};

struct PCR_BITS {                       // bits description
    Uint16 CLKRP:1;                     // 0 Receive Clock polarity
    Uint16 CLKXP:1;                     // 1 Transmit clock polarity
    Uint16 FSRP:1;                      // 2 Receive Frame synchronization polarity
    Uint16 FSXP:1;                      // 3 Transmit Frame synchronization polarity
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 rsvd2:1;                     // 5 Reserved
    Uint16 rsvd3:1;                     // 6 Reserved
    Uint16 SCLKME:1;                    // 7 Sample clock mode selection
    Uint16 CLKRM:1;                     // 8 Receiver Clock Mode
    Uint16 CLKXM:1;                     // 9 Transmit Clock Mode.
    Uint16 FSRM:1;                      // 10 Receive Frame Synchronization Mode
    Uint16 FSXM:1;                      // 11 Transmit Frame Synchronization Mode
    Uint16 rsvd4:4;                     // 15:12 Reserved
};

union PCR_REG {
    Uint16  all;
    struct  PCR_BITS  bit;
};

struct MFFINT_BITS {                    // bits description
    Uint16 XINT:1;                      // 0 Enable for Receive Interrupt
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 RINT:1;                      // 2 Enable for transmit Interrupt
    Uint16 rsvd2:13;                    // 15:3 Reserved
};

union MFFINT_REG {
    Uint16  all;
    struct  MFFINT_BITS  bit;
};

struct McBSP_REGS {
    union   DRR2_REG                         DRR2;                         // Data receive register bits 31-16
    union   DRR1_REG                         DRR1;                         // Data receive register bits 15-0
    union   DXR2_REG                         DXR2;                         // Data transmit register bits 31-16
    union   DXR1_REG                         DXR1;                         // Data transmit register bits 15-0
    union   SPCR2_REG                        SPCR2;                        // Control register 2
    union   SPCR1_REG                        SPCR1;                        // Control register 1
    union   RCR2_REG                         RCR2;                         // Receive Control register 2
    union   RCR1_REG                         RCR1;                         // Receive Control register 1
    union   XCR2_REG                         XCR2;                         // Transmit Control register 2
    union   XCR1_REG                         XCR1;                         // Transmit Control register 1
    union   SRGR2_REG                        SRGR2;                        // Sample rate generator register 2
    union   SRGR1_REG                        SRGR1;                        // Sample rate generator register 1
    union   MCR2_REG                         MCR2;                         // Multi-channel register 2
    union   MCR1_REG                         MCR1;                         // Multi-channel register 1
    Uint16                                   RCERA;                        // Receive channel enable partition A
    Uint16                                   RCERB;                        // Receive channel enable partition B
    Uint16                                   XCERA;                        // Transmit channel enable partition A
    Uint16                                   XCERB;                        // Transmit channel enable partition B
    union   PCR_REG                          PCR;                          // Pin Control register
    Uint16                                   RCERC;                        // Receive channel enable partition C
    Uint16                                   RCERD;                        // Receive channel enable partition D
    Uint16                                   XCERC;                        // Transmit channel enable partition C
    Uint16                                   XCERD;                        // Transmit channel enable partition D
    Uint16                                   RCERE;                        // Receive channel enable partition E
    Uint16                                   RCERF;                        // Receive channel enable partition F
    Uint16                                   XCERE;                        // Transmit channel enable partition E
    Uint16                                   XCERF;                        // Transmit channel enable partition F
    Uint16                                   RCERG;                        // Receive channel enable partition G
    Uint16                                   RCERH;                        // Receive channel enable partition H
    Uint16                                   XCERG;                        // Transmit channel enable partition G
    Uint16                                   XCERH;                        // Transmit channel enable partition H
    Uint16                                   rsvd1[4];                     // Reserved
    union   MFFINT_REG                       MFFINT;                       // Interrupt enable
};

//---------------------------------------------------------------------------
// MCBSP External References & Function Declarations:
//
extern volatile struct McBSP_REGS McbspaRegs;
extern volatile struct McBSP_REGS McbspbRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_memconfig.h
//
// TITLE:   F2807x Device MEMCONFIG Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// MEMCONFIG Individual Register Bit Definitions:

struct DxLOCK_BITS {                    // bits description
    Uint16 rsvd1:2;                     // 1:0 Reserved
    Uint16 LOCK_D0:1;                   // 2 D0 RAM access protection and master select fields lock bit
    Uint16 LOCK_D1:1;                   // 3 D1 RAM access protection and master select fields lock bit
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union DxLOCK_REG {
    Uint32  all;
    struct  DxLOCK_BITS  bit;
};

struct DxCOMMIT_BITS {                  // bits description
    Uint16 rsvd1:2;                     // 1:0 Reserved
    Uint16 COMMIT_D0:1;                 // 2 D0 RAM access protection and master select permanent lock
    Uint16 COMMIT_D1:1;                 // 3 D1 RAM access protection and master select permanent lock
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union DxCOMMIT_REG {
    Uint32  all;
    struct  DxCOMMIT_BITS  bit;
};

struct DxACCPROT0_BITS {                // bits description
    Uint16 rsvd1:16;                    // 15:0 Reserved
    Uint16 FETCHPROT_D0:1;              // 16 Fetch Protection For D0 RAM
    Uint16 CPUWRPROT_D0:1;              // 17 CPU WR Protection For D0 RAM
    Uint16 rsvd2:6;                     // 23:18 Reserved
    Uint16 FETCHPROT_D1:1;              // 24 Fetch Protection For D1 RAM
    Uint16 CPUWRPROT_D1:1;              // 25 CPU WR Protection For D1 RAM
    Uint16 rsvd3:6;                     // 31:26 Reserved
};

union DxACCPROT0_REG {
    Uint32  all;
    struct  DxACCPROT0_BITS  bit;
};

struct DxTEST_BITS {                    // bits description
    Uint16 TEST_M0:2;                   // 1:0 Selects the different modes for M0 RAM
    Uint16 TEST_M1:2;                   // 3:2 Selects the different modes for M1 RAM
    Uint16 TEST_D0:2;                   // 5:4 Selects the different modes for D0 RAM
    Uint16 TEST_D1:2;                   // 7:6 Selects the different modes for D1 RAM
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DxTEST_REG {
    Uint32  all;
    struct  DxTEST_BITS  bit;
};

struct DxINIT_BITS {                    // bits description
    Uint16 INIT_M0:1;                   // 0 RAM Initialization control for M0 RAM.
    Uint16 INIT_M1:1;                   // 1 RAM Initialization control for M1 RAM.
    Uint16 INIT_D0:1;                   // 2 RAM Initialization control for D0 RAM.
    Uint16 INIT_D1:1;                   // 3 RAM Initialization control for D1 RAM.
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DxINIT_REG {
    Uint32  all;
    struct  DxINIT_BITS  bit;
};

struct DxINITDONE_BITS {                // bits description
    Uint16 INITDONE_M0:1;               // 0 RAM Initialization status for M0 RAM.
    Uint16 INITDONE_M1:1;               // 1 RAM Initialization status for M1 RAM.
    Uint16 INITDONE_D0:1;               // 2 RAM Initialization status for D0 RAM.
    Uint16 INITDONE_D1:1;               // 3 RAM Initialization status for D1 RAM.
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DxINITDONE_REG {
    Uint32  all;
    struct  DxINITDONE_BITS  bit;
};

struct LSxLOCK_BITS {                   // bits description
    Uint16 LOCK_LS0:1;                  // 0 LS0 RAM access protection and master select fields lock bit
    Uint16 LOCK_LS1:1;                  // 1 LS1 RAM access protection and master select fields lock bit
    Uint16 LOCK_LS2:1;                  // 2 LS2 RAM access protection and master select fields lock bit
    Uint16 LOCK_LS3:1;                  // 3 LS3 RAM access protection and master select fields lock bit
    Uint16 LOCK_LS4:1;                  // 4 LS4 RAM access protection and master select fields lock bit
    Uint16 LOCK_LS5:1;                  // 5 LS5 RAM access protection and master select fields lock bit
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxLOCK_REG {
    Uint32  all;
    struct  LSxLOCK_BITS  bit;
};

struct LSxCOMMIT_BITS {                 // bits description
    Uint16 COMMIT_LS0:1;                // 0 LS0 RAM access protection and master select permanent lock
    Uint16 COMMIT_LS1:1;                // 1 LS1 RAM access protection and master select permanent lock
    Uint16 COMMIT_LS2:1;                // 2 LS2 RAM access protection and master select permanent lock
    Uint16 COMMIT_LS3:1;                // 3 LS3 RAM access protection and master select permanent lock
    Uint16 COMMIT_LS4:1;                // 4 LS4 RAM access protection and master select permanent lock
    Uint16 COMMIT_LS5:1;                // 5 LS5 RAM access protection and master select permanent lock
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxCOMMIT_REG {
    Uint32  all;
    struct  LSxCOMMIT_BITS  bit;
};

struct LSxMSEL_BITS {                   // bits description
    Uint16 MSEL_LS0:2;                  // 1:0 Master Select for LS0 RAM
    Uint16 MSEL_LS1:2;                  // 3:2 Master Select for LS1 RAM
    Uint16 MSEL_LS2:2;                  // 5:4 Master Select for LS2 RAM
    Uint16 MSEL_LS3:2;                  // 7:6 Master Select for LS3 RAM
    Uint16 MSEL_LS4:2;                  // 9:8 Master Select for LS4 RAM
    Uint16 MSEL_LS5:2;                  // 11:10 Master Select for LS5 RAM
    Uint16 rsvd1:4;                     // 15:12 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxMSEL_REG {
    Uint32  all;
    struct  LSxMSEL_BITS  bit;
};

struct LSxCLAPGM_BITS {                 // bits description
    Uint16 CLAPGM_LS0:1;                // 0 Selects LS0 RAM as program vs data memory for CLA
    Uint16 CLAPGM_LS1:1;                // 1 Selects LS1 RAM as program vs data memory for CLA
    Uint16 CLAPGM_LS2:1;                // 2 Selects LS2 RAM as program vs data memory for CLA
    Uint16 CLAPGM_LS3:1;                // 3 Selects LS3 RAM as program vs data memory for CLA
    Uint16 CLAPGM_LS4:1;                // 4 Selects LS4 RAM as program vs data memory for CLA
    Uint16 CLAPGM_LS5:1;                // 5 Selects LS5 RAM as program vs data memory for CLA
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxCLAPGM_REG {
    Uint32  all;
    struct  LSxCLAPGM_BITS  bit;
};

struct LSxACCPROT0_BITS {               // bits description
    Uint16 FETCHPROT_LS0:1;             // 0 Fetch Protection For LS0 RAM
    Uint16 CPUWRPROT_LS0:1;             // 1 CPU WR Protection For LS0 RAM
    Uint16 rsvd1:6;                     // 7:2 Reserved
    Uint16 FETCHPROT_LS1:1;             // 8 Fetch Protection For LS1 RAM
    Uint16 CPUWRPROT_LS1:1;             // 9 CPU WR Protection For LS1 RAM
    Uint16 rsvd2:6;                     // 15:10 Reserved
    Uint16 FETCHPROT_LS2:1;             // 16 Fetch Protection For LS2 RAM
    Uint16 CPUWRPROT_LS2:1;             // 17 CPU WR Protection For LS2 RAM
    Uint16 rsvd3:6;                     // 23:18 Reserved
    Uint16 FETCHPROT_LS3:1;             // 24 Fetch Protection For LS3 RAM
    Uint16 CPUWRPROT_LS3:1;             // 25 CPU WR Protection For LS3 RAM
    Uint16 rsvd4:6;                     // 31:26 Reserved
};

union LSxACCPROT0_REG {
    Uint32  all;
    struct  LSxACCPROT0_BITS  bit;
};

struct LSxACCPROT1_BITS {               // bits description
    Uint16 FETCHPROT_LS4:1;             // 0 Fetch Protection For LS4 RAM
    Uint16 CPUWRPROT_LS4:1;             // 1 CPU WR Protection For LS4 RAM
    Uint16 rsvd1:6;                     // 7:2 Reserved
    Uint16 FETCHPROT_LS5:1;             // 8 Fetch Protection For LS5 RAM
    Uint16 CPUWRPROT_LS5:1;             // 9 CPU WR Protection For LS5 RAM
    Uint16 rsvd2:6;                     // 15:10 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union LSxACCPROT1_REG {
    Uint32  all;
    struct  LSxACCPROT1_BITS  bit;
};

struct LSxTEST_BITS {                   // bits description
    Uint16 TEST_LS0:2;                  // 1:0 Selects the different modes for LS0 RAM
    Uint16 TEST_LS1:2;                  // 3:2 Selects the different modes for LS1 RAM
    Uint16 TEST_LS2:2;                  // 5:4 Selects the different modes for LS2 RAM
    Uint16 TEST_LS3:2;                  // 7:6 Selects the different modes for LS3 RAM
    Uint16 TEST_LS4:2;                  // 9:8 Selects the different modes for LS4 RAM
    Uint16 TEST_LS5:2;                  // 11:10 Selects the different modes for LS5 RAM
    Uint16 rsvd1:4;                     // 15:12 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxTEST_REG {
    Uint32  all;
    struct  LSxTEST_BITS  bit;
};

struct LSxINIT_BITS {                   // bits description
    Uint16 INIT_LS0:1;                  // 0 RAM Initialization control for LS0 RAM.
    Uint16 INIT_LS1:1;                  // 1 RAM Initialization control for LS1 RAM.
    Uint16 INIT_LS2:1;                  // 2 RAM Initialization control for LS2 RAM.
    Uint16 INIT_LS3:1;                  // 3 RAM Initialization control for LS3 RAM.
    Uint16 INIT_LS4:1;                  // 4 RAM Initialization control for LS4 RAM.
    Uint16 INIT_LS5:1;                  // 5 RAM Initialization control for LS5 RAM.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxINIT_REG {
    Uint32  all;
    struct  LSxINIT_BITS  bit;
};

struct LSxINITDONE_BITS {               // bits description
    Uint16 INITDONE_LS0:1;              // 0 RAM Initialization status for LS0 RAM.
    Uint16 INITDONE_LS1:1;              // 1 RAM Initialization status for LS1 RAM.
    Uint16 INITDONE_LS2:1;              // 2 RAM Initialization status for LS2 RAM.
    Uint16 INITDONE_LS3:1;              // 3 RAM Initialization status for LS3 RAM.
    Uint16 INITDONE_LS4:1;              // 4 RAM Initialization status for LS4 RAM.
    Uint16 INITDONE_LS5:1;              // 5 RAM Initialization status for LS5 RAM.
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LSxINITDONE_REG {
    Uint32  all;
    struct  LSxINITDONE_BITS  bit;
};

struct GSxLOCK_BITS {                   // bits description
    Uint16 LOCK_GS0:1;                  // 0 GS0 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS1:1;                  // 1 GS1 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS2:1;                  // 2 GS2 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS3:1;                  // 3 GS3 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS4:1;                  // 4 GS4 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS5:1;                  // 5 GS5 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS6:1;                  // 6 GS6 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS7:1;                  // 7 GS7 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS8:1;                  // 8 GS8 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS9:1;                  // 9 GS9 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS10:1;                 // 10 GS10 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS11:1;                 // 11 GS11 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS12:1;                 // 12 GS12 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS13:1;                 // 13 GS13 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS14:1;                 // 14 GS14 RAM access protection and master select fields lock bit
    Uint16 LOCK_GS15:1;                 // 15 GS15 RAM access protection and master select fields lock bit
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union GSxLOCK_REG {
    Uint32  all;
    struct  GSxLOCK_BITS  bit;
};

struct GSxCOMMIT_BITS {                 // bits description
    Uint16 COMMIT_GS0:1;                // 0 GS0 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS1:1;                // 1 GS1 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS2:1;                // 2 GS2 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS3:1;                // 3 GS3 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS4:1;                // 4 GS4 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS5:1;                // 5 GS5 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS6:1;                // 6 GS6 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS7:1;                // 7 GS7 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS8:1;                // 8 GS8 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS9:1;                // 9 GS9 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS10:1;               // 10 GS10 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS11:1;               // 11 GS11 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS12:1;               // 12 GS12 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS13:1;               // 13 GS13 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS14:1;               // 14 GS14 RAM access protection and master select permanent lock
    Uint16 COMMIT_GS15:1;               // 15 GS15 RAM access protection and master select permanent lock
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union GSxCOMMIT_REG {
    Uint32  all;
    struct  GSxCOMMIT_BITS  bit;
};

struct GSxACCPROT0_BITS {               // bits description
    Uint16 FETCHPROT_GS0:1;             // 0 Fetch Protection For GS0 RAM
    Uint16 CPUWRPROT_GS0:1;             // 1 CPU WR Protection For GS0 RAM
    Uint16 DMAWRPROT_GS0:1;             // 2 DMA WR Protection For GS0 RAM
    Uint16 rsvd1:5;                     // 7:3 Reserved
    Uint16 FETCHPROT_GS1:1;             // 8 Fetch Protection For GS1 RAM
    Uint16 CPUWRPROT_GS1:1;             // 9 CPU WR Protection For GS1 RAM
    Uint16 DMAWRPROT_GS1:1;             // 10 DMA WR Protection For GS1 RAM
    Uint16 rsvd2:5;                     // 15:11 Reserved
    Uint16 FETCHPROT_GS2:1;             // 16 Fetch Protection For GS2 RAM
    Uint16 CPUWRPROT_GS2:1;             // 17 CPU WR Protection For GS2 RAM
    Uint16 DMAWRPROT_GS2:1;             // 18 DMA WR Protection For GS2 RAM
    Uint16 rsvd3:5;                     // 23:19 Reserved
    Uint16 FETCHPROT_GS3:1;             // 24 Fetch Protection For GS3 RAM
    Uint16 CPUWRPROT_GS3:1;             // 25 CPU WR Protection For GS3 RAM
    Uint16 DMAWRPROT_GS3:1;             // 26 DMA WR Protection For GS3 RAM
    Uint16 rsvd4:5;                     // 31:27 Reserved
};

union GSxACCPROT0_REG {
    Uint32  all;
    struct  GSxACCPROT0_BITS  bit;
};

struct GSxACCPROT1_BITS {               // bits description
    Uint16 FETCHPROT_GS4:1;             // 0 Fetch Protection For GS4 RAM
    Uint16 CPUWRPROT_GS4:1;             // 1 CPU WR Protection For GS4 RAM
    Uint16 DMAWRPROT_GS4:1;             // 2 DMA WR Protection For GS4 RAM
    Uint16 rsvd1:5;                     // 7:3 Reserved
    Uint16 FETCHPROT_GS5:1;             // 8 Fetch Protection For GS5 RAM
    Uint16 CPUWRPROT_GS5:1;             // 9 CPU WR Protection For GS5 RAM
    Uint16 DMAWRPROT_GS5:1;             // 10 DMA WR Protection For GS5RAM
    Uint16 rsvd2:5;                     // 15:11 Reserved
    Uint16 FETCHPROT_GS6:1;             // 16 Fetch Protection For GS6 RAM
    Uint16 CPUWRPROT_GS6:1;             // 17 CPU WR Protection For GS6 RAM
    Uint16 DMAWRPROT_GS6:1;             // 18 DMA WR Protection For GS6RAM
    Uint16 rsvd3:5;                     // 23:19 Reserved
    Uint16 FETCHPROT_GS7:1;             // 24 Fetch Protection For GS7 RAM
    Uint16 CPUWRPROT_GS7:1;             // 25 CPU WR Protection For GS7 RAM
    Uint16 DMAWRPROT_GS7:1;             // 26 DMA WR Protection For GS7RAM
    Uint16 rsvd4:5;                     // 31:27 Reserved
};

union GSxACCPROT1_REG {
    Uint32  all;
    struct  GSxACCPROT1_BITS  bit;
};

struct GSxACCPROT2_BITS {               // bits description
    Uint16 FETCHPROT_GS8:1;             // 0 Fetch Protection For GS8 RAM
    Uint16 CPUWRPROT_GS8:1;             // 1 CPU WR Protection For GS8 RAM
    Uint16 DMAWRPROT_GS8:1;             // 2 DMA WR Protection For GS8 RAM
    Uint16 rsvd1:5;                     // 7:3 Reserved
    Uint16 FETCHPROT_GS9:1;             // 8 Fetch Protection For GS9 RAM
    Uint16 CPUWRPROT_GS9:1;             // 9 CPU WR Protection For GS9 RAM
    Uint16 DMAWRPROT_GS9:1;             // 10 DMA WR Protection For GS9RAM
    Uint16 rsvd2:5;                     // 15:11 Reserved
    Uint16 FETCHPROT_GS10:1;            // 16 Fetch Protection For GS10 RAM
    Uint16 CPUWRPROT_GS10:1;            // 17 CPU WR Protection For GS10 RAM
    Uint16 DMAWRPROT_GS10:1;            // 18 DMA WR Protection For GS10RAM
    Uint16 rsvd3:5;                     // 23:19 Reserved
    Uint16 FETCHPROT_GS11:1;            // 24 Fetch Protection For GS11 RAM
    Uint16 CPUWRPROT_GS11:1;            // 25 CPU WR Protection For GS11 RAM
    Uint16 DMAWRPROT_GS11:1;            // 26 DMA WR Protection For GS11RAM
    Uint16 rsvd4:5;                     // 31:27 Reserved
};

union GSxACCPROT2_REG {
    Uint32  all;
    struct  GSxACCPROT2_BITS  bit;
};

struct GSxACCPROT3_BITS {               // bits description
    Uint16 FETCHPROT_GS12:1;            // 0 Fetch Protection For GS12 RAM
    Uint16 CPUWRPROT_GS12:1;            // 1 CPU WR Protection For GS12 RAM
    Uint16 DMAWRPROT_GS12:1;            // 2 DMA WR Protection For GS12 RAM
    Uint16 rsvd1:5;                     // 7:3 Reserved
    Uint16 FETCHPROT_GS13:1;            // 8 Fetch Protection For GS13 RAM
    Uint16 CPUWRPROT_GS13:1;            // 9 CPU WR Protection For GS13 RAM
    Uint16 DMAWRPROT_GS13:1;            // 10 DMA WR Protection For GS13RAM
    Uint16 rsvd2:5;                     // 15:11 Reserved
    Uint16 FETCHPROT_GS14:1;            // 16 Fetch Protection For GS14 RAM
    Uint16 CPUWRPROT_GS14:1;            // 17 CPU WR Protection For GS14 RAM
    Uint16 DMAWRPROT_GS14:1;            // 18 DMA WR Protection For GS14RAM
    Uint16 rsvd3:5;                     // 23:19 Reserved
    Uint16 FETCHPROT_GS15:1;            // 24 Fetch Protection For GS15 RAM
    Uint16 CPUWRPROT_GS15:1;            // 25 CPU WR Protection For GS15 RAM
    Uint16 DMAWRPROT_GS15:1;            // 26 DMA WR Protection For GS15RAM
    Uint16 rsvd4:5;                     // 31:27 Reserved
};

union GSxACCPROT3_REG {
    Uint32  all;
    struct  GSxACCPROT3_BITS  bit;
};

struct GSxTEST_BITS {                   // bits description
    Uint16 TEST_GS0:2;                  // 1:0 Selects the different modes for GS0 RAM
    Uint16 TEST_GS1:2;                  // 3:2 Selects the different modes for GS1 RAM
    Uint16 TEST_GS2:2;                  // 5:4 Selects the different modes for GS2 RAM
    Uint16 TEST_GS3:2;                  // 7:6 Selects the different modes for GS3 RAM
    Uint16 TEST_GS4:2;                  // 9:8 Selects the different modes for GS4 RAM
    Uint16 TEST_GS5:2;                  // 11:10 Selects the different modes for GS5 RAM
    Uint16 TEST_GS6:2;                  // 13:12 Selects the different modes for GS6 RAM
    Uint16 TEST_GS7:2;                  // 15:14 Selects the different modes for GS7 RAM
    Uint16 TEST_GS8:2;                  // 17:16 Selects the different modes for GS8 RAM
    Uint16 TEST_GS9:2;                  // 19:18 Selects the different modes for GS9 RAM
    Uint16 TEST_GS10:2;                 // 21:20 Selects the different modes for GS10 RAM
    Uint16 TEST_GS11:2;                 // 23:22 Selects the different modes for GS11 RAM
    Uint16 TEST_GS12:2;                 // 25:24 Selects the different modes for GS12 RAM
    Uint16 TEST_GS13:2;                 // 27:26 Selects the different modes for GS13 RAM
    Uint16 TEST_GS14:2;                 // 29:28 Selects the different modes for GS14 RAM
    Uint16 TEST_GS15:2;                 // 31:30 Selects the different modes for GS15 RAM
};

union GSxTEST_REG {
    Uint32  all;
    struct  GSxTEST_BITS  bit;
};

struct GSxINIT_BITS {                   // bits description
    Uint16 INIT_GS0:1;                  // 0 RAM Initialization control for GS0 RAM.
    Uint16 INIT_GS1:1;                  // 1 RAM Initialization control for GS1 RAM.
    Uint16 INIT_GS2:1;                  // 2 RAM Initialization control for GS2 RAM.
    Uint16 INIT_GS3:1;                  // 3 RAM Initialization control for GS3 RAM.
    Uint16 INIT_GS4:1;                  // 4 RAM Initialization control for GS4 RAM.
    Uint16 INIT_GS5:1;                  // 5 RAM Initialization control for GS5 RAM.
    Uint16 INIT_GS6:1;                  // 6 RAM Initialization control for GS6 RAM.
    Uint16 INIT_GS7:1;                  // 7 RAM Initialization control for GS7 RAM.
    Uint16 INIT_GS8:1;                  // 8 RAM Initialization control for GS8 RAM.
    Uint16 INIT_GS9:1;                  // 9 RAM Initialization control for GS9 RAM.
    Uint16 INIT_GS10:1;                 // 10 RAM Initialization control for GS10 RAM.
    Uint16 INIT_GS11:1;                 // 11 RAM Initialization control for GS11 RAM.
    Uint16 INIT_GS12:1;                 // 12 RAM Initialization control for GS12 RAM.
    Uint16 INIT_GS13:1;                 // 13 RAM Initialization control for GS13 RAM.
    Uint16 INIT_GS14:1;                 // 14 RAM Initialization control for GS14 RAM.
    Uint16 INIT_GS15:1;                 // 15 RAM Initialization control for GS15 RAM.
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union GSxINIT_REG {
    Uint32  all;
    struct  GSxINIT_BITS  bit;
};

struct GSxINITDONE_BITS {               // bits description
    Uint16 INITDONE_GS0:1;              // 0 RAM Initialization status for GS0 RAM.
    Uint16 INITDONE_GS1:1;              // 1 RAM Initialization status for GS1 RAM.
    Uint16 INITDONE_GS2:1;              // 2 RAM Initialization status for GS2 RAM.
    Uint16 INITDONE_GS3:1;              // 3 RAM Initialization status for GS3 RAM.
    Uint16 INITDONE_GS4:1;              // 4 RAM Initialization status for GS4 RAM.
    Uint16 INITDONE_GS5:1;              // 5 RAM Initialization status for GS5 RAM.
    Uint16 INITDONE_GS6:1;              // 6 RAM Initialization status for GS6 RAM.
    Uint16 INITDONE_GS7:1;              // 7 RAM Initialization status for GS7 RAM.
    Uint16 INITDONE_GS8:1;              // 8 RAM Initialization status for GS8 RAM.
    Uint16 INITDONE_GS9:1;              // 9 RAM Initialization status for GS9 RAM.
    Uint16 INITDONE_GS10:1;             // 10 RAM Initialization status for GS10 RAM.
    Uint16 INITDONE_GS11:1;             // 11 RAM Initialization status for GS11 RAM.
    Uint16 INITDONE_GS12:1;             // 12 RAM Initialization status for GS12 RAM.
    Uint16 INITDONE_GS13:1;             // 13 RAM Initialization status for GS13 RAM.
    Uint16 INITDONE_GS14:1;             // 14 RAM Initialization status for GS14 RAM.
    Uint16 INITDONE_GS15:1;             // 15 RAM Initialization status for GS15 RAM.
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union GSxINITDONE_REG {
    Uint32  all;
    struct  GSxINITDONE_BITS  bit;
};

struct MSGxTEST_BITS {                  // bits description
    Uint16 TEST_CPUTOCPU:2;             // 1:0 CPU to CPU Mode Select
    Uint16 TEST_CPUTOCLA1:2;            // 3:2 CPU to CLA1 MSG RAM Mode Select
    Uint16 TEST_CLA1TOCPU:2;            // 5:4 CLA1 to CPU MSG RAM Mode Select
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 rsvd2:2;                     // 9:8 Reserved
    Uint16 rsvd3:6;                     // 15:10 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union MSGxTEST_REG {
    Uint32  all;
    struct  MSGxTEST_BITS  bit;
};

struct MSGxINIT_BITS {                  // bits description
    Uint16 INIT_CPUTOCPU:1;             // 0 Initialization control for CPU to CPU MSG RAM
    Uint16 INIT_CPUTOCLA1:1;            // 1 Initialization control for CPUTOCLA1 MSG RAM
    Uint16 INIT_CLA1TOCPU:1;            // 2 Initialization control for CLA1TOCPU MSG RAM
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:1;                     // 4 Reserved
    Uint16 rsvd3:11;                    // 15:5 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union MSGxINIT_REG {
    Uint32  all;
    struct  MSGxINIT_BITS  bit;
};

struct MSGxINITDONE_BITS {              // bits description
    Uint16 INITDONE_CPUTOCPU:1;         // 0 Initialization status for CPU to CPU MSG RAM
    Uint16 INITDONE_CPUTOCLA1:1;        // 1 Initialization status for CPU to CLA1 MSG RAM
    Uint16 INITDONE_CLA1TOCPU:1;        // 2 Initialization status for CLA1 to CPU MSG RAM
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:1;                     // 4 Reserved
    Uint16 rsvd3:11;                    // 15:5 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union MSGxINITDONE_REG {
    Uint32  all;
    struct  MSGxINITDONE_BITS  bit;
};

struct MEM_CFG_REGS {
    union   DxLOCK_REG                       DxLOCK;                       // Dedicated RAM Config Lock Register
    union   DxCOMMIT_REG                     DxCOMMIT;                     // Dedicated RAM Config Lock Commit Register
    Uint16                                   rsvd1[4];                     // Reserved
    union   DxACCPROT0_REG                   DxACCPROT0;                   // Dedicated RAM Config Register
    Uint16                                   rsvd2[6];                     // Reserved
    union   DxTEST_REG                       DxTEST;                       // Dedicated RAM TEST Register
    union   DxINIT_REG                       DxINIT;                       // Dedicated RAM Init Register
    union   DxINITDONE_REG                   DxINITDONE;                   // Dedicated RAM InitDone Status Register
    Uint16                                   rsvd3[10];                    // Reserved
    union   LSxLOCK_REG                      LSxLOCK;                      // Local Shared RAM Config Lock Register
    union   LSxCOMMIT_REG                    LSxCOMMIT;                    // Local Shared RAM Config Lock Commit Register
    union   LSxMSEL_REG                      LSxMSEL;                      // Local Shared RAM Master Sel Register
    union   LSxCLAPGM_REG                    LSxCLAPGM;                    // Local Shared RAM Prog/Exe control Register
    union   LSxACCPROT0_REG                  LSxACCPROT0;                  // Local Shared RAM Config Register 0
    union   LSxACCPROT1_REG                  LSxACCPROT1;                  // Local Shared RAM Config Register 1
    Uint16                                   rsvd4[4];                     // Reserved
    union   LSxTEST_REG                      LSxTEST;                      // Local Shared RAM TEST Register
    union   LSxINIT_REG                      LSxINIT;                      // Local Shared RAM Init Register
    union   LSxINITDONE_REG                  LSxINITDONE;                  // Local Shared RAM InitDone Status Register
    Uint16                                   rsvd5[10];                    // Reserved
    union   GSxLOCK_REG                      GSxLOCK;                      // Global Shared RAM Config Lock Register
    union   GSxCOMMIT_REG                    GSxCOMMIT;                    // Global Shared RAM Config Lock Commit Register
    Uint16                                   rsvd6[4];                     // Reserved
    union   GSxACCPROT0_REG                  GSxACCPROT0;                  // Global Shared RAM Config Register 0
    union   GSxACCPROT1_REG                  GSxACCPROT1;                  // Global Shared RAM Config Register 1
    union   GSxACCPROT2_REG                  GSxACCPROT2;                  // Global Shared RAM Config Register 2
    union   GSxACCPROT3_REG                  GSxACCPROT3;                  // Global Shared RAM Config Register 3
    union   GSxTEST_REG                      GSxTEST;                      // Global Shared RAM TEST Register
    union   GSxINIT_REG                      GSxINIT;                      // Global Shared RAM Init Register
    union   GSxINITDONE_REG                  GSxINITDONE;                  // Global Shared RAM InitDone Status Register
    Uint16                                   rsvd7[26];                    // Reserved
    union   MSGxTEST_REG                     MSGxTEST;                     // Message RAM TEST Register
    union   MSGxINIT_REG                     MSGxINIT;                     // Message RAM Init Register
    union   MSGxINITDONE_REG                 MSGxINITDONE;                 // Message RAM InitDone Status Register
    Uint16                                   rsvd8[10];                    // Reserved
};

struct EMIF1LOCK_BITS {                 // bits description
    Uint16 LOCK_EMIF1:1;                // 0 EMIF1 access protection and master select fields lock bit
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF1LOCK_REG {
    Uint32  all;
    struct  EMIF1LOCK_BITS  bit;
};

struct EMIF1COMMIT_BITS {               // bits description
    Uint16 COMMIT_EMIF1:1;              // 0 EMIF1 access protection and master select permanent lock
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF1COMMIT_REG {
    Uint32  all;
    struct  EMIF1COMMIT_BITS  bit;
};

struct EMIF1ACCPROT0_BITS {             // bits description
    Uint16 FETCHPROT_EMIF1:1;           // 0 Fetch Protection For EMIF1
    Uint16 CPUWRPROT_EMIF1:1;           // 1 CPU WR Protection For EMIF1
    Uint16 DMAWRPROT_EMIF1:1;           // 2 DMA WR Protection For EMIF1
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF1ACCPROT0_REG {
    Uint32  all;
    struct  EMIF1ACCPROT0_BITS  bit;
};

struct EMIF1_CONFIG_REGS {
    union   EMIF1LOCK_REG                    EMIF1LOCK;                    // EMIF1 Config Lock Register
    union   EMIF1COMMIT_REG                  EMIF1COMMIT;                  // EMIF1 Config Lock Commit Register
    Uint16                                   rsvd1[4];                     // Reserved
    union   EMIF1ACCPROT0_REG                EMIF1ACCPROT0;                // EMIF1 Config Register 0
    Uint16                                   rsvd2[22];                    // Reserved
};

struct EMIF2LOCK_BITS {                 // bits description
    Uint16 LOCK_EMIF2:1;                // 0 EMIF2 access protection and master select permanent lock
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF2LOCK_REG {
    Uint32  all;
    struct  EMIF2LOCK_BITS  bit;
};

struct EMIF2COMMIT_BITS {               // bits description
    Uint16 COMMIT_EMIF2:1;              // 0 EMIF2 access protection and master select permanent lock
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF2COMMIT_REG {
    Uint32  all;
    struct  EMIF2COMMIT_BITS  bit;
};

struct EMIF2ACCPROT0_BITS {             // bits description
    Uint16 FETCHPROT_EMIF1:1;           // 0 Fetch Protection For EMIF2
    Uint16 CPUWRPROT_EMIF1:1;           // 1 CPU WR Protection For EMIF2
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union EMIF2ACCPROT0_REG {
    Uint32  all;
    struct  EMIF2ACCPROT0_BITS  bit;
};

struct EMIF2_CONFIG_REGS {
    union   EMIF2LOCK_REG                    EMIF2LOCK;                    // EMIF2 Config Lock Register
    union   EMIF2COMMIT_REG                  EMIF2COMMIT;                  // EMIF2 Config Lock Commit Register
    Uint16                                   rsvd1[4];                     // Reserved
    union   EMIF2ACCPROT0_REG                EMIF2ACCPROT0;                // EMIF2 Config Register 0
    Uint16                                   rsvd2[22];                    // Reserved
};

struct NMAVFLG_BITS {                   // bits description
    Uint16 CPUREAD:1;                   // 0 Non Master CPU Read Access Violation Flag
    Uint16 CPUWRITE:1;                  // 1 Non Master CPU Write Access Violation Flag
    Uint16 CPUFETCH:1;                  // 2 Non Master CPU Fetch Access Violation Flag
    Uint16 DMAWRITE:1;                  // 3 Non Master DMA Write Access Violation Flag
    Uint16 CLA1READ:1;                  // 4 Non Master CLA1 Read Access Violation Flag
    Uint16 CLA1WRITE:1;                 // 5 Non Master CLA1 Write Access Violation Flag
    Uint16 CLA1FETCH:1;                 // 6 Non Master CLA1 Fetch Access Violation Flag
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 rsvd2:1;                     // 8 Reserved
    Uint16 rsvd3:1;                     // 9 Reserved
    Uint16 rsvd4:6;                     // 15:10 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union NMAVFLG_REG {
    Uint32  all;
    struct  NMAVFLG_BITS  bit;
};

struct NMAVSET_BITS {                   // bits description
    Uint16 CPUREAD:1;                   // 0 Non Master CPU Read Access Violation Flag Set
    Uint16 CPUWRITE:1;                  // 1 Non Master CPU Write Access Violation Flag Set
    Uint16 CPUFETCH:1;                  // 2 Non Master CPU Fetch Access Violation Flag Set
    Uint16 DMAWRITE:1;                  // 3 Non Master DMA Write Access Violation Flag Set
    Uint16 CLA1READ:1;                  // 4 Non Master CLA1 Read Access Violation Flag Set
    Uint16 CLA1WRITE:1;                 // 5 Non Master CLA1 Write Access Violation Flag Set
    Uint16 CLA1FETCH:1;                 // 6 Non Master CLA1 Fetch Access Violation Flag Set
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 rsvd2:1;                     // 8 Reserved
    Uint16 rsvd3:1;                     // 9 Reserved
    Uint16 rsvd4:6;                     // 15:10 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union NMAVSET_REG {
    Uint32  all;
    struct  NMAVSET_BITS  bit;
};

struct NMAVCLR_BITS {                   // bits description
    Uint16 CPUREAD:1;                   // 0 Non Master CPU Read Access Violation Flag Clear 
    Uint16 CPUWRITE:1;                  // 1 Non Master CPU Write Access Violation Flag Clear 
    Uint16 CPUFETCH:1;                  // 2 Non Master CPU Fetch Access Violation Flag Clear 
    Uint16 DMAWRITE:1;                  // 3 Non Master DMA Write Access Violation Flag Clear 
    Uint16 CLA1READ:1;                  // 4 Non Master CLA1 Read Access Violation Flag Clear 
    Uint16 CLA1WRITE:1;                 // 5 Non Master CLA1 Write Access Violation Flag Clear 
    Uint16 CLA1FETCH:1;                 // 6 Non Master CLA1 Fetch Access Violation Flag Clear 
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 rsvd2:1;                     // 8 Reserved
    Uint16 rsvd3:1;                     // 9 Reserved
    Uint16 rsvd4:6;                     // 15:10 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union NMAVCLR_REG {
    Uint32  all;
    struct  NMAVCLR_BITS  bit;
};

struct NMAVINTEN_BITS {                 // bits description
    Uint16 CPUREAD:1;                   // 0 Non Master CPU Read Access Violation Interrupt Enable 
    Uint16 CPUWRITE:1;                  // 1 Non Master CPU Write Access Violation Interrupt Enable 
    Uint16 CPUFETCH:1;                  // 2 Non Master CPU Fetch Access Violation Interrupt Enable 
    Uint16 DMAWRITE:1;                  // 3 Non Master DMA Write Access Violation Interrupt Enable 
    Uint16 CLA1READ:1;                  // 4 Non Master CLA1 Read Access Violation Interrupt Enable 
    Uint16 CLA1WRITE:1;                 // 5 Non Master CLA1 Write Access Violation Interrupt Enable 
    Uint16 CLA1FETCH:1;                 // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable 
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 rsvd2:1;                     // 8 Reserved
    Uint16 rsvd3:1;                     // 9 Reserved
    Uint16 rsvd4:6;                     // 15:10 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union NMAVINTEN_REG {
    Uint32  all;
    struct  NMAVINTEN_BITS  bit;
};

struct MAVFLG_BITS {                    // bits description
    Uint16 CPUFETCH:1;                  // 0 Master CPU Fetch Access Violation Flag
    Uint16 CPUWRITE:1;                  // 1 Master CPU Write Access Violation Flag
    Uint16 DMAWRITE:1;                  // 2 Master DMA Write Access Violation Flag
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union MAVFLG_REG {
    Uint32  all;
    struct  MAVFLG_BITS  bit;
};

struct MAVSET_BITS {                    // bits description
    Uint16 CPUFETCH:1;                  // 0 Master CPU Fetch Access Violation Flag Set
    Uint16 CPUWRITE:1;                  // 1 Master CPU Write Access Violation Flag Set
    Uint16 DMAWRITE:1;                  // 2 Master DMA Write Access Violation Flag Set
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union MAVSET_REG {
    Uint32  all;
    struct  MAVSET_BITS  bit;
};

struct MAVCLR_BITS {                    // bits description
    Uint16 CPUFETCH:1;                  // 0 Master CPU Fetch Access Violation Flag Clear 
    Uint16 CPUWRITE:1;                  // 1 Master CPU Write Access Violation Flag Clear 
    Uint16 DMAWRITE:1;                  // 2 Master DMA Write Access Violation Flag Clear 
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union MAVCLR_REG {
    Uint32  all;
    struct  MAVCLR_BITS  bit;
};

struct MAVINTEN_BITS {                  // bits description
    Uint16 CPUFETCH:1;                  // 0 Master CPU Fetch Access Violation Interrupt Enable 
    Uint16 CPUWRITE:1;                  // 1 Master CPU Write Access Violation Interrupt Enable 
    Uint16 DMAWRITE:1;                  // 2 Master DMA Write Access Violation Interrupt Enable 
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union MAVINTEN_REG {
    Uint32  all;
    struct  MAVINTEN_BITS  bit;
};

struct ACCESS_PROTECTION_REGS {
    union   NMAVFLG_REG                      NMAVFLG;                      // Non-Master Access Violation Flag Register
    union   NMAVSET_REG                      NMAVSET;                      // Non-Master Access Violation Flag Set Register
    union   NMAVCLR_REG                      NMAVCLR;                      // Non-Master Access Violation Flag Clear Register
    union   NMAVINTEN_REG                    NMAVINTEN;                    // Non-Master Access Violation Interrupt Enable Register
    Uint32                                   NMCPURDAVADDR;                // Non-Master CPU Read Access Violation Address
    Uint32                                   NMCPUWRAVADDR;                // Non-Master CPU Write Access Violation Address
    Uint32                                   NMCPUFAVADDR;                 // Non-Master CPU Fetch Access Violation Address
    Uint32                                   NMDMAWRAVADDR;                // Non-Master DMA Write Access Violation Address
    Uint32                                   NMCLA1RDAVADDR;               // Non-Master CLA1 Read Access Violation Address
    Uint32                                   NMCLA1WRAVADDR;               // Non-Master CLA1 Write Access Violation Address
    Uint32                                   NMCLA1FAVADDR;                // Non-Master CLA1 Fetch Access Violation Address
    Uint16                                   rsvd1[10];                    // Reserved
    union   MAVFLG_REG                       MAVFLG;                       // Master Access Violation Flag Register
    union   MAVSET_REG                       MAVSET;                       // Master Access Violation Flag Set Register
    union   MAVCLR_REG                       MAVCLR;                       // Master Access Violation Flag Clear Register
    union   MAVINTEN_REG                     MAVINTEN;                     // Master Access Violation Interrupt Enable Register
    Uint32                                   MCPUFAVADDR;                  // Master CPU Fetch Access Violation Address
    Uint32                                   MCPUWRAVADDR;                 // Master CPU Write Access Violation Address
    Uint32                                   MDMAWRAVADDR;                 // Master  DMA Write Access Violation Address
    Uint16                                   rsvd2[18];                    // Reserved
};

struct UCERRFLG_BITS {                  // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Uncorrectable Read Error Flag 
    Uint16 DMARDERR:1;                  // 1 DMA Uncorrectable Read Error Flag 
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Uncorrectable Read Error Flag 
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union UCERRFLG_REG {
    Uint32  all;
    struct  UCERRFLG_BITS  bit;
};

struct UCERRSET_BITS {                  // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Uncorrectable Read Error Flag Set
    Uint16 DMARDERR:1;                  // 1 DMA Uncorrectable Read Error Flag Set
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Uncorrectable Read Error Flag Set
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union UCERRSET_REG {
    Uint32  all;
    struct  UCERRSET_BITS  bit;
};

struct UCERRCLR_BITS {                  // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Uncorrectable Read Error Flag Clear
    Uint16 DMARDERR:1;                  // 1 DMA Uncorrectable Read Error Flag Clear
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Uncorrectable Read Error Flag Clear
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union UCERRCLR_REG {
    Uint32  all;
    struct  UCERRCLR_BITS  bit;
};

struct CERRFLG_BITS {                   // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Correctable Read Error Flag 
    Uint16 DMARDERR:1;                  // 1 DMA Correctable Read Error Flag 
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Correctable Read Error Flag 
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union CERRFLG_REG {
    Uint32  all;
    struct  CERRFLG_BITS  bit;
};

struct CERRSET_BITS {                   // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Correctable Read Error Flag Set
    Uint16 DMARDERR:1;                  // 1 DMA Correctable Read Error Flag Set
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Correctable Read Error Flag Set
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union CERRSET_REG {
    Uint32  all;
    struct  CERRSET_BITS  bit;
};

struct CERRCLR_BITS {                   // bits description
    Uint16 CPURDERR:1;                  // 0 CPU Correctable Read Error Flag Clear
    Uint16 DMARDERR:1;                  // 1 DMA Correctable Read Error Flag Clear
    Uint16 CLA1RDERR:1;                 // 2 CLA1 Correctable Read Error Flag Clear
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union CERRCLR_REG {
    Uint32  all;
    struct  CERRCLR_BITS  bit;
};

struct CEINTFLG_BITS {                  // bits description
    Uint16 CEINTFLAG:1;                 // 0 Total corrected error count exceeded threshold flag.
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CEINTFLG_REG {
    Uint32  all;
    struct  CEINTFLG_BITS  bit;
};

struct CEINTCLR_BITS {                  // bits description
    Uint16 CEINTCLR:1;                  // 0 CPU Corrected Error Threshold Exceeded Error Clear.
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CEINTCLR_REG {
    Uint32  all;
    struct  CEINTCLR_BITS  bit;
};

struct CEINTSET_BITS {                  // bits description
    Uint16 CEINTSET:1;                  // 0 Total corrected error count exceeded flag set.
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CEINTSET_REG {
    Uint32  all;
    struct  CEINTSET_BITS  bit;
};

struct CEINTEN_BITS {                   // bits description
    Uint16 CEINTEN:1;                   // 0 CPU/DMA Correctable Error Interrupt Enable.
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CEINTEN_REG {
    Uint32  all;
    struct  CEINTEN_BITS  bit;
};

struct MEMORY_ERROR_REGS {
    union   UCERRFLG_REG                     UCERRFLG;                     // Uncorrectable Error Flag Register
    union   UCERRSET_REG                     UCERRSET;                     // Uncorrectable Error Flag Set Register
    union   UCERRCLR_REG                     UCERRCLR;                     // Uncorrectable Error Flag Clear Register
    Uint32                                   UCCPUREADDR;                  // Uncorrectable CPU Read Error Address
    Uint32                                   UCDMAREADDR;                  // Uncorrectable DMA Read Error Address
    Uint32                                   UCCLA1READDR;                 // Uncorrectable CLA1 Read Error Address
    Uint16                                   rsvd1[20];                    // Reserved
    union   CERRFLG_REG                      CERRFLG;                      // Correctable Error Flag Register
    union   CERRSET_REG                      CERRSET;                      // Correctable Error Flag Set Register
    union   CERRCLR_REG                      CERRCLR;                      // Correctable Error Flag Clear Register
    Uint32                                   CCPUREADDR;                   // Correctable CPU Read Error Address
    Uint16                                   rsvd2[6];                     // Reserved
    Uint32                                   CERRCNT;                      // Correctable Error Count Register
    Uint32                                   CERRTHRES;                    // Correctable Error Threshold Value Register
    union   CEINTFLG_REG                     CEINTFLG;                     // Correctable Error Interrupt Flag Status Register
    union   CEINTCLR_REG                     CEINTCLR;                     // Correctable Error Interrupt Flag Clear Register
    union   CEINTSET_REG                     CEINTSET;                     // Correctable Error Interrupt Flag Set Register
    union   CEINTEN_REG                      CEINTEN;                      // Correctable Error Interrupt Enable Register
    Uint16                                   rsvd3[6];                     // Reserved
};

struct ROMWAITSTATE_BITS {              // bits description
    Uint16 WSDISABLE:1;                 // 0 ROM Wait State Enable/Disable Control
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union ROMWAITSTATE_REG {
    Uint32  all;
    struct  ROMWAITSTATE_BITS  bit;
};

struct ROM_WAIT_STATE_REGS {
    union   ROMWAITSTATE_REG                 ROMWAITSTATE;                 // ROM Wait State Configuration Register
};

struct ROMPREFETCH_BITS {               // bits description
    Uint16 PFENABLE:1;                  // 0 ROM Prefetch Enable/Disable Control
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union ROMPREFETCH_REG {
    Uint32  all;
    struct  ROMPREFETCH_BITS  bit;
};

struct ROM_PREFETCH_REGS {
    union   ROMPREFETCH_REG                  ROMPREFETCH;                  // ROM Prefetch Configuration Register
};

//---------------------------------------------------------------------------
// MEMCONFIG External References & Function Declarations:
//
extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;
extern volatile struct MEM_CFG_REGS MemCfgRegs;
extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;
extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;
extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;
extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_nmiintrupt.h
//
// TITLE:   F2807x Device NMIINTRUPT Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// NMIINTRUPT Individual Register Bit Definitions:

struct NMICFG_BITS {                    // bits description
    Uint16 NMIE:1;                      // 0 Global NMI Enable
    Uint16 rsvd1:15;                    // 15:1 Reserved
};

union NMICFG_REG {
    Uint16  all;
    struct  NMICFG_BITS  bit;
};

struct NMIFLG_BITS {                    // bits description
    Uint16 NMIINT:1;                    // 0 NMI Interrupt Flag
    Uint16 CLOCKFAIL:1;                 // 1 Clock Fail Interrupt Flag
    Uint16 RAMUNCERR:1;                 // 2 RAM Uncorrectable Error NMI Flag
    Uint16 FLUNCERR:1;                  // 3 Flash Uncorrectable Error NMI Flag
    Uint16 CPU1HWBISTERR:1;             // 4 HW BIST Error NMI Flag
    Uint16 rsvd1:1;                     // 5 Reserved
    Uint16 rsvd2:1;                     // 6 Reserved
    Uint16 rsvd3:1;                     // 7 Reserved
    Uint16 rsvd4:1;                     // 8 Reserved
    Uint16 rsvd5:1;                     // 9 Reserved
    Uint16 rsvd6:1;                     // 10 Reserved
    Uint16 rsvd7:1;                     // 11 Reserved
    Uint16 rsvd8:4;                     // 15:12 Reserved
};

union NMIFLG_REG {
    Uint16  all;
    struct  NMIFLG_BITS  bit;
};

struct NMIFLGCLR_BITS {                 // bits description
    Uint16 NMIINT:1;                    // 0 NMIINT Flag Clear
    Uint16 CLOCKFAIL:1;                 // 1 CLOCKFAIL Flag Clear
    Uint16 RAMUNCERR:1;                 // 2 RAMUNCERR Flag Clear
    Uint16 FLUNCERR:1;                  // 3 FLUNCERR Flag Clear
    Uint16 CPU1HWBISTERR:1;             // 4 CPU1HWBISTERR Flag Clear
    Uint16 rsvd1:1;                     // 5 Reserved
    Uint16 rsvd2:1;                     // 6 Reserved
    Uint16 rsvd3:1;                     // 7 Reserved
    Uint16 rsvd4:1;                     // 8 Reserved
    Uint16 rsvd5:1;                     // 9 Reserved
    Uint16 rsvd6:1;                     // 10 Reserved
    Uint16 OVF:1;                       // 11 OVF Flag Clear
    Uint16 rsvd7:4;                     // 15:12 Reserved
};

union NMIFLGCLR_REG {
    Uint16  all;
    struct  NMIFLGCLR_BITS  bit;
};

struct NMIFLGFRC_BITS {                 // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CLOCKFAIL:1;                 // 1 CLOCKFAIL Flag Force
    Uint16 RAMUNCERR:1;                 // 2 RAMUNCERR Flag Force
    Uint16 FLUNCERR:1;                  // 3 FLUNCERR Flag Force
    Uint16 CPU1HWBISTERR:1;             // 4 CPU1HWBISTERR Flag Force
    Uint16 rsvd2:1;                     // 5 Reserved
    Uint16 rsvd3:1;                     // 6 Reserved
    Uint16 rsvd4:1;                     // 7 Reserved
    Uint16 rsvd5:1;                     // 8 Reserved
    Uint16 rsvd6:1;                     // 9 Reserved
    Uint16 rsvd7:1;                     // 10 Reserved
    Uint16 OVF:1;                       // 11 OVF Flag Force
    Uint16 rsvd8:4;                     // 15:12 Reserved
};

union NMIFLGFRC_REG {
    Uint16  all;
    struct  NMIFLGFRC_BITS  bit;
};

struct NMISHDFLG_BITS {                 // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 CLOCKFAIL:1;                 // 1 Shadow CLOCKFAIL Flag
    Uint16 RAMUNCERR:1;                 // 2 Shadow RAMUNCERR Flag
    Uint16 FLUNCERR:1;                  // 3 Shadow FLUNCERR Flag
    Uint16 CPU1HWBISTERR:1;             // 4 Shadow CPU1HWBISTERR Flag
    Uint16 rsvd2:1;                     // 5 Reserved
    Uint16 rsvd3:1;                     // 6 Reserved
    Uint16 rsvd4:1;                     // 7 Reserved
    Uint16 rsvd5:1;                     // 8 Reserved
    Uint16 rsvd6:1;                     // 9 Reserved
    Uint16 rsvd7:1;                     // 10 Reserved
    Uint16 OVF:1;                       // 11 Shadow OVF Flag
    Uint16 rsvd8:4;                     // 15:12 Reserved
};

union NMISHDFLG_REG {
    Uint16  all;
    struct  NMISHDFLG_BITS  bit;
};

struct NMI_INTRUPT_REGS {
    union   NMICFG_REG                       NMICFG;                       // NMI Configuration Register
    union   NMIFLG_REG                       NMIFLG;                       // NMI Flag Register (XRSn Clear)
    union   NMIFLGCLR_REG                    NMIFLGCLR;                    // NMI Flag Clear Register
    union   NMIFLGFRC_REG                    NMIFLGFRC;                    // NMI Flag Force Register
    Uint16                                   NMIWDCNT;                     // NMI Watchdog Counter Register
    Uint16                                   NMIWDPRD;                     // NMI Watchdog Period Register
    union   NMISHDFLG_REG                    NMISHDFLG;                    // NMI Shadow Flag Register
};

//---------------------------------------------------------------------------
// NMIINTRUPT External References & Function Declarations:
//
extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_output_xbar.h
//
// TITLE:   F2807x Device OUTPUT_XBAR Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// OUTPUT_XBAR Individual Register Bit Definitions:

struct OUTPUT1MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR
};

union OUTPUT1MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT1MUX0TO15CFG_BITS  bit;
};

struct OUTPUT1MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR
};

union OUTPUT1MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT1MUX16TO31CFG_BITS  bit;
};

struct OUTPUT2MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR
};

union OUTPUT2MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT2MUX0TO15CFG_BITS  bit;
};

struct OUTPUT2MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR
};

union OUTPUT2MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT2MUX16TO31CFG_BITS  bit;
};

struct OUTPUT3MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR
};

union OUTPUT3MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT3MUX0TO15CFG_BITS  bit;
};

struct OUTPUT3MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR
};

union OUTPUT3MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT3MUX16TO31CFG_BITS  bit;
};

struct OUTPUT4MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR
};

union OUTPUT4MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT4MUX0TO15CFG_BITS  bit;
};

struct OUTPUT4MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR
};

union OUTPUT4MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT4MUX16TO31CFG_BITS  bit;
};

struct OUTPUT5MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR
};

union OUTPUT5MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT5MUX0TO15CFG_BITS  bit;
};

struct OUTPUT5MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR
};

union OUTPUT5MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT5MUX16TO31CFG_BITS  bit;
};

struct OUTPUT6MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR
};

union OUTPUT6MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT6MUX0TO15CFG_BITS  bit;
};

struct OUTPUT6MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR
};

union OUTPUT6MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT6MUX16TO31CFG_BITS  bit;
};

struct OUTPUT7MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR
};

union OUTPUT7MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT7MUX0TO15CFG_BITS  bit;
};

struct OUTPUT7MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR
};

union OUTPUT7MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT7MUX16TO31CFG_BITS  bit;
};

struct OUTPUT8MUX0TO15CFG_BITS {        // bits description
    Uint16 MUX0:2;                      // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX1:2;                      // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX2:2;                      // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX3:2;                      // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX4:2;                      // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX5:2;                      // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX6:2;                      // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX7:2;                      // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX8:2;                      // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX9:2;                      // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX10:2;                     // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX11:2;                     // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX12:2;                     // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX13:2;                     // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX14:2;                     // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX15:2;                     // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR
};

union OUTPUT8MUX0TO15CFG_REG {
    Uint32  all;
    struct  OUTPUT8MUX0TO15CFG_BITS  bit;
};

struct OUTPUT8MUX16TO31CFG_BITS {       // bits description
    Uint16 MUX16:2;                     // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX17:2;                     // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX18:2;                     // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX19:2;                     // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX20:2;                     // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX21:2;                     // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX22:2;                     // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX23:2;                     // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX24:2;                     // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX25:2;                     // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX26:2;                     // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX27:2;                     // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX28:2;                     // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX29:2;                     // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX30:2;                     // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX31:2;                     // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR
};

union OUTPUT8MUX16TO31CFG_REG {
    Uint32  all;
    struct  OUTPUT8MUX16TO31CFG_BITS  bit;
};

struct OUTPUT1MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR
};

union OUTPUT1MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT1MUXENABLE_BITS  bit;
};

struct OUTPUT2MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR
};

union OUTPUT2MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT2MUXENABLE_BITS  bit;
};

struct OUTPUT3MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR
};

union OUTPUT3MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT3MUXENABLE_BITS  bit;
};

struct OUTPUT4MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR
};

union OUTPUT4MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT4MUXENABLE_BITS  bit;
};

struct OUTPUT5MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR
};

union OUTPUT5MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT5MUXENABLE_BITS  bit;
};

struct OUTPUT6MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR
};

union OUTPUT6MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT6MUXENABLE_BITS  bit;
};

struct OUTPUT7MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR
};

union OUTPUT7MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT7MUXENABLE_BITS  bit;
};

struct OUTPUT8MUXENABLE_BITS {          // bits description
    Uint16 MUX0:1;                      // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX1:1;                      // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX2:1;                      // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX3:1;                      // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX4:1;                      // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX5:1;                      // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX6:1;                      // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX7:1;                      // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX8:1;                      // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX9:1;                      // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX10:1;                     // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX11:1;                     // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX12:1;                     // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX13:1;                     // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX14:1;                     // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX15:1;                     // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX16:1;                     // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX17:1;                     // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX18:1;                     // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX19:1;                     // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX20:1;                     // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX21:1;                     // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX22:1;                     // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX23:1;                     // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX24:1;                     // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX25:1;                     // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX26:1;                     // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX27:1;                     // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX28:1;                     // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX29:1;                     // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX30:1;                     // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR
    Uint16 MUX31:1;                     // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR
};

union OUTPUT8MUXENABLE_REG {
    Uint32  all;
    struct  OUTPUT8MUXENABLE_BITS  bit;
};

struct OUTPUTLATCH_BITS {               // bits description
    Uint16 OUTPUT1:1;                   // 0 Records the OUTPUT1 of OUTPUT-XBAR
    Uint16 OUTPUT2:1;                   // 1 Records the OUTPUT2 of OUTPUT-XBAR
    Uint16 OUTPUT3:1;                   // 2 Records the OUTPUT3 of OUTPUT-XBAR
    Uint16 OUTPUT4:1;                   // 3 Records the OUTPUT4 of OUTPUT-XBAR
    Uint16 OUTPUT5:1;                   // 4 Records the OUTPUT5 of OUTPUT-XBAR
    Uint16 OUTPUT6:1;                   // 5 Records the OUTPUT6 of OUTPUT-XBAR
    Uint16 OUTPUT7:1;                   // 6 Records the OUTPUT7 of OUTPUT-XBAR
    Uint16 OUTPUT8:1;                   // 7 Records the OUTPUT8 of OUTPUT-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union OUTPUTLATCH_REG {
    Uint32  all;
    struct  OUTPUTLATCH_BITS  bit;
};

struct OUTPUTLATCHCLR_BITS {            // bits description
    Uint16 OUTPUT1:1;                   // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR
    Uint16 OUTPUT2:1;                   // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR
    Uint16 OUTPUT3:1;                   // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR
    Uint16 OUTPUT4:1;                   // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR
    Uint16 OUTPUT5:1;                   // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR
    Uint16 OUTPUT6:1;                   // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR
    Uint16 OUTPUT7:1;                   // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR
    Uint16 OUTPUT8:1;                   // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union OUTPUTLATCHCLR_REG {
    Uint32  all;
    struct  OUTPUTLATCHCLR_BITS  bit;
};

struct OUTPUTLATCHFRC_BITS {            // bits description
    Uint16 OUTPUT1:1;                   // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR
    Uint16 OUTPUT2:1;                   // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR
    Uint16 OUTPUT3:1;                   // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR
    Uint16 OUTPUT4:1;                   // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR
    Uint16 OUTPUT5:1;                   // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR
    Uint16 OUTPUT6:1;                   // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR
    Uint16 OUTPUT7:1;                   // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR
    Uint16 OUTPUT8:1;                   // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union OUTPUTLATCHFRC_REG {
    Uint32  all;
    struct  OUTPUTLATCHFRC_BITS  bit;
};

struct OUTPUTLATCHENABLE_BITS {         // bits description
    Uint16 OUTPUT1:1;                   // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR
    Uint16 OUTPUT2:1;                   // 1 Selects the output latch to drive output1 for OUTPUT-XBAR
    Uint16 OUTPUT3:1;                   // 2 Selects the output latch to drive output2 for OUTPUT-XBAR
    Uint16 OUTPUT4:1;                   // 3 Selects the output latch to drive output3 for OUTPUT-XBAR
    Uint16 OUTPUT5:1;                   // 4 Selects the output latch to drive output4 for OUTPUT-XBAR
    Uint16 OUTPUT6:1;                   // 5 Selects the output latch to drive output5 for OUTPUT-XBAR
    Uint16 OUTPUT7:1;                   // 6 Selects the output latch to drive output6 for OUTPUT-XBAR
    Uint16 OUTPUT8:1;                   // 7 Selects the output latch to drive output7 for OUTPUT-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union OUTPUTLATCHENABLE_REG {
    Uint32  all;
    struct  OUTPUTLATCHENABLE_BITS  bit;
};

struct OUTPUTINV_BITS {                 // bits description
    Uint16 OUTPUT1:1;                   // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR
    Uint16 OUTPUT2:1;                   // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR
    Uint16 OUTPUT3:1;                   // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR
    Uint16 OUTPUT4:1;                   // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR
    Uint16 OUTPUT5:1;                   // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR
    Uint16 OUTPUT6:1;                   // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR
    Uint16 OUTPUT7:1;                   // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR
    Uint16 OUTPUT8:1;                   // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union OUTPUTINV_REG {
    Uint32  all;
    struct  OUTPUTINV_BITS  bit;
};

struct OUTPUTLOCK_BITS {                // bits description
    Uint16 LOCK:1;                      // 0 Locks the configuration for OUTPUT-XBAR
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 KEY:16;                      // 31:16 Write Protection KEY
};

union OUTPUTLOCK_REG {
    Uint32  all;
    struct  OUTPUTLOCK_BITS  bit;
};

struct OUTPUT_XBAR_REGS {
    union   OUTPUT1MUX0TO15CFG_REG           OUTPUT1MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 1
    union   OUTPUT1MUX16TO31CFG_REG          OUTPUT1MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 1
    union   OUTPUT2MUX0TO15CFG_REG           OUTPUT2MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 2
    union   OUTPUT2MUX16TO31CFG_REG          OUTPUT2MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 2
    union   OUTPUT3MUX0TO15CFG_REG           OUTPUT3MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 3
    union   OUTPUT3MUX16TO31CFG_REG          OUTPUT3MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 3
    union   OUTPUT4MUX0TO15CFG_REG           OUTPUT4MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 4
    union   OUTPUT4MUX16TO31CFG_REG          OUTPUT4MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 4
    union   OUTPUT5MUX0TO15CFG_REG           OUTPUT5MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 5
    union   OUTPUT5MUX16TO31CFG_REG          OUTPUT5MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 5
    union   OUTPUT6MUX0TO15CFG_REG           OUTPUT6MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 6
    union   OUTPUT6MUX16TO31CFG_REG          OUTPUT6MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 6
    union   OUTPUT7MUX0TO15CFG_REG           OUTPUT7MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 7
    union   OUTPUT7MUX16TO31CFG_REG          OUTPUT7MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 7
    union   OUTPUT8MUX0TO15CFG_REG           OUTPUT8MUX0TO15CFG;           // Output X-BAR Mux Configuration for Output 8
    union   OUTPUT8MUX16TO31CFG_REG          OUTPUT8MUX16TO31CFG;          // Output X-BAR Mux Configuration for Output 8
    union   OUTPUT1MUXENABLE_REG             OUTPUT1MUXENABLE;             // Output X-BAR Mux Enable  for Output 1
    union   OUTPUT2MUXENABLE_REG             OUTPUT2MUXENABLE;             // Output X-BAR Mux Enable  for Output 2
    union   OUTPUT3MUXENABLE_REG             OUTPUT3MUXENABLE;             // Output X-BAR Mux Enable  for Output 3
    union   OUTPUT4MUXENABLE_REG             OUTPUT4MUXENABLE;             // Output X-BAR Mux Enable  for Output 4
    union   OUTPUT5MUXENABLE_REG             OUTPUT5MUXENABLE;             // Output X-BAR Mux Enable  for Output 5
    union   OUTPUT6MUXENABLE_REG             OUTPUT6MUXENABLE;             // Output X-BAR Mux Enable  for Output 6
    union   OUTPUT7MUXENABLE_REG             OUTPUT7MUXENABLE;             // Output X-BAR Mux Enable  for Output 7
    union   OUTPUT8MUXENABLE_REG             OUTPUT8MUXENABLE;             // Output X-BAR Mux Enable  for Output 8
    union   OUTPUTLATCH_REG                  OUTPUTLATCH;                  // Output X-BAR Output Latch 
    union   OUTPUTLATCHCLR_REG               OUTPUTLATCHCLR;               // Output X-BAR Output Latch Clear 
    union   OUTPUTLATCHFRC_REG               OUTPUTLATCHFRC;               // Output X-BAR Output Latch Clear 
    union   OUTPUTLATCHENABLE_REG            OUTPUTLATCHENABLE;            // Output X-BAR Output Latch Enable 
    union   OUTPUTINV_REG                    OUTPUTINV;                    // Output X-BAR Output Inversion 
    Uint16                                   rsvd1[4];                     // Reserved
    union   OUTPUTLOCK_REG                   OUTPUTLOCK;                   // Output X-BAR Configuration Lock register
};

//---------------------------------------------------------------------------
// OUTPUT_XBAR External References & Function Declarations:
//
extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_piectrl.h
//
// TITLE:   F2807x Device PIECTRL Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// PIECTRL Individual Register Bit Definitions:

struct PIECTRL_BITS {                   // bits description
    Uint16 ENPIE:1;                     // 0 PIE Enable
    Uint16 PIEVECT:15;                  // 15:1 PIE Vector Address
};

union PIECTRL_REG {
    Uint16  all;
    struct  PIECTRL_BITS  bit;
};

struct PIEACK_BITS {                    // bits description
    Uint16 ACK1:1;                      // 0 Acknowledge PIE Interrupt Group 1
    Uint16 ACK2:1;                      // 1 Acknowledge PIE Interrupt Group 2
    Uint16 ACK3:1;                      // 2 Acknowledge PIE Interrupt Group 3
    Uint16 ACK4:1;                      // 3 Acknowledge PIE Interrupt Group 4
    Uint16 ACK5:1;                      // 4 Acknowledge PIE Interrupt Group 5
    Uint16 ACK6:1;                      // 5 Acknowledge PIE Interrupt Group 6
    Uint16 ACK7:1;                      // 6 Acknowledge PIE Interrupt Group 7
    Uint16 ACK8:1;                      // 7 Acknowledge PIE Interrupt Group 8
    Uint16 ACK9:1;                      // 8 Acknowledge PIE Interrupt Group 9
    Uint16 ACK10:1;                     // 9 Acknowledge PIE Interrupt Group 10
    Uint16 ACK11:1;                     // 10 Acknowledge PIE Interrupt Group 11
    Uint16 ACK12:1;                     // 11 Acknowledge PIE Interrupt Group 12
    Uint16 rsvd1:4;                     // 15:12 Reserved
};

union PIEACK_REG {
    Uint16  all;
    struct  PIEACK_BITS  bit;
};

struct PIEIER1_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT1.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT1.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT1.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT1.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT1.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT1.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT1.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT1.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT1.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT1.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT1.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT1.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT1.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT1.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT1.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT1.16
};

union PIEIER1_REG {
    Uint16  all;
    struct  PIEIER1_BITS  bit;
};

struct PIEIFR1_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT1.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT1.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT1.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT1.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT1.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT1.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT1.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT1.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT1.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT1.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT1.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT1.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT1.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT1.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT1.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT1.16
};

union PIEIFR1_REG {
    Uint16  all;
    struct  PIEIFR1_BITS  bit;
};

struct PIEIER2_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT2.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT2.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT2.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT2.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT2.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT2.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT2.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT2.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT2.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT2.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT2.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT2.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT2.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT2.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT2.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT2.16
};

union PIEIER2_REG {
    Uint16  all;
    struct  PIEIER2_BITS  bit;
};

struct PIEIFR2_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT2.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT2.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT2.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT2.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT2.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT2.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT2.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT2.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT2.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT2.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT2.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT2.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT2.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT2.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT2.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT2.16
};

union PIEIFR2_REG {
    Uint16  all;
    struct  PIEIFR2_BITS  bit;
};

struct PIEIER3_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT3.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT3.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT3.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT3.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT3.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT3.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT3.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT3.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT3.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT3.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT3.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT3.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT3.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT3.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT3.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT3.16
};

union PIEIER3_REG {
    Uint16  all;
    struct  PIEIER3_BITS  bit;
};

struct PIEIFR3_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT3.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT3.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT3.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT3.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT3.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT3.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT3.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT3.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT3.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT3.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT3.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT3.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT3.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT3.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT3.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT3.16
};

union PIEIFR3_REG {
    Uint16  all;
    struct  PIEIFR3_BITS  bit;
};

struct PIEIER4_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT4.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT4.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT4.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT4.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT4.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT4.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT4.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT4.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT4.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT4.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT4.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT4.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT4.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT4.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT4.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT4.16
};

union PIEIER4_REG {
    Uint16  all;
    struct  PIEIER4_BITS  bit;
};

struct PIEIFR4_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT4.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT4.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT4.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT4.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT4.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT4.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT4.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT4.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT4.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT4.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT4.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT4.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT4.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT4.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT4.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT4.16
};

union PIEIFR4_REG {
    Uint16  all;
    struct  PIEIFR4_BITS  bit;
};

struct PIEIER5_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT5.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT5.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT5.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT5.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT5.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT5.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT5.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT5.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT5.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT5.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT5.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT5.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT5.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT5.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT5.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT5.16
};

union PIEIER5_REG {
    Uint16  all;
    struct  PIEIER5_BITS  bit;
};

struct PIEIFR5_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT5.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT5.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT5.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT5.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT5.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT5.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT5.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT5.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT5.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT5.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT5.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT5.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT5.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT5.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT5.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT5.16
};

union PIEIFR5_REG {
    Uint16  all;
    struct  PIEIFR5_BITS  bit;
};

struct PIEIER6_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT6.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT6.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT6.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT6.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT6.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT6.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT6.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT6.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT6.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT6.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT6.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT6.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT6.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT6.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT6.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT6.16
};

union PIEIER6_REG {
    Uint16  all;
    struct  PIEIER6_BITS  bit;
};

struct PIEIFR6_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT6.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT6.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT6.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT6.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT6.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT6.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT6.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT6.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT6.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT6.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT6.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT6.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT6.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT6.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT6.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT6.16
};

union PIEIFR6_REG {
    Uint16  all;
    struct  PIEIFR6_BITS  bit;
};

struct PIEIER7_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT7.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT7.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT7.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT7.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT7.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT7.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT7.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT7.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT7.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT7.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT7.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT7.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT7.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT7.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT7.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT7.16
};

union PIEIER7_REG {
    Uint16  all;
    struct  PIEIER7_BITS  bit;
};

struct PIEIFR7_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT7.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT7.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT7.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT7.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT7.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT7.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT7.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT7.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT7.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT7.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT7.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT7.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT7.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT7.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT7.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT7.16
};

union PIEIFR7_REG {
    Uint16  all;
    struct  PIEIFR7_BITS  bit;
};

struct PIEIER8_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT8.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT8.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT8.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT8.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT8.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT8.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT8.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT8.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT8.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT8.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT8.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT8.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT8.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT8.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT8.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT8.16
};

union PIEIER8_REG {
    Uint16  all;
    struct  PIEIER8_BITS  bit;
};

struct PIEIFR8_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT8.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT8.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT8.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT8.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT8.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT8.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT8.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT8.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT8.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT8.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT8.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT8.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT8.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT8.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT8.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT8.16
};

union PIEIFR8_REG {
    Uint16  all;
    struct  PIEIFR8_BITS  bit;
};

struct PIEIER9_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT9.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT9.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT9.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT9.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT9.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT9.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT9.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT9.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT9.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT9.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT9.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT9.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT9.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT9.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT9.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT9.16
};

union PIEIER9_REG {
    Uint16  all;
    struct  PIEIER9_BITS  bit;
};

struct PIEIFR9_BITS {                   // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT9.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT9.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT9.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT9.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT9.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT9.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT9.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT9.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT9.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT9.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT9.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT9.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT9.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT9.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT9.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT9.16
};

union PIEIFR9_REG {
    Uint16  all;
    struct  PIEIFR9_BITS  bit;
};

struct PIEIER10_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT10.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT10.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT10.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT10.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT10.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT10.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT10.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT10.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT10.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT10.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT10.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT10.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT10.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT10.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT10.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT10.16
};

union PIEIER10_REG {
    Uint16  all;
    struct  PIEIER10_BITS  bit;
};

struct PIEIFR10_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT10.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT10.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT10.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT10.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT10.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT10.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT10.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT10.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT10.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT10.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT10.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT10.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT10.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT10.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT10.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT10.16
};

union PIEIFR10_REG {
    Uint16  all;
    struct  PIEIFR10_BITS  bit;
};

struct PIEIER11_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT11.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT11.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT11.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT11.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT11.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT11.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT11.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT11.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT11.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT11.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT11.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT11.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT11.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT11.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT11.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT11.16
};

union PIEIER11_REG {
    Uint16  all;
    struct  PIEIER11_BITS  bit;
};

struct PIEIFR11_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT11.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT11.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT11.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT11.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT11.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT11.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT11.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT11.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT11.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT11.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT11.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT11.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT11.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT11.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT11.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT11.16
};

union PIEIFR11_REG {
    Uint16  all;
    struct  PIEIFR11_BITS  bit;
};

struct PIEIER12_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Enable for INT12.1
    Uint16 INTx2:1;                     // 1 Interrupt Enable for INT12.2
    Uint16 INTx3:1;                     // 2 Interrupt Enable for INT12.3
    Uint16 INTx4:1;                     // 3 Interrupt Enable for INT12.4
    Uint16 INTx5:1;                     // 4 Interrupt Enable for INT12.5
    Uint16 INTx6:1;                     // 5 Interrupt Enable for INT12.6
    Uint16 INTx7:1;                     // 6 Interrupt Enable for INT12.7
    Uint16 INTx8:1;                     // 7 Interrupt Enable for INT12.8
    Uint16 INTx9:1;                     // 8 Interrupt Enable for INT12.9
    Uint16 INTx10:1;                    // 9 Interrupt Enable for INT12.10
    Uint16 INTx11:1;                    // 10 Interrupt Enable for INT12.11
    Uint16 INTx12:1;                    // 11 Interrupt Enable for INT12.12
    Uint16 INTx13:1;                    // 12 Interrupt Enable for INT12.13
    Uint16 INTx14:1;                    // 13 Interrupt Enable for INT12.14
    Uint16 INTx15:1;                    // 14 Interrupt Enable for INT12.15
    Uint16 INTx16:1;                    // 15 Interrupt Enable for INT12.16
};

union PIEIER12_REG {
    Uint16  all;
    struct  PIEIER12_BITS  bit;
};

struct PIEIFR12_BITS {                  // bits description
    Uint16 INTx1:1;                     // 0 Interrupt Flag for INT12.1
    Uint16 INTx2:1;                     // 1 Interrupt Flag for INT12.2
    Uint16 INTx3:1;                     // 2 Interrupt Flag for INT12.3
    Uint16 INTx4:1;                     // 3 Interrupt Flag for INT12.4
    Uint16 INTx5:1;                     // 4 Interrupt Flag for INT12.5
    Uint16 INTx6:1;                     // 5 Interrupt Flag for INT12.6
    Uint16 INTx7:1;                     // 6 Interrupt Flag for INT12.7
    Uint16 INTx8:1;                     // 7 Interrupt Flag for INT12.8
    Uint16 INTx9:1;                     // 8 Interrupt Flag for INT12.9
    Uint16 INTx10:1;                    // 9 Interrupt Flag for INT12.10
    Uint16 INTx11:1;                    // 10 Interrupt Flag for INT12.11
    Uint16 INTx12:1;                    // 11 Interrupt Flag for INT12.12
    Uint16 INTx13:1;                    // 12 Interrupt Flag for INT12.13
    Uint16 INTx14:1;                    // 13 Interrupt Flag for INT12.14
    Uint16 INTx15:1;                    // 14 Interrupt Flag for INT12.15
    Uint16 INTx16:1;                    // 15 Interrupt Flag for INT12.16
};

union PIEIFR12_REG {
    Uint16  all;
    struct  PIEIFR12_BITS  bit;
};

struct PIE_CTRL_REGS {
    union   PIECTRL_REG                      PIECTRL;                      // Control Register
    union   PIEACK_REG                       PIEACK;                       // Acknowledge Register
    union   PIEIER1_REG                      PIEIER1;                      // INT1 Group Enable Register
    union   PIEIFR1_REG                      PIEIFR1;                      // INT1 Group Flag Register
    union   PIEIER2_REG                      PIEIER2;                      // INT2 Group Enable Register
    union   PIEIFR2_REG                      PIEIFR2;                      // INT2 Group Flag Register
    union   PIEIER3_REG                      PIEIER3;                      // INT3 Group Enable Register
    union   PIEIFR3_REG                      PIEIFR3;                      // INT3 Group Flag Register
    union   PIEIER4_REG                      PIEIER4;                      // INT4 Group Enable Register
    union   PIEIFR4_REG                      PIEIFR4;                      // INT4 Group Flag Register
    union   PIEIER5_REG                      PIEIER5;                      // INT5 Group Enable Register
    union   PIEIFR5_REG                      PIEIFR5;                      // INT5 Group Flag Register
    union   PIEIER6_REG                      PIEIER6;                      // INT6 Group Enable Register
    union   PIEIFR6_REG                      PIEIFR6;                      // INT6 Group Flag Register
    union   PIEIER7_REG                      PIEIER7;                      // INT7 Group Enable Register
    union   PIEIFR7_REG                      PIEIFR7;                      // INT7 Group Flag Register
    union   PIEIER8_REG                      PIEIER8;                      // INT8 Group Enable Register
    union   PIEIFR8_REG                      PIEIFR8;                      // INT8 Group Flag Register
    union   PIEIER9_REG                      PIEIER9;                      // INT9 Group Enable Register
    union   PIEIFR9_REG                      PIEIFR9;                      // INT9 Group Flag Register
    union   PIEIER10_REG                     PIEIER10;                     // INT10 Group Enable Register
    union   PIEIFR10_REG                     PIEIFR10;                     // INT10 Group Flag Register
    union   PIEIER11_REG                     PIEIER11;                     // INT11 Group Enable Register
    union   PIEIFR11_REG                     PIEIFR11;                     // INT11 Group Flag Register
    union   PIEIER12_REG                     PIEIER12;                     // INT12 Group Enable Register
    union   PIEIFR12_REG                     PIEIFR12;                     // INT12 Group Flag Register
};

//---------------------------------------------------------------------------
// PIECTRL External References & Function Declarations:
//
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_pievect.h
//
// TITLE:  F2807x Device PIE Vector Table Definitions
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

extern "C" {

//---------------------------------------------------------------------------
// PIE Interrupt Vector Table Definition:
// Create a user type called PINT (pointer to interrupt):

typedef __interrupt void (*PINT)(void);

// Define Vector Table:
struct PIE_VECT_TABLE {
    PINT  PIE1_RESERVED_INT;                          // Reserved 
    PINT  PIE2_RESERVED_INT;                          // Reserved 
    PINT  PIE3_RESERVED_INT;                          // Reserved 
    PINT  PIE4_RESERVED_INT;                          // Reserved 
    PINT  PIE5_RESERVED_INT;                          // Reserved 
    PINT  PIE6_RESERVED_INT;                          // Reserved 
    PINT  PIE7_RESERVED_INT;                          // Reserved 
    PINT  PIE8_RESERVED_INT;                          // Reserved 
    PINT  PIE9_RESERVED_INT;                          // Reserved 
    PINT  PIE10_RESERVED_INT;                         // Reserved 
    PINT  PIE11_RESERVED_INT;                         // Reserved 
    PINT  PIE12_RESERVED_INT;                         // Reserved 
    PINT  PIE13_RESERVED_INT;                         // Reserved 
    PINT  TIMER1_INT;                                 // CPU Timer 1 Interrupt 
    PINT  TIMER2_INT;                                 // CPU Timer 2 Interrupt 
    PINT  DATALOG_INT;                                // Datalogging Interrupt 
    PINT  RTOS_INT;                                   // RTOS Interrupt 
    PINT  EMU_INT;                                    // Emulation Interrupt 
    PINT  NMI_INT;                                    // Non-Maskable Interrupt 
    PINT  ILLEGAL_INT;                                // Illegal Operation Trap 
    PINT  USER1_INT;                                  // User Defined Trap 1 
    PINT  USER2_INT;                                  // User Defined Trap 2 
    PINT  USER3_INT;                                  // User Defined Trap 3 
    PINT  USER4_INT;                                  // User Defined Trap 4 
    PINT  USER5_INT;                                  // User Defined Trap 5 
    PINT  USER6_INT;                                  // User Defined Trap 6 
    PINT  USER7_INT;                                  // User Defined Trap 7 
    PINT  USER8_INT;                                  // User Defined Trap 8 
    PINT  USER9_INT;                                  // User Defined Trap 9 
    PINT  USER10_INT;                                 // User Defined Trap 10 
    PINT  USER11_INT;                                 // User Defined Trap 11 
    PINT  USER12_INT;                                 // User Defined Trap 12 
    PINT  ADCA1_INT;                                  // 1.1 - ADCA Interrupt 1 
    PINT  ADCB1_INT;                                  // 1.2 - ADCB Interrupt 1 
    PINT  PIE14_RESERVED_INT;                         // 1.3 - Reserved 
    PINT  XINT1_INT;                                  // 1.4 - XINT1 Interrupt 
    PINT  XINT2_INT;                                  // 1.5 - XINT2 Interrupt 
    PINT  ADCD1_INT;                                  // 1.6 - ADCD Interrupt 1 
    PINT  TIMER0_INT;                                 // 1.7 - Timer 0 Interrupt 
    PINT  WAKE_INT;                                   // 1.8 - Standby and Halt Wakeup Interrupt 
    PINT  EPWM1_TZ_INT;                               // 2.1 - ePWM1 Trip Zone Interrupt 
    PINT  EPWM2_TZ_INT;                               // 2.2 - ePWM2 Trip Zone Interrupt 
    PINT  EPWM3_TZ_INT;                               // 2.3 - ePWM3 Trip Zone Interrupt 
    PINT  EPWM4_TZ_INT;                               // 2.4 - ePWM4 Trip Zone Interrupt 
    PINT  EPWM5_TZ_INT;                               // 2.5 - ePWM5 Trip Zone Interrupt 
    PINT  EPWM6_TZ_INT;                               // 2.6 - ePWM6 Trip Zone Interrupt 
    PINT  EPWM7_TZ_INT;                               // 2.7 - ePWM7 Trip Zone Interrupt 
    PINT  EPWM8_TZ_INT;                               // 2.8 - ePWM8 Trip Zone Interrupt 
    PINT  EPWM1_INT;                                  // 3.1 - ePWM1 Interrupt 
    PINT  EPWM2_INT;                                  // 3.2 - ePWM2 Interrupt 
    PINT  EPWM3_INT;                                  // 3.3 - ePWM3 Interrupt 
    PINT  EPWM4_INT;                                  // 3.4 - ePWM4 Interrupt 
    PINT  EPWM5_INT;                                  // 3.5 - ePWM5 Interrupt 
    PINT  EPWM6_INT;                                  // 3.6 - ePWM6 Interrupt 
    PINT  EPWM7_INT;                                  // 3.7 - ePWM7 Interrupt 
    PINT  EPWM8_INT;                                  // 3.8 - ePWM8 Interrupt 
    PINT  ECAP1_INT;                                  // 4.1 - eCAP1 Interrupt 
    PINT  ECAP2_INT;                                  // 4.2 - eCAP2 Interrupt 
    PINT  ECAP3_INT;                                  // 4.3 - eCAP3 Interrupt 
    PINT  ECAP4_INT;                                  // 4.4 - eCAP4 Interrupt 
    PINT  ECAP5_INT;                                  // 4.5 - eCAP5 Interrupt 
    PINT  ECAP6_INT;                                  // 4.6 - eCAP6 Interrupt 
    PINT  PIE15_RESERVED_INT;                         // 4.7 - Reserved 
    PINT  PIE16_RESERVED_INT;                         // 4.8 - Reserved 
    PINT  EQEP1_INT;                                  // 5.1 - eQEP1 Interrupt 
    PINT  EQEP2_INT;                                  // 5.2 - eQEP2 Interrupt 
    PINT  EQEP3_INT;                                  // 5.3 - eQEP3 Interrupt 
    PINT  PIE17_RESERVED_INT;                         // 5.4 - Reserved 
    PINT  PIE18_RESERVED_INT;                         // 5.5 - Reserved 
    PINT  PIE19_RESERVED_INT;                         // 5.6 - Reserved 
    PINT  PIE20_RESERVED_INT;                         // 5.7 - Reserved 
    PINT  PIE21_RESERVED_INT;                         // 5.8 - Reserved 
    PINT  SPIA_RX_INT;                                // 6.1 - SPIA Receive Interrupt 
    PINT  SPIA_TX_INT;                                // 6.2 - SPIA Transmit Interrupt 
    PINT  SPIB_RX_INT;                                // 6.3 - SPIB Receive Interrupt 
    PINT  SPIB_TX_INT;                                // 6.4 - SPIB Transmit Interrupt 
    PINT  MCBSPA_RX_INT;                              // 6.5 - McBSPA Receive Interrupt 
    PINT  MCBSPA_TX_INT;                              // 6.6 - McBSPA Transmit Interrupt 
    PINT  MCBSPB_RX_INT;                              // 6.7 - McBSPB Receive Interrupt 
    PINT  MCBSPB_TX_INT;                              // 6.8 - McBSPB Transmit Interrupt 
    PINT  DMA_CH1_INT;                                // 7.1 - DMA Channel 1 Interrupt 
    PINT  DMA_CH2_INT;                                // 7.2 - DMA Channel 2 Interrupt 
    PINT  DMA_CH3_INT;                                // 7.3 - DMA Channel 3 Interrupt 
    PINT  DMA_CH4_INT;                                // 7.4 - DMA Channel 4 Interrupt 
    PINT  DMA_CH5_INT;                                // 7.5 - DMA Channel 5 Interrupt 
    PINT  DMA_CH6_INT;                                // 7.6 - DMA Channel 6 Interrupt 
    PINT  PIE22_RESERVED_INT;                         // 7.7 - Reserved 
    PINT  PIE23_RESERVED_INT;                         // 7.8 - Reserved 
    PINT  I2CA_INT;                                   // 8.1 - I2CA Interrupt 1 
    PINT  I2CA_FIFO_INT;                              // 8.2 - I2CA Interrupt 2 
    PINT  I2CB_INT;                                   // 8.3 - I2CB Interrupt 1 
    PINT  I2CB_FIFO_INT;                              // 8.4 - I2CB Interrupt 2 
    PINT  SCIC_RX_INT;                                // 8.5 - SCIC Receive Interrupt 
    PINT  SCIC_TX_INT;                                // 8.6 - SCIC Transmit Interrupt 
    PINT  SCID_RX_INT;                                // 8.7 - SCID Receive Interrupt 
    PINT  SCID_TX_INT;                                // 8.8 - SCID Transmit Interrupt 
    PINT  SCIA_RX_INT;                                // 9.1 - SCIA Receive Interrupt 
    PINT  SCIA_TX_INT;                                // 9.2 - SCIA Transmit Interrupt 
    PINT  SCIB_RX_INT;                                // 9.3 - SCIB Receive Interrupt 
    PINT  SCIB_TX_INT;                                // 9.4 - SCIB Transmit Interrupt 
    PINT  CANA0_INT;                                  // 9.5 - CANA Interrupt 0 
    PINT  CANA1_INT;                                  // 9.6 - CANA Interrupt 1 
    PINT  CANB0_INT;                                  // 9.7 - CANB Interrupt 0 
    PINT  CANB1_INT;                                  // 9.8 - CANB Interrupt 1 
    PINT  ADCA_EVT_INT;                               // 10.1 - ADCA Event Interrupt 
    PINT  ADCA2_INT;                                  // 10.2 - ADCA Interrupt 2 
    PINT  ADCA3_INT;                                  // 10.3 - ADCA Interrupt 3 
    PINT  ADCA4_INT;                                  // 10.4 - ADCA Interrupt 4 
    PINT  ADCB_EVT_INT;                               // 10.5 - ADCB Event Interrupt 
    PINT  ADCB2_INT;                                  // 10.6 - ADCB Interrupt 2 
    PINT  ADCB3_INT;                                  // 10.7 - ADCB Interrupt 3 
    PINT  ADCB4_INT;                                  // 10.8 - ADCB Interrupt 4 
    PINT  CLA1_1_INT;                                 // 11.1 - CLA1 Interrupt 1 
    PINT  CLA1_2_INT;                                 // 11.2 - CLA1 Interrupt 2 
    PINT  CLA1_3_INT;                                 // 11.3 - CLA1 Interrupt 3 
    PINT  CLA1_4_INT;                                 // 11.4 - CLA1 Interrupt 4 
    PINT  CLA1_5_INT;                                 // 11.5 - CLA1 Interrupt 5 
    PINT  CLA1_6_INT;                                 // 11.6 - CLA1 Interrupt 6 
    PINT  CLA1_7_INT;                                 // 11.7 - CLA1 Interrupt 7 
    PINT  CLA1_8_INT;                                 // 11.8 - CLA1 Interrupt 8 
    PINT  XINT3_INT;                                  // 12.1 - XINT3 Interrupt 
    PINT  XINT4_INT;                                  // 12.2 - XINT4 Interrupt 
    PINT  XINT5_INT;                                  // 12.3 - XINT5 Interrupt 
    PINT  PIE24_RESERVED_INT;                         // 12.4 - Reserved 
    PINT  PIE25_RESERVED_INT;                         // 12.5 - Reserved 
    PINT  VCU_INT;                                    // 12.6 - VCU Interrupt 
    PINT  FPU_OVERFLOW_INT;                           // 12.7 - FPU Overflow Interrupt 
    PINT  FPU_UNDERFLOW_INT;                          // 12.8 - FPU Underflow Interrupt 
    PINT  PIE26_RESERVED_INT;                         // 1.9 - Reserved 
    PINT  PIE27_RESERVED_INT;                         // 1.10 - Reserved 
    PINT  PIE28_RESERVED_INT;                         // 1.11 - Reserved 
    PINT  PIE29_RESERVED_INT;                         // 1.12 - Reserved 
    PINT  IPC0_INT;                                   // 1.13 - IPC Interrupt 0 
    PINT  IPC1_INT;                                   // 1.14 - IPC Interrupt 1 
    PINT  IPC2_INT;                                   // 1.15 - IPC Interrupt 2 
    PINT  IPC3_INT;                                   // 1.16 - IPC Interrupt 3 
    PINT  EPWM9_TZ_INT;                               // 2.9 - ePWM9 Trip Zone Interrupt 
    PINT  EPWM10_TZ_INT;                              // 2.10 - ePWM10 Trip Zone Interrupt 
    PINT  EPWM11_TZ_INT;                              // 2.11 - ePWM11 Trip Zone Interrupt 
    PINT  EPWM12_TZ_INT;                              // 2.12 - ePWM12 Trip Zone Interrupt 
    PINT  PIE30_RESERVED_INT;                         // 2.13 - Reserved 
    PINT  PIE31_RESERVED_INT;                         // 2.14 - Reserved 
    PINT  PIE32_RESERVED_INT;                         // 2.15 - Reserved 
    PINT  PIE33_RESERVED_INT;                         // 2.16 - Reserved 
    PINT  EPWM9_INT;                                  // 3.9 - ePWM9 Interrupt 
    PINT  EPWM10_INT;                                 // 3.10 - ePWM10 Interrupt 
    PINT  EPWM11_INT;                                 // 3.11 - ePWM11 Interrupt 
    PINT  EPWM12_INT;                                 // 3.12 - ePWM12 Interrupt 
    PINT  PIE34_RESERVED_INT;                         // 3.13 - Reserved 
    PINT  PIE35_RESERVED_INT;                         // 3.14 - Reserved 
    PINT  PIE36_RESERVED_INT;                         // 3.15 - Reserved 
    PINT  PIE37_RESERVED_INT;                         // 3.16 - Reserved 
    PINT  PIE38_RESERVED_INT;                         // 4.9 - Reserved 
    PINT  PIE39_RESERVED_INT;                         // 4.10 - Reserved 
    PINT  PIE40_RESERVED_INT;                         // 4.11 - Reserved 
    PINT  PIE41_RESERVED_INT;                         // 4.12 - Reserved 
    PINT  PIE42_RESERVED_INT;                         // 4.13 - Reserved 
    PINT  PIE43_RESERVED_INT;                         // 4.14 - Reserved 
    PINT  PIE44_RESERVED_INT;                         // 4.15 - Reserved 
    PINT  PIE45_RESERVED_INT;                         // 4.16 - Reserved 
    PINT  SD1_INT;                                    // 5.9 - SD1 Interrupt 
    PINT  SD2_INT;                                    // 5.10 - SD2 Interrupt 
    PINT  PIE46_RESERVED_INT;                         // 5.11 - Reserved 
    PINT  PIE47_RESERVED_INT;                         // 5.12 - Reserved 
    PINT  PIE48_RESERVED_INT;                         // 5.13 - Reserved 
    PINT  PIE49_RESERVED_INT;                         // 5.14 - Reserved 
    PINT  PIE50_RESERVED_INT;                         // 5.15 - Reserved 
    PINT  PIE51_RESERVED_INT;                         // 5.16 - Reserved 
    PINT  SPIC_RX_INT;                                // 6.9 - SPIC Receive Interrupt 
    PINT  SPIC_TX_INT;                                // 6.10 - SPIC Transmit Interrupt 
    PINT  PIE52_RESERVED_INT;                         // 6.11 - Reserved 
    PINT  PIE53_RESERVED_INT;                         // 6.12 - Reserved 
    PINT  PIE54_RESERVED_INT;                         // 6.13 - Reserved 
    PINT  PIE55_RESERVED_INT;                         // 6.14 - Reserved 
    PINT  PIE56_RESERVED_INT;                         // 6.15 - Reserved 
    PINT  PIE57_RESERVED_INT;                         // 6.16 - Reserved 
    PINT  PIE58_RESERVED_INT;                         // 7.9 - Reserved 
    PINT  PIE59_RESERVED_INT;                         // 7.10 - Reserved 
    PINT  PIE60_RESERVED_INT;                         // 7.11 - Reserved 
    PINT  PIE61_RESERVED_INT;                         // 7.12 - Reserved 
    PINT  PIE62_RESERVED_INT;                         // 7.13 - Reserved 
    PINT  PIE63_RESERVED_INT;                         // 7.14 - Reserved 
    PINT  PIE64_RESERVED_INT;                         // 7.15 - Reserved 
    PINT  PIE65_RESERVED_INT;                         // 7.16 - Reserved 
    PINT  PIE66_RESERVED_INT;                         // 8.9 - Reserved 
    PINT  PIE67_RESERVED_INT;                         // 8.10 - Reserved 
    PINT  PIE68_RESERVED_INT;                         // 8.11 - Reserved 
    PINT  PIE69_RESERVED_INT;                         // 8.12 - Reserved 
    PINT  PIE70_RESERVED_INT;                         // 8.13 - Reserved 
    PINT  PIE71_RESERVED_INT;                         // 8.14 - Reserved 
    PINT  PIE72_RESERVED_INT;                         // 8.15 - Reserved 
    PINT  PIE73_RESERVED_INT;                         // 8.16 - Reserved 
    PINT  PIE74_RESERVED_INT;                         // 9.9 - Reserved 
    PINT  PIE75_RESERVED_INT;                         // 9.10 - Reserved 
    PINT  PIE76_RESERVED_INT;                         // 9.11 - Reserved 
    PINT  PIE77_RESERVED_INT;                         // 9.12 - Reserved 
    PINT  PIE78_RESERVED_INT;                         // 9.13 - Reserved 
    PINT  PIE79_RESERVED_INT;                         // 9.14 - Reserved 
    PINT  USBA_INT;                                   // 9.15 - USBA Interrupt 
    PINT  PIE80_RESERVED_INT;                         // 9.16 - Reserved 
    PINT  PIE81_RESERVED_INT;                         // 10.9 - Reserved 
    PINT  PIE82_RESERVED_INT;                         // 10.10 - Reserved 
    PINT  PIE83_RESERVED_INT;                         // 10.11 - Reserved 
    PINT  PIE84_RESERVED_INT;                         // 10.12 - Reserved 
    PINT  ADCD_EVT_INT;                               // 10.13 - ADCD Event Interrupt 
    PINT  ADCD2_INT;                                  // 10.14 - ADCD Interrupt 2 
    PINT  ADCD3_INT;                                  // 10.15 - ADCD Interrupt 3 
    PINT  ADCD4_INT;                                  // 10.16 - ADCD Interrupt 4 
    PINT  PIE85_RESERVED_INT;                         // 11.9 - Reserved 
    PINT  PIE86_RESERVED_INT;                         // 11.10 - Reserved 
    PINT  PIE87_RESERVED_INT;                         // 11.11 - Reserved 
    PINT  PIE88_RESERVED_INT;                         // 11.12 - Reserved 
    PINT  PIE89_RESERVED_INT;                         // 11.13 - Reserved 
    PINT  PIE90_RESERVED_INT;                         // 11.14 - Reserved 
    PINT  PIE91_RESERVED_INT;                         // 11.15 - Reserved 
    PINT  PIE92_RESERVED_INT;                         // 11.16 - Reserved 
    PINT  EMIF_ERROR_INT;                             // 12.9 - EMIF Error Interrupt 
    PINT  RAM_CORRECTABLE_ERROR_INT;                  // 12.10 - RAM Correctable Error Interrupt 
    PINT  FLASH_CORRECTABLE_ERROR_INT;                // 12.11 - Flash Correctable Error Interrupt 
    PINT  RAM_ACCESS_VIOLATION_INT;                   // 12.12 - RAM Access Violation Interrupt 
    PINT  SYS_PLL_SLIP_INT;                           // 12.13 - System PLL Slip Interrupt 
    PINT  AUX_PLL_SLIP_INT;                           // 12.14 - Auxiliary PLL Slip Interrupt 
    PINT  CLA_OVERFLOW_INT;                           // 12.15 - CLA Overflow Interrupt 
    PINT  CLA_UNDERFLOW_INT;                          // 12.16 - CLA Underflow Interrupt 
};

//---------------------------------------------------------------------------
// PieVect External References & Function Declarations:
//

extern volatile struct PIE_VECT_TABLE PieVectTable;

}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_sci.h
//
// TITLE:   F2807x Device SCI Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// SCI Individual Register Bit Definitions:

struct SCICCR_BITS {                    // bits description
    Uint16 SCICHAR:3;                   // 2:0 Character length control 
    Uint16 ADDRIDLE_MODE:1;             // 3 ADDR/IDLE Mode control 
    Uint16 LOOPBKENA:1;                 // 4 Loop Back enable
    Uint16 PARITYENA:1;                 // 5 Parity enable 
    Uint16 PARITY:1;                    // 6 Even or Odd Parity 
    Uint16 STOPBITS:1;                  // 7 Number of Stop Bits 
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SCICCR_REG {
    Uint16  all;
    struct  SCICCR_BITS  bit;
};

struct SCICTL1_BITS {                   // bits description
    Uint16 RXENA:1;                     // 0 SCI receiver enable 
    Uint16 TXENA:1;                     // 1 SCI transmitter enable 
    Uint16 SLEEP:1;                     // 2 SCI sleep 
    Uint16 TXWAKE:1;                    // 3 Transmitter wakeup method 
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 SWRESET:1;                   // 5 Software reset 
    Uint16 RXERRINTENA:1;               // 6 Recieve __interrupt enable 
    Uint16 rsvd2:9;                     // 15:7 Reserved
};

union SCICTL1_REG {
    Uint16  all;
    struct  SCICTL1_BITS  bit;
};

struct SCIHBAUD_BITS {                  // bits description
    Uint16 BAUD:8;                      // 7:0 SCI 16-bit baud selection Registers SCIHBAUD
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SCIHBAUD_REG {
    Uint16  all;
    struct  SCIHBAUD_BITS  bit;
};

struct SCILBAUD_BITS {                  // bits description
    Uint16 BAUD:8;                      // 7:0 SCI 16-bit baud selection Registers SCILBAUD
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SCILBAUD_REG {
    Uint16  all;
    struct  SCILBAUD_BITS  bit;
};

struct SCICTL2_BITS {                   // bits description
    Uint16 TXINTENA:1;                  // 0 Transmit __interrupt enable 
    Uint16 RXBKINTENA:1;                // 1 Receiver-buffer break enable 
    Uint16 rsvd1:4;                     // 5:2 Reserved
    Uint16 TXEMPTY:1;                   // 6 Transmitter empty flag 
    Uint16 TXRDY:1;                     // 7 Transmitter ready flag 
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union SCICTL2_REG {
    Uint16  all;
    struct  SCICTL2_BITS  bit;
};

struct SCIRXST_BITS {                   // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 RXWAKE:1;                    // 1 Receiver wakeup detect flag 
    Uint16 PE:1;                        // 2 Parity error flag 
    Uint16 OE:1;                        // 3 Overrun error flag
    Uint16 FE:1;                        // 4 Framing error flag 
    Uint16 BRKDT:1;                     // 5 Break-detect flag 
    Uint16 RXRDY:1;                     // 6 Receiver ready flag 
    Uint16 RXERROR:1;                   // 7 Receiver error flag 
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union SCIRXST_REG {
    Uint16  all;
    struct  SCIRXST_BITS  bit;
};

struct SCIRXEMU_BITS {                  // bits description
    Uint16 ERXDT:8;                     // 7:0 Receive emulation buffer data
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SCIRXEMU_REG {
    Uint16  all;
    struct  SCIRXEMU_BITS  bit;
};

struct SCIRXBUF_BITS {                  // bits description
    Uint16 SAR:8;                       // 7:0 Receive Character bits
    Uint16 rsvd1:6;                     // 13:8 Reserved
    Uint16 SCIFFPE:1;                   // 14 Receiver error flag 
    Uint16 SCIFFFE:1;                   // 15 Receiver error flag 
};

union SCIRXBUF_REG {
    Uint16  all;
    struct  SCIRXBUF_BITS  bit;
};

struct SCITXBUF_BITS {                  // bits description
    Uint16 TXDT:8;                      // 7:0 Transmit data buffer
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SCITXBUF_REG {
    Uint16  all;
    struct  SCITXBUF_BITS  bit;
};

struct SCIFFTX_BITS {                   // bits description
    Uint16 TXFFIL:5;                    // 4:0 Interrupt level 
    Uint16 TXFFIENA:1;                  // 5 Interrupt enable 
    Uint16 TXFFINTCLR:1;                // 6 Clear INT flag 
    Uint16 TXFFINT:1;                   // 7 INT flag
    Uint16 TXFFST:5;                    // 12:8 FIFO status 
    Uint16 TXFIFORESET:1;               // 13 FIFO reset 
    Uint16 SCIFFENA:1;                  // 14 Enhancement enable 
    Uint16 SCIRST:1;                    // 15 SCI reset rx/tx channels 
};

union SCIFFTX_REG {
    Uint16  all;
    struct  SCIFFTX_BITS  bit;
};

struct SCIFFRX_BITS {                   // bits description
    Uint16 RXFFIL:5;                    // 4:0 Interrupt level 
    Uint16 RXFFIENA:1;                  // 5 Interrupt enable 
    Uint16 RXFFINTCLR:1;                // 6 Clear INT flag 
    Uint16 RXFFINT:1;                   // 7 INT flag 
    Uint16 RXFFST:5;                    // 12:8 FIFO status 
    Uint16 RXFIFORESET:1;               // 13 FIFO reset 
    Uint16 RXFFOVRCLR:1;                // 14 Clear overflow 
    Uint16 RXFFOVF:1;                   // 15 FIFO overflow 
};

union SCIFFRX_REG {
    Uint16  all;
    struct  SCIFFRX_BITS  bit;
};

struct SCIFFCT_BITS {                   // bits description
    Uint16 FFTXDLY:8;                   // 7:0 FIFO transmit delay 
    Uint16 rsvd1:5;                     // 12:8 Reserved
    Uint16 CDC:1;                       // 13 Auto baud mode enable 
    Uint16 ABDCLR:1;                    // 14 Auto baud clear 
    Uint16 ABD:1;                       // 15 Auto baud detect 
};

union SCIFFCT_REG {
    Uint16  all;
    struct  SCIFFCT_BITS  bit;
};

struct SCIPRI_BITS {                    // bits description
    Uint16 rsvd1:3;                     // 2:0 Reserved
    Uint16 FREESOFT:2;                  // 4:3 Emulation modes 
    Uint16 rsvd2:3;                     // 7:5 Reserved
    Uint16 rsvd3:8;                     // 15:8 Reserved
};

union SCIPRI_REG {
    Uint16  all;
    struct  SCIPRI_BITS  bit;
};

struct SCI_REGS {
    union   SCICCR_REG                       SCICCR;                       // Communications control register
    union   SCICTL1_REG                      SCICTL1;                      // Control register 1
    union   SCIHBAUD_REG                     SCIHBAUD;                     // Baud rate (high) register
    union   SCILBAUD_REG                     SCILBAUD;                     // Baud rate (low) register
    union   SCICTL2_REG                      SCICTL2;                      // Control register 2
    union   SCIRXST_REG                      SCIRXST;                      // Recieve status register
    union   SCIRXEMU_REG                     SCIRXEMU;                     // Recieve emulation buffer register
    union   SCIRXBUF_REG                     SCIRXBUF;                     // Recieve data buffer
    Uint16                                   rsvd1;                        // Reserved
    union   SCITXBUF_REG                     SCITXBUF;                     // Transmit data buffer
    union   SCIFFTX_REG                      SCIFFTX;                      // FIFO transmit register
    union   SCIFFRX_REG                      SCIFFRX;                      // FIFO recieve register
    union   SCIFFCT_REG                      SCIFFCT;                      // FIFO control register
    Uint16                                   rsvd2[2];                     // Reserved
    union   SCIPRI_REG                       SCIPRI;                       // SCI Priority control
};

//---------------------------------------------------------------------------
// SCI External References & Function Declarations:
//
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
extern volatile struct SCI_REGS ScicRegs;
extern volatile struct SCI_REGS ScidRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_sdfm.h
//
// TITLE:   F2807x Device SDFM Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// SDFM Individual Register Bit Definitions:

struct SDIFLG_BITS {                    // bits description
    Uint16 IFH1:1;                      // 0 High-level Interrupt flag Filter 1
    Uint16 IFL1:1;                      // 1 Low-Level Interrupt flag Filter 1
    Uint16 IFH2:1;                      // 2 High-level Interrupt flag Filter 2
    Uint16 IFL2:1;                      // 3 Low-Level Interrupt flag Filter 2
    Uint16 IFH3:1;                      // 4 High-level Interrupt flag Filter 3
    Uint16 IFL3:1;                      // 5 Low-Level Interrupt flag Filter 3
    Uint16 IFH4:1;                      // 6 High-level Interrupt flag Filter 4
    Uint16 IFL4:1;                      // 7 Low-Level Interrupt flag Filter 4
    Uint16 MF1:1;                       // 8 Modulator Failure for Filter 1
    Uint16 MF2:1;                       // 9 Modulator Failure for Filter 2
    Uint16 MF3:1;                       // 10 Modulator Failure for Filter 3
    Uint16 MF4:1;                       // 11 Modulator Failure for Filter 4
    Uint16 AF1:1;                       // 12 Acknowledge flag for Filter 1
    Uint16 AF2:1;                       // 13 Acknowledge flag for Filter 2
    Uint16 AF3:1;                       // 14 Acknowledge flag for Filter 3
    Uint16 AF4:1;                       // 15 Acknowledge flag for Filter 4
    Uint16 rsvd1:15;                    // 30:16 Reserved
    Uint16 MIF:1;                       // 31 Master Interrupt Flag
};

union SDIFLG_REG {
    Uint32  all;
    struct  SDIFLG_BITS  bit;
};

struct SDIFLGCLR_BITS {                 // bits description
    Uint16 IFH1:1;                      // 0 High-level Interrupt flag Filter 1
    Uint16 IFL1:1;                      // 1 Low-Level Interrupt flag Filter 1
    Uint16 IFH2:1;                      // 2 High-level Interrupt flag Filter 2
    Uint16 IFL2:1;                      // 3 Low-Level Interrupt flag Filter 2
    Uint16 IFH3:1;                      // 4 High-level Interrupt flag Filter 3
    Uint16 IFL3:1;                      // 5 Low-Level Interrupt flag Filter 3
    Uint16 IFH4:1;                      // 6 High-level Interrupt flag Filter 4
    Uint16 IFL4:1;                      // 7 Low-Level Interrupt flag Filter 4
    Uint16 MF1:1;                       // 8 Modulator Failure for Filter 1
    Uint16 MF2:1;                       // 9 Modulator Failure for Filter 2
    Uint16 MF3:1;                       // 10 Modulator Failure for Filter 3
    Uint16 MF4:1;                       // 11 Modulator Failure for Filter 4
    Uint16 AF1:1;                       // 12 Acknowledge flag for Filter 1
    Uint16 AF2:1;                       // 13 Acknowledge flag for Filter 2
    Uint16 AF3:1;                       // 14 Acknowledge flag for Filter 3
    Uint16 AF4:1;                       // 15 Acknowledge flag for Filter 4
    Uint16 rsvd1:15;                    // 30:16 Reserved
    Uint16 MIF:1;                       // 31 Master Interrupt Flag
};

union SDIFLGCLR_REG {
    Uint32  all;
    struct  SDIFLGCLR_BITS  bit;
};

struct SDCTL_BITS {                     // bits description
    Uint16 rsvd1:13;                    // 12:0 Reserved
    Uint16 MIE:1;                       // 13 Master Interrupt enable
    Uint16 rsvd2:1;                     // 14 Reserved
    Uint16 rsvd3:1;                     // 15 Reserved
};

union SDCTL_REG {
    Uint16  all;
    struct  SDCTL_BITS  bit;
};

struct SDMFILEN_BITS {                  // bits description
    Uint16 rsvd1:4;                     // 3:0 Reserved
    Uint16 rsvd2:3;                     // 6:4 Reserved
    Uint16 rsvd3:2;                     // 8:7 Reserved
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 rsvd5:1;                     // 10 Reserved
    Uint16 MFE:1;                       // 11 Master Filter Enable. 
    Uint16 rsvd6:1;                     // 12 Reserved
    Uint16 rsvd7:3;                     // 15:13 Reserved
};

union SDMFILEN_REG {
    Uint16  all;
    struct  SDMFILEN_BITS  bit;
};

struct SDCTLPARM1_BITS {                // bits description
    Uint16 MOD:2;                       // 1:0 Delta-Sigma Modulator mode
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:11;                    // 15:5 Reserved
};

union SDCTLPARM1_REG {
    Uint16  all;
    struct  SDCTLPARM1_BITS  bit;
};

struct SDDFPARM1_BITS {                 // bits description
    Uint16 DOSR:8;                      // 7:0 Data Filter Oversample Ratio= DOSR+1
    Uint16 FEN:1;                       // 8 Filter Enable 
    Uint16 AE:1;                        // 9 Ack Enable
    Uint16 SST:2;                       // 11:10 Data Filter Structure (DataFast/1/2/3)
    Uint16 FILRESEN:1;                  // 12 Data FILTER Reset Enable
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union SDDFPARM1_REG {
    Uint16  all;
    struct  SDDFPARM1_BITS  bit;
};

struct SDIPARM1_BITS {                  // bits description
    Uint16 rsvd1:7;                     // 6:0 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 DR:1;                        // 10 Data Representation (0/1 = 16/32b 2's complement)
    Uint16 SH:5;                        // 15:11 Shift Control (# bits to shift in 16b mode)
};

union SDIPARM1_REG {
    Uint16  all;
    struct  SDIPARM1_BITS  bit;
};

struct SDCMPH1_BITS {                   // bits description
    Uint16 HLT:15;                      // 14:0 High-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPH1_REG {
    Uint16  all;
    struct  SDCMPH1_BITS  bit;
};

struct SDCMPL1_BITS {                   // bits description
    Uint16 LLT:15;                      // 14:0 Low-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPL1_REG {
    Uint16  all;
    struct  SDCMPL1_BITS  bit;
};

struct SDCPARM1_BITS {                  // bits description
    Uint16 COSR:5;                      // 4:0 Comparator Oversample Ratio = COSR + 1
    Uint16 IEH:1;                       // 5 High-level interrupt enable
    Uint16 IEL:1;                       // 6 Low-level interrupt enable
    Uint16 CS1_CS0:2;                   // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
    Uint16 MFIE:1;                      // 9 Modulator Failure Interrupt enable
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union SDCPARM1_REG {
    Uint16  all;
    struct  SDCPARM1_BITS  bit;
};

struct SDDATA1_BITS {                   // bits description
    Uint16 DATA16:16;                   // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
    Uint16 DATA32HI:16;                 // 31:16 Hi-order 16b in 32b mode
};

union SDDATA1_REG {
    Uint32  all;
    struct  SDDATA1_BITS  bit;
};

struct SDCTLPARM2_BITS {                // bits description
    Uint16 MOD:2;                       // 1:0 Delta-Sigma Modulator mode
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:11;                    // 15:5 Reserved
};

union SDCTLPARM2_REG {
    Uint16  all;
    struct  SDCTLPARM2_BITS  bit;
};

struct SDDFPARM2_BITS {                 // bits description
    Uint16 DOSR:8;                      // 7:0 Data Filter Oversample Ratio= DOSR+1
    Uint16 FEN:1;                       // 8 Filter Enable 
    Uint16 AE:1;                        // 9 Ack Enable
    Uint16 SST:2;                       // 11:10 Data Filter Structure (SincFast/1/2/3)
    Uint16 FILRESEN:1;                  // 12 Data FILTER Reset Enable
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union SDDFPARM2_REG {
    Uint16  all;
    struct  SDDFPARM2_BITS  bit;
};

struct SDIPARM2_BITS {                  // bits description
    Uint16 rsvd1:7;                     // 6:0 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 DR:1;                        // 10 Data Representation (0/1 = 16/32b 2's complement)
    Uint16 SH:5;                        // 15:11 Shift Control (# bits to shift in 16b mode)
};

union SDIPARM2_REG {
    Uint16  all;
    struct  SDIPARM2_BITS  bit;
};

struct SDCMPH2_BITS {                   // bits description
    Uint16 HLT:15;                      // 14:0 High-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPH2_REG {
    Uint16  all;
    struct  SDCMPH2_BITS  bit;
};

struct SDCMPL2_BITS {                   // bits description
    Uint16 LLT:15;                      // 14:0 Low-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPL2_REG {
    Uint16  all;
    struct  SDCMPL2_BITS  bit;
};

struct SDCPARM2_BITS {                  // bits description
    Uint16 COSR:5;                      // 4:0 Comparator Oversample Ratio = COSR + 1
    Uint16 IEH:1;                       // 5 High-level interrupt enable
    Uint16 IEL:1;                       // 6 Low-level interrupt enable
    Uint16 CS1_CS0:2;                   // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
    Uint16 MFIE:1;                      // 9 Modulator Failure Interrupt enable
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union SDCPARM2_REG {
    Uint16  all;
    struct  SDCPARM2_BITS  bit;
};

struct SDDATA2_BITS {                   // bits description
    Uint16 DATA16:16;                   // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
    Uint16 DATA32HI:16;                 // 31:16 Hi-order 16b in 32b mode
};

union SDDATA2_REG {
    Uint32  all;
    struct  SDDATA2_BITS  bit;
};

struct SDCTLPARM3_BITS {                // bits description
    Uint16 MOD:2;                       // 1:0 Delta-Sigma Modulator mode
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:11;                    // 15:5 Reserved
};

union SDCTLPARM3_REG {
    Uint16  all;
    struct  SDCTLPARM3_BITS  bit;
};

struct SDDFPARM3_BITS {                 // bits description
    Uint16 DOSR:8;                      // 7:0 Data Filter Oversample Ratio= DOSR+1
    Uint16 FEN:1;                       // 8 Filter Enable 
    Uint16 AE:1;                        // 9 Ack Enable
    Uint16 SST:2;                       // 11:10 Data filter structure (SincFast/1/2/3)
    Uint16 FILRESEN:1;                  // 12 Data FILTER Reset Enable
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union SDDFPARM3_REG {
    Uint16  all;
    struct  SDDFPARM3_BITS  bit;
};

struct SDIPARM3_BITS {                  // bits description
    Uint16 rsvd1:7;                     // 6:0 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 DR:1;                        // 10 Data Representation (0/1 = 16/32b 2's complement)
    Uint16 SH:5;                        // 15:11 Shift Control (# bits to shift in 16b mode)
};

union SDIPARM3_REG {
    Uint16  all;
    struct  SDIPARM3_BITS  bit;
};

struct SDCMPH3_BITS {                   // bits description
    Uint16 HLT:15;                      // 14:0 High-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPH3_REG {
    Uint16  all;
    struct  SDCMPH3_BITS  bit;
};

struct SDCMPL3_BITS {                   // bits description
    Uint16 LLT:15;                      // 14:0 Low-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPL3_REG {
    Uint16  all;
    struct  SDCMPL3_BITS  bit;
};

struct SDCPARM3_BITS {                  // bits description
    Uint16 COSR:5;                      // 4:0 Comparator Oversample Ratio = COSR + 1
    Uint16 IEH:1;                       // 5 High-level interrupt enable
    Uint16 IEL:1;                       // 6 Low-level interrupt enable
    Uint16 CS1_CS0:2;                   // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
    Uint16 MFIE:1;                      // 9 Modulator Failure Interrupt enable
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union SDCPARM3_REG {
    Uint16  all;
    struct  SDCPARM3_BITS  bit;
};

struct SDDATA3_BITS {                   // bits description
    Uint16 DATA16:16;                   // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
    Uint16 DATA32HI:16;                 // 31:16 Hi-order 16b in 32b mode
};

union SDDATA3_REG {
    Uint32  all;
    struct  SDDATA3_BITS  bit;
};

struct SDCTLPARM4_BITS {                // bits description
    Uint16 MOD:2;                       // 1:0 Delta-Sigma Modulator mode
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:11;                    // 15:5 Reserved
};

union SDCTLPARM4_REG {
    Uint16  all;
    struct  SDCTLPARM4_BITS  bit;
};

struct SDDFPARM4_BITS {                 // bits description
    Uint16 DOSR:8;                      // 7:0 SINC Filter Oversample Ratio= DOSR+1
    Uint16 FEN:1;                       // 8 Filter Enable 
    Uint16 AE:1;                        // 9 Ack Enable
    Uint16 SST:2;                       // 11:10 Data filter structure (SincFast/1/2/3)
    Uint16 FILRESEN:1;                  // 12 SINC FILTER Reset Enable
    Uint16 rsvd1:3;                     // 15:13 Reserved
};

union SDDFPARM4_REG {
    Uint16  all;
    struct  SDDFPARM4_BITS  bit;
};

struct SDIPARM4_BITS {                  // bits description
    Uint16 rsvd1:7;                     // 6:0 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:1;                     // 8 Reserved
    Uint16 rsvd4:1;                     // 9 Reserved
    Uint16 DR:1;                        // 10 Data Representation (0/1 = 16/32b 2's complement)
    Uint16 SH:5;                        // 15:11 Shift Control (# bits to shift in 16b mode)
};

union SDIPARM4_REG {
    Uint16  all;
    struct  SDIPARM4_BITS  bit;
};

struct SDCMPH4_BITS {                   // bits description
    Uint16 HLT:15;                      // 14:0 High-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPH4_REG {
    Uint16  all;
    struct  SDCMPH4_BITS  bit;
};

struct SDCMPL4_BITS {                   // bits description
    Uint16 LLT:15;                      // 14:0 Low-level threshold for the comparator filter output.
    Uint16 rsvd1:1;                     // 15 Reserved
};

union SDCMPL4_REG {
    Uint16  all;
    struct  SDCMPL4_BITS  bit;
};

struct SDCPARM4_BITS {                  // bits description
    Uint16 COSR:5;                      // 4:0 Comparator Oversample Ratio = COSR + 1
    Uint16 IEH:1;                       // 5 High-level interrupt enable
    Uint16 IEL:1;                       // 6 Low-level interrupt enable
    Uint16 CS1_CS0:2;                   // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
    Uint16 MFIE:1;                      // 9 Modulator Failure Interrupt enable
    Uint16 rsvd1:6;                     // 15:10 Reserved
};

union SDCPARM4_REG {
    Uint16  all;
    struct  SDCPARM4_BITS  bit;
};

struct SDDATA4_BITS {                   // bits description
    Uint16 DATA16:16;                   // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
    Uint16 DATA32HI:16;                 // 31:16 Hi-order 16b in 32b mode
};

union SDDATA4_REG {
    Uint32  all;
    struct  SDDATA4_BITS  bit;
};

struct SDFM_REGS {
    union   SDIFLG_REG                       SDIFLG;                       // Interrupt Flag Register
    union   SDIFLGCLR_REG                    SDIFLGCLR;                    // Interrupt Flag Clear Register
    union   SDCTL_REG                        SDCTL;                        // SD Control Register
    Uint16                                   rsvd1;                        // Reserved
    union   SDMFILEN_REG                     SDMFILEN;                     // SD Master Filter Enable
    Uint16                                   rsvd2[9];                     // Reserved
    union   SDCTLPARM1_REG                   SDCTLPARM1;                   // Control Parameter Register for Ch1
    union   SDDFPARM1_REG                    SDDFPARM1;                    // Data Filter Parameter Register for Ch1
    union   SDIPARM1_REG                     SDIPARM1;                     // Integer Parameter Register for Ch1
    union   SDCMPH1_REG                      SDCMPH1;                      // High-level Threshold Register for Ch1
    union   SDCMPL1_REG                      SDCMPL1;                      // Low-level Threshold Register for Ch1
    union   SDCPARM1_REG                     SDCPARM1;                     // Comparator Parameter Register for Ch1
    union   SDDATA1_REG                      SDDATA1;                      // Filter Data Register (16 or 32bit) for Ch1
    Uint16                                   rsvd3[8];                     // Reserved
    union   SDCTLPARM2_REG                   SDCTLPARM2;                   // Control Parameter Register for Ch2
    union   SDDFPARM2_REG                    SDDFPARM2;                    // Data Filter Parameter Register for Ch2
    union   SDIPARM2_REG                     SDIPARM2;                     // Integer Parameter Register for Ch2
    union   SDCMPH2_REG                      SDCMPH2;                      // High-level Threshold Register for Ch2
    union   SDCMPL2_REG                      SDCMPL2;                      // Low-level Threshold Register for Ch2
    union   SDCPARM2_REG                     SDCPARM2;                     // Comparator Parameter Register for Ch2
    union   SDDATA2_REG                      SDDATA2;                      // Filter Data Register (16 or 32bit) for Ch2
    Uint16                                   rsvd4[8];                     // Reserved
    union   SDCTLPARM3_REG                   SDCTLPARM3;                   // Control Parameter Register for Ch3
    union   SDDFPARM3_REG                    SDDFPARM3;                    // Data Filter Parameter Register for Ch3
    union   SDIPARM3_REG                     SDIPARM3;                     // Integer Parameter Register for Ch3
    union   SDCMPH3_REG                      SDCMPH3;                      // High-level Threshold Register for Ch3
    union   SDCMPL3_REG                      SDCMPL3;                      // Low-level Threshold Register for Ch3
    union   SDCPARM3_REG                     SDCPARM3;                     // Comparator Parameter Register for Ch3
    union   SDDATA3_REG                      SDDATA3;                      // Filter Data Register (16 or 32bit) for Ch3
    Uint16                                   rsvd5[8];                     // Reserved
    union   SDCTLPARM4_REG                   SDCTLPARM4;                   // Control Parameter Register for Ch4
    union   SDDFPARM4_REG                    SDDFPARM4;                    // Data Filter Parameter Register for Ch4
    union   SDIPARM4_REG                     SDIPARM4;                     // Integer Parameter Register for Ch4
    union   SDCMPH4_REG                      SDCMPH4;                      // High-level Threshold Register for Ch4
    union   SDCMPL4_REG                      SDCMPL4;                      // Low-level Threshold Register for Ch4
    union   SDCPARM4_REG                     SDCPARM4;                     // Comparator Parameter Register for Ch4
    union   SDDATA4_REG                      SDDATA4;                      // Filter Data Register (16 or 32bit) for Ch4
    Uint16                                   rsvd6[56];                    // Reserved
};

//---------------------------------------------------------------------------
// SDFM External References & Function Declarations:
//
extern volatile struct SDFM_REGS Sdfm1Regs;
extern volatile struct SDFM_REGS Sdfm2Regs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_spi.h
//
// TITLE:   F2807x Device SPI Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// SPI Individual Register Bit Definitions:

struct SPICCR_BITS {                    // bits description
    Uint16 SPICHAR:4;                   // 3:0 Character Length Control
    Uint16 SPILBK:1;                    // 4 SPI Loopback
    Uint16 HS_MODE:1;                   // 5 High Speed mode control
    Uint16 CLKPOLARITY:1;               // 6 Shift Clock Polarity
    Uint16 SPISWRESET:1;                // 7 SPI Software Reset
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SPICCR_REG {
    Uint16  all;
    struct  SPICCR_BITS  bit;
};

struct SPICTL_BITS {                    // bits description
    Uint16 SPIINTENA:1;                 // 0 SPI Interupt Enable
    Uint16 TALK:1;                      // 1 Master/Slave Transmit Enable
    Uint16 MASTER_SLAVE:1;              // 2 SPI Network Mode Control
    Uint16 CLK_PHASE:1;                 // 3 SPI Clock Phase
    Uint16 OVERRUNINTENA:1;             // 4 Overrun Interrupt Enable
    Uint16 rsvd1:11;                    // 15:5 Reserved
};

union SPICTL_REG {
    Uint16  all;
    struct  SPICTL_BITS  bit;
};

struct SPISTS_BITS {                    // bits description
    Uint16 rsvd1:5;                     // 4:0 Reserved
    Uint16 BUFFULL_FLAG:1;              // 5 SPI Transmit Buffer Full Flag
    Uint16 INT_FLAG:1;                  // 6 SPI Interrupt Flag
    Uint16 OVERRUN_FLAG:1;              // 7 SPI Receiver Overrun Flag
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union SPISTS_REG {
    Uint16  all;
    struct  SPISTS_BITS  bit;
};

struct SPIBRR_BITS {                    // bits description
    Uint16 SPI_BIT_RATE:7;              // 6:0 SPI Bit Rate Control
    Uint16 rsvd1:9;                     // 15:7 Reserved
};

union SPIBRR_REG {
    Uint16  all;
    struct  SPIBRR_BITS  bit;
};

struct SPIFFTX_BITS {                   // bits description
    Uint16 TXFFIL:5;                    // 4:0 TXFIFO Interrupt Level
    Uint16 TXFFIENA:1;                  // 5 TXFIFO Interrupt Enable
    Uint16 TXFFINTCLR:1;                // 6 TXFIFO Interrupt Clear
    Uint16 TXFFINT:1;                   // 7 TXFIFO Interrupt Flag
    Uint16 TXFFST:5;                    // 12:8 Transmit FIFO Status
    Uint16 TXFIFO:1;                    // 13 TXFIFO Reset
    Uint16 SPIFFENA:1;                  // 14 FIFO Enhancements Enable
    Uint16 SPIRST:1;                    // 15 SPI Reset
};

union SPIFFTX_REG {
    Uint16  all;
    struct  SPIFFTX_BITS  bit;
};

struct SPIFFRX_BITS {                   // bits description
    Uint16 RXFFIL:5;                    // 4:0 RXFIFO Interrupt Level
    Uint16 RXFFIENA:1;                  // 5 RXFIFO Interrupt Enable
    Uint16 RXFFINTCLR:1;                // 6 RXFIFO Interupt Clear
    Uint16 RXFFINT:1;                   // 7 RXFIFO Interrupt Flag
    Uint16 RXFFST:5;                    // 12:8 Receive FIFO Status
    Uint16 RXFIFORESET:1;               // 13 RXFIFO Reset
    Uint16 RXFFOVFCLR:1;                // 14 Receive FIFO Overflow Clear
    Uint16 RXFFOVF:1;                   // 15 Receive FIFO Overflow Flag
};

union SPIFFRX_REG {
    Uint16  all;
    struct  SPIFFRX_BITS  bit;
};

struct SPIFFCT_BITS {                   // bits description
    Uint16 TXDLY:8;                     // 7:0 FIFO Transmit Delay Bits
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union SPIFFCT_REG {
    Uint16  all;
    struct  SPIFFCT_BITS  bit;
};

struct SPIPRI_BITS {                    // bits description
    Uint16 TRIWIRE:1;                   // 0 3-wire mode select bit
    Uint16 STEINV:1;                    // 1 SPISTE inversion bit
    Uint16 rsvd1:2;                     // 3:2 Reserved
    Uint16 FREE:1;                      // 4 Free emulation mode
    Uint16 SOFT:1;                      // 5 Soft emulation mode
    Uint16 rsvd2:1;                     // 6 Reserved
    Uint16 rsvd3:9;                     // 15:7 Reserved
};

union SPIPRI_REG {
    Uint16  all;
    struct  SPIPRI_BITS  bit;
};

struct SPI_REGS {
    union   SPICCR_REG                       SPICCR;                       // SPI Configuration Control Register
    union   SPICTL_REG                       SPICTL;                       // SPI Operation Control Register
    union   SPISTS_REG                       SPISTS;                       // SPI Status Register
    Uint16                                   rsvd1;                        // Reserved
    union   SPIBRR_REG                       SPIBRR;                       // SPI Baud Rate Register
    Uint16                                   rsvd2;                        // Reserved
    Uint16                                   SPIRXEMU;                     // SPI Emulation Buffer Register
    Uint16                                   SPIRXBUF;                     // SPI Serial Input Buffer Register
    Uint16                                   SPITXBUF;                     // SPI Serial Output Buffer Register
    Uint16                                   SPIDAT;                       // SPI Serial Data Register
    union   SPIFFTX_REG                      SPIFFTX;                      // SPI FIFO Transmit Register
    union   SPIFFRX_REG                      SPIFFRX;                      // SPI FIFO Receive Register
    union   SPIFFCT_REG                      SPIFFCT;                      // SPI FIFO Control Register
    Uint16                                   rsvd3[2];                     // Reserved
    union   SPIPRI_REG                       SPIPRI;                       // SPI Priority Control Register
};

//---------------------------------------------------------------------------
// SPI External References & Function Declarations:
//
extern volatile struct SPI_REGS SpiaRegs;
extern volatile struct SPI_REGS SpibRegs;
extern volatile struct SPI_REGS SpicRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_sysctrl.h
//
// TITLE:   F2807x Device SYSCTRL Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// SYSCTRL Individual Register Bit Definitions:

struct PARTIDL_BITS {                   // bits description
    Uint16 rsvd1:3;                     // 2:0 Reserved
    Uint16 rsvd2:2;                     // 4:3 Reserved
    Uint16 rsvd3:1;                     // 5 Reserved
    Uint16 QUAL:2;                      // 7:6 Qualification Status
    Uint16 PIN_COUNT:3;                 // 10:8 Device Pin Count
    Uint16 rsvd4:1;                     // 11 Reserved
    Uint16 rsvd5:1;                     // 12 Reserved
    Uint16 INSTASPIN:2;                 // 14:13 Motorware feature set
    Uint16 rsvd6:1;                     // 15 Reserved
    Uint16 FLASH_SIZE:8;                // 23:16 Flash size in KB
    Uint16 rsvd7:4;                     // 27:24 Reserved
    Uint16 PARTID_FORMAT_REVISION:4;    // 31:28 Revision of the PARTID format
};

union PARTIDL_REG {
    Uint32  all;
    struct  PARTIDL_BITS  bit;
};

struct PARTIDH_BITS {                   // bits description
    Uint16 rsvd1:8;                     // 7:0 Reserved
    Uint16 FAMILY:8;                    // 15:8 Device family
    Uint16 PARTNO:8;                    // 23:16 Device part number
    Uint16 DEVICE_CLASS_ID:8;           // 31:24 Device class ID
};

union PARTIDH_REG {
    Uint32  all;
    struct  PARTIDH_BITS  bit;
};

struct DC0_BITS {                       // bits description
    Uint16 SINGLE_CORE:1;               // 0 Single Core vs Dual Core 
    Uint16 rsvd1:15;                    // 15:1 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DC0_REG {
    Uint32  all;
    struct  DC0_BITS  bit;
};

struct DC1_BITS {                       // bits description
    Uint16 CPU1_FPU_TMU:1;              // 0 CPU1's FPU1+TMU1 
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 CPU1_VCU:1;                  // 2 CPU1's VCU 
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:2;                     // 5:4 Reserved
    Uint16 CPU1_CLA1:1;                 // 6 CPU1.CLA1 
    Uint16 rsvd4:1;                     // 7 Reserved
    Uint16 rsvd5:1;                     // 8 Reserved
    Uint16 rsvd6:1;                     // 9 Reserved
    Uint16 rsvd7:6;                     // 15:10 Reserved
    Uint16 rsvd8:16;                    // 31:16 Reserved
};

union DC1_REG {
    Uint32  all;
    struct  DC1_BITS  bit;
};

struct DC2_BITS {                       // bits description
    Uint16 EMIF1:1;                     // 0 EMIF1 
    Uint16 EMIF2:1;                     // 1 EMIF2 
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DC2_REG {
    Uint32  all;
    struct  DC2_BITS  bit;
};

struct DC3_BITS {                       // bits description
    Uint16 EPWM1:1;                     // 0 EPWM1 
    Uint16 EPWM2:1;                     // 1 EPWM2 
    Uint16 EPWM3:1;                     // 2 EPWM3 
    Uint16 EPWM4:1;                     // 3 EPWM4 
    Uint16 EPWM5:1;                     // 4 EPWM5 
    Uint16 EPWM6:1;                     // 5 EPWM6 
    Uint16 EPWM7:1;                     // 6 EPWM7 
    Uint16 EPWM8:1;                     // 7 EPWM8 
    Uint16 EPWM9:1;                     // 8 EPWM9 
    Uint16 EPWM10:1;                    // 9 EPWM10 
    Uint16 EPWM11:1;                    // 10 EPWM11 
    Uint16 EPWM12:1;                    // 11 EPWM12 
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 rsvd2:1;                     // 13 Reserved
    Uint16 rsvd3:1;                     // 14 Reserved
    Uint16 rsvd4:1;                     // 15 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union DC3_REG {
    Uint32  all;
    struct  DC3_BITS  bit;
};

struct DC4_BITS {                       // bits description
    Uint16 ECAP1:1;                     // 0 ECAP1 
    Uint16 ECAP2:1;                     // 1 ECAP2 
    Uint16 ECAP3:1;                     // 2 ECAP3 
    Uint16 ECAP4:1;                     // 3 ECAP4 
    Uint16 ECAP5:1;                     // 4 ECAP5 
    Uint16 ECAP6:1;                     // 5 ECAP6 
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:8;                     // 15:8 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union DC4_REG {
    Uint32  all;
    struct  DC4_BITS  bit;
};

struct DC5_BITS {                       // bits description
    Uint16 EQEP1:1;                     // 0 EQEP1 
    Uint16 EQEP2:1;                     // 1 EQEP2 
    Uint16 EQEP3:1;                     // 2 EQEP3 
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union DC5_REG {
    Uint32  all;
    struct  DC5_BITS  bit;
};

struct DC6_BITS {                       // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 rsvd4:1;                     // 3 Reserved
    Uint16 rsvd5:1;                     // 4 Reserved
    Uint16 rsvd6:1;                     // 5 Reserved
    Uint16 rsvd7:1;                     // 6 Reserved
    Uint16 rsvd8:1;                     // 7 Reserved
    Uint16 rsvd9:8;                     // 15:8 Reserved
    Uint16 rsvd10:16;                   // 31:16 Reserved
};

union DC6_REG {
    Uint32  all;
    struct  DC6_BITS  bit;
};

struct DC7_BITS {                       // bits description
    Uint16 SD1:1;                       // 0 SD1 
    Uint16 SD2:1;                       // 1 SD2 
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:1;                     // 5 Reserved
    Uint16 rsvd5:1;                     // 6 Reserved
    Uint16 rsvd6:1;                     // 7 Reserved
    Uint16 rsvd7:8;                     // 15:8 Reserved
    Uint16 rsvd8:16;                    // 31:16 Reserved
};

union DC7_REG {
    Uint32  all;
    struct  DC7_BITS  bit;
};

struct DC8_BITS {                       // bits description
    Uint16 SCI_A:1;                     // 0 SCI_A 
    Uint16 SCI_B:1;                     // 1 SCI_B 
    Uint16 SCI_C:1;                     // 2 SCI_C 
    Uint16 SCI_D:1;                     // 3 SCI_D 
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DC8_REG {
    Uint32  all;
    struct  DC8_BITS  bit;
};

struct DC9_BITS {                       // bits description
    Uint16 SPI_A:1;                     // 0 SPI_A 
    Uint16 SPI_B:1;                     // 1 SPI_B 
    Uint16 SPI_C:1;                     // 2 SPI_C 
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:1;                     // 16 Reserved
    Uint16 rsvd4:1;                     // 17 Reserved
    Uint16 rsvd5:14;                    // 31:18 Reserved
};

union DC9_REG {
    Uint32  all;
    struct  DC9_BITS  bit;
};

struct DC10_BITS {                      // bits description
    Uint16 I2C_A:1;                     // 0 I2C_A 
    Uint16 I2C_B:1;                     // 1 I2C_B 
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:1;                     // 16 Reserved
    Uint16 rsvd3:1;                     // 17 Reserved
    Uint16 rsvd4:14;                    // 31:18 Reserved
};

union DC10_REG {
    Uint32  all;
    struct  DC10_BITS  bit;
};

struct DC11_BITS {                      // bits description
    Uint16 CAN_A:1;                     // 0 CAN_A 
    Uint16 CAN_B:1;                     // 1 CAN_B 
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:12;                    // 15:4 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union DC11_REG {
    Uint32  all;
    struct  DC11_BITS  bit;
};

struct DC12_BITS {                      // bits description
    Uint16 McBSP_A:1;                   // 0 McBSP_A 
    Uint16 McBSP_B:1;                   // 1 McBSP_B 
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 USB_A:2;                     // 17:16 Decides the capability of the USB_A Module
    Uint16 rsvd2:2;                     // 19:18 Reserved
    Uint16 rsvd3:12;                    // 31:20 Reserved
};

union DC12_REG {
    Uint32  all;
    struct  DC12_BITS  bit;
};

struct DC13_BITS {                      // bits description
    Uint16 uPP_A:1;                     // 0 uPP_A 
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 rsvd2:14;                    // 15:2 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union DC13_REG {
    Uint32  all;
    struct  DC13_BITS  bit;
};

struct DC14_BITS {                      // bits description
    Uint16 ADC_A:1;                     // 0 ADC_A
    Uint16 ADC_B:1;                     // 1 ADC_B
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 ADC_D:1;                     // 3 ADC_D
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union DC14_REG {
    Uint32  all;
    struct  DC14_BITS  bit;
};

struct DC15_BITS {                      // bits description
    Uint16 CMPSS1:1;                    // 0 CMPSS1 
    Uint16 CMPSS2:1;                    // 1 CMPSS2 
    Uint16 CMPSS3:1;                    // 2 CMPSS3 
    Uint16 CMPSS4:1;                    // 3 CMPSS4 
    Uint16 CMPSS5:1;                    // 4 CMPSS5 
    Uint16 CMPSS6:1;                    // 5 CMPSS6 
    Uint16 CMPSS7:1;                    // 6 CMPSS7 
    Uint16 CMPSS8:1;                    // 7 CMPSS8 
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DC15_REG {
    Uint32  all;
    struct  DC15_BITS  bit;
};

struct DC17_BITS {                      // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 rsvd4:1;                     // 3 Reserved
    Uint16 rsvd5:12;                    // 15:4 Reserved
    Uint16 DAC_A:1;                     // 16 Buffered-DAC_A
    Uint16 DAC_B:1;                     // 17 Buffered-DAC_B
    Uint16 DAC_C:1;                     // 18 Buffered-DAC_C
    Uint16 rsvd6:1;                     // 19 Reserved
    Uint16 rsvd7:12;                    // 31:20 Reserved
};

union DC17_REG {
    Uint32  all;
    struct  DC17_BITS  bit;
};

struct DC18_BITS {                      // bits description
    Uint16 LS0_1:1;                     // 0 LS0_1 
    Uint16 LS1_1:1;                     // 1 LS1_1 
    Uint16 LS2_1:1;                     // 2 LS2_1 
    Uint16 LS3_1:1;                     // 3 LS3_1 
    Uint16 LS4_1:1;                     // 4 LS4_1 
    Uint16 LS5_1:1;                     // 5 LS5_1 
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DC18_REG {
    Uint32  all;
    struct  DC18_BITS  bit;
};

struct DC20_BITS {                      // bits description
    Uint16 GS0:1;                       // 0 GS0 
    Uint16 GS1:1;                       // 1 GS1 
    Uint16 GS2:1;                       // 2 GS2 
    Uint16 GS3:1;                       // 3 GS3 
    Uint16 GS4:1;                       // 4 GS4 
    Uint16 GS5:1;                       // 5 GS5 
    Uint16 GS6:1;                       // 6 GS6 
    Uint16 GS7:1;                       // 7 GS7 
    Uint16 GS8:1;                       // 8 GS8 
    Uint16 GS9:1;                       // 9 GS9 
    Uint16 GS10:1;                      // 10 GS10 
    Uint16 GS11:1;                      // 11 GS11 
    Uint16 GS12:1;                      // 12 GS12 
    Uint16 GS13:1;                      // 13 GS13 
    Uint16 GS14:1;                      // 14 GS14 
    Uint16 GS15:1;                      // 15 GS15 
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union DC20_REG {
    Uint32  all;
    struct  DC20_BITS  bit;
};

struct PERCNF1_BITS {                   // bits description
    Uint16 ADC_A_MODE:1;                // 0 ADC_A mode setting bit
    Uint16 ADC_B_MODE:1;                // 1 ADC_B mode setting bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 ADC_D_MODE:1;                // 3 ADC_D mode setting bit
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 USB_A_PHY:1;                 // 16 USB_A_PHY 
    Uint16 rsvd3:1;                     // 17 Reserved
    Uint16 rsvd4:14;                    // 31:18 Reserved
};

union PERCNF1_REG {
    Uint32  all;
    struct  PERCNF1_BITS  bit;
};

struct FUSEERR_BITS {                   // bits description
    Uint16 ALERR:5;                     // 4:0 Efuse Autoload Error Status
    Uint16 ERR:1;                       // 5 Efuse Self Test Error Status
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union FUSEERR_REG {
    Uint32  all;
    struct  FUSEERR_BITS  bit;
};

struct SOFTPRES0_BITS {                 // bits description
    Uint16 CPU1_CLA1:1;                 // 0 CPU1_CLA1 software reset bit
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 rsvd2:1;                     // 2 Reserved
    Uint16 rsvd3:1;                     // 3 Reserved
    Uint16 rsvd4:12;                    // 15:4 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union SOFTPRES0_REG {
    Uint32  all;
    struct  SOFTPRES0_BITS  bit;
};

struct SOFTPRES1_BITS {                 // bits description
    Uint16 EMIF1:1;                     // 0 EMIF1 software reset bit
    Uint16 EMIF2:1;                     // 1 EMIF2 software reset bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SOFTPRES1_REG {
    Uint32  all;
    struct  SOFTPRES1_BITS  bit;
};

struct SOFTPRES2_BITS {                 // bits description
    Uint16 EPWM1:1;                     // 0 EPWM1 software reset bit
    Uint16 EPWM2:1;                     // 1 EPWM2 software reset bit
    Uint16 EPWM3:1;                     // 2 EPWM3 software reset bit
    Uint16 EPWM4:1;                     // 3 EPWM4 software reset bit
    Uint16 EPWM5:1;                     // 4 EPWM5 software reset bit
    Uint16 EPWM6:1;                     // 5 EPWM6 software reset bit
    Uint16 EPWM7:1;                     // 6 EPWM7 software reset bit
    Uint16 EPWM8:1;                     // 7 EPWM8 software reset bit
    Uint16 EPWM9:1;                     // 8 EPWM9 software reset bit
    Uint16 EPWM10:1;                    // 9 EPWM10 software reset bit
    Uint16 EPWM11:1;                    // 10 EPWM11 software reset bit
    Uint16 EPWM12:1;                    // 11 EPWM12 software reset bit
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 rsvd2:1;                     // 13 Reserved
    Uint16 rsvd3:1;                     // 14 Reserved
    Uint16 rsvd4:1;                     // 15 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union SOFTPRES2_REG {
    Uint32  all;
    struct  SOFTPRES2_BITS  bit;
};

struct SOFTPRES3_BITS {                 // bits description
    Uint16 ECAP1:1;                     // 0 ECAP1 software reset bit
    Uint16 ECAP2:1;                     // 1 ECAP2 software reset bit
    Uint16 ECAP3:1;                     // 2 ECAP3 software reset bit
    Uint16 ECAP4:1;                     // 3 ECAP4 software reset bit
    Uint16 ECAP5:1;                     // 4 ECAP5 software reset bit
    Uint16 ECAP6:1;                     // 5 ECAP6 software reset bit
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:8;                     // 15:8 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union SOFTPRES3_REG {
    Uint32  all;
    struct  SOFTPRES3_BITS  bit;
};

struct SOFTPRES4_BITS {                 // bits description
    Uint16 EQEP1:1;                     // 0 EQEP1 software reset bit
    Uint16 EQEP2:1;                     // 1 EQEP2 software reset bit
    Uint16 EQEP3:1;                     // 2 EQEP3 software reset bit
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union SOFTPRES4_REG {
    Uint32  all;
    struct  SOFTPRES4_BITS  bit;
};

struct SOFTPRES6_BITS {                 // bits description
    Uint16 SD1:1;                       // 0 SD1 software reset bit
    Uint16 SD2:1;                       // 1 SD2 software reset bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:1;                     // 5 Reserved
    Uint16 rsvd5:1;                     // 6 Reserved
    Uint16 rsvd6:1;                     // 7 Reserved
    Uint16 rsvd7:8;                     // 15:8 Reserved
    Uint16 rsvd8:16;                    // 31:16 Reserved
};

union SOFTPRES6_REG {
    Uint32  all;
    struct  SOFTPRES6_BITS  bit;
};

struct SOFTPRES7_BITS {                 // bits description
    Uint16 SCI_A:1;                     // 0 SCI_A software reset bit
    Uint16 SCI_B:1;                     // 1 SCI_B software reset bit
    Uint16 SCI_C:1;                     // 2 SCI_C software reset bit
    Uint16 SCI_D:1;                     // 3 SCI_D software reset bit
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SOFTPRES7_REG {
    Uint32  all;
    struct  SOFTPRES7_BITS  bit;
};

struct SOFTPRES8_BITS {                 // bits description
    Uint16 SPI_A:1;                     // 0 SPI_A software reset bit
    Uint16 SPI_B:1;                     // 1 SPI_B software reset bit
    Uint16 SPI_C:1;                     // 2 SPI_C software reset bit
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:1;                     // 16 Reserved
    Uint16 rsvd4:1;                     // 17 Reserved
    Uint16 rsvd5:14;                    // 31:18 Reserved
};

union SOFTPRES8_REG {
    Uint32  all;
    struct  SOFTPRES8_BITS  bit;
};

struct SOFTPRES9_BITS {                 // bits description
    Uint16 I2C_A:1;                     // 0 I2C_A software reset bit
    Uint16 I2C_B:1;                     // 1 I2C_B software reset bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:1;                     // 16 Reserved
    Uint16 rsvd3:1;                     // 17 Reserved
    Uint16 rsvd4:14;                    // 31:18 Reserved
};

union SOFTPRES9_REG {
    Uint32  all;
    struct  SOFTPRES9_BITS  bit;
};

struct SOFTPRES11_BITS {                // bits description
    Uint16 McBSP_A:1;                   // 0 McBSP_A software reset bit
    Uint16 McBSP_B:1;                   // 1 McBSP_B software reset bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 USB_A:1;                     // 16 USB_A software reset bit
    Uint16 rsvd2:1;                     // 17 Reserved
    Uint16 rsvd3:14;                    // 31:18 Reserved
};

union SOFTPRES11_REG {
    Uint32  all;
    struct  SOFTPRES11_BITS  bit;
};

struct SOFTPRES13_BITS {                // bits description
    Uint16 ADC_A:1;                     // 0 ADC_A software reset bit
    Uint16 ADC_B:1;                     // 1 ADC_B software reset bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 ADC_D:1;                     // 3 ADC_D software reset bit
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union SOFTPRES13_REG {
    Uint32  all;
    struct  SOFTPRES13_BITS  bit;
};

struct SOFTPRES14_BITS {                // bits description
    Uint16 CMPSS1:1;                    // 0 CMPSS1 software reset bit
    Uint16 CMPSS2:1;                    // 1 CMPSS2 software reset bit
    Uint16 CMPSS3:1;                    // 2 CMPSS3 software reset bit
    Uint16 CMPSS4:1;                    // 3 CMPSS4 software reset bit
    Uint16 CMPSS5:1;                    // 4 CMPSS5 software reset bit
    Uint16 CMPSS6:1;                    // 5 CMPSS6 software reset bit
    Uint16 CMPSS7:1;                    // 6 CMPSS7 software reset bit
    Uint16 CMPSS8:1;                    // 7 CMPSS8 software reset bit
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SOFTPRES14_REG {
    Uint32  all;
    struct  SOFTPRES14_BITS  bit;
};

struct SOFTPRES16_BITS {                // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 rsvd4:1;                     // 3 Reserved
    Uint16 rsvd5:12;                    // 15:4 Reserved
    Uint16 DAC_A:1;                     // 16 Buffered_DAC_A software reset bit
    Uint16 DAC_B:1;                     // 17 Buffered_DAC_B software reset bit
    Uint16 DAC_C:1;                     // 18 Buffered_DAC_C software reset bit
    Uint16 rsvd6:1;                     // 19 Reserved
    Uint16 rsvd7:12;                    // 31:20 Reserved
};

union SOFTPRES16_REG {
    Uint32  all;
    struct  SOFTPRES16_BITS  bit;
};

struct DEV_CFG_REGS {
    Uint16                                   rsvd1[8];                     // Reserved
    union   PARTIDL_REG                      PARTIDL;                      // Lower 32-bit of Device PART Identification Number
    union   PARTIDH_REG                      PARTIDH;                      // Upper 32-bit of Device PART Identification Number
    Uint32                                   REVID;                        // Device Revision Number
    Uint16                                   rsvd2[2];                     // Reserved
    union   DC0_REG                          DC0;                          // Device Capability: Device Information
    union   DC1_REG                          DC1;                          // Device Capability: Processing Block Customization
    union   DC2_REG                          DC2;                          // Device Capability: EMIF Customization
    union   DC3_REG                          DC3;                          // Device Capability: Peripheral Customization
    union   DC4_REG                          DC4;                          // Device Capability: Peripheral Customization
    union   DC5_REG                          DC5;                          // Device Capability: Peripheral Customization
    union   DC6_REG                          DC6;                          // Device Capability: Peripheral Customization
    union   DC7_REG                          DC7;                          // Device Capability: Peripheral Customization
    union   DC8_REG                          DC8;                          // Device Capability: Peripheral Customization
    union   DC9_REG                          DC9;                          // Device Capability: Peripheral Customization
    union   DC10_REG                         DC10;                         // Device Capability: Peripheral Customization
    union   DC11_REG                         DC11;                         // Device Capability: Peripheral Customization
    union   DC12_REG                         DC12;                         // Device Capability: Peripheral Customization
    union   DC13_REG                         DC13;                         // Device Capability: Peripheral Customization
    union   DC14_REG                         DC14;                         // Device Capability: Analog Modules Customization
    union   DC15_REG                         DC15;                         // Device Capability: Analog Modules Customization
    Uint16                                   rsvd3[2];                     // Reserved
    union   DC17_REG                         DC17;                         // Device Capability: Analog Modules Customization
    union   DC18_REG                         DC18;                         // Device Capability: CPU1 Lx SRAM Customization
    Uint16                                   rsvd4[2];                     // Reserved
    union   DC20_REG                         DC20;                         // Device Capability: GSx SRAM Customization
    Uint16                                   rsvd5[38];                    // Reserved
    union   PERCNF1_REG                      PERCNF1;                      // Peripheral Configuration register
    Uint16                                   rsvd6[18];                    // Reserved
    union   FUSEERR_REG                      FUSEERR;                      // e-Fuse error Status register
    Uint16                                   rsvd7[12];                    // Reserved
    union   SOFTPRES0_REG                    SOFTPRES0;                    // Processing Block Software Reset register
    union   SOFTPRES1_REG                    SOFTPRES1;                    // EMIF Software Reset register
    union   SOFTPRES2_REG                    SOFTPRES2;                    // Peripheral Software Reset register
    union   SOFTPRES3_REG                    SOFTPRES3;                    // Peripheral Software Reset register
    union   SOFTPRES4_REG                    SOFTPRES4;                    // Peripheral Software Reset register
    Uint16                                   rsvd8[2];                     // Reserved
    union   SOFTPRES6_REG                    SOFTPRES6;                    // Peripheral Software Reset register
    union   SOFTPRES7_REG                    SOFTPRES7;                    // Peripheral Software Reset register
    union   SOFTPRES8_REG                    SOFTPRES8;                    // Peripheral Software Reset register
    union   SOFTPRES9_REG                    SOFTPRES9;                    // Peripheral Software Reset register
    Uint16                                   rsvd9[2];                     // Reserved
    union   SOFTPRES11_REG                   SOFTPRES11;                   // Peripheral Software Reset register
    Uint16                                   rsvd10[2];                    // Reserved
    union   SOFTPRES13_REG                   SOFTPRES13;                   // Peripheral Software Reset register
    union   SOFTPRES14_REG                   SOFTPRES14;                   // Peripheral Software Reset register
    Uint16                                   rsvd11[2];                    // Reserved
    union   SOFTPRES16_REG                   SOFTPRES16;                   // Peripheral Software Reset register
    Uint16                                   rsvd12[138];                  // Reserved
};

struct CLKCFGLOCK1_BITS {               // bits description
    Uint16 CLKSRCCTL1:1;                // 0 Lock bit for CLKSRCCTL1 register
    Uint16 CLKSRCCTL2:1;                // 1 Lock bit for CLKSRCCTL2 register
    Uint16 CLKSRCCTL3:1;                // 2 Lock bit for CLKSRCCTL3 register
    Uint16 SYSPLLCTL1:1;                // 3 Lock bit for SYSPLLCTL1 register
    Uint16 SYSPLLCTL2:1;                // 4 Lock bit for SYSPLLCTL2 register
    Uint16 SYSPLLCTL3:1;                // 5 Lock bit for SYSPLLCTL3 register
    Uint16 SYSPLLMULT:1;                // 6 Lock bit for SYSPLLMULT register
    Uint16 AUXPLLCTL1:1;                // 7 Lock bit for AUXPLLCTL1 register
    Uint16 rsvd1:1;                     // 8 Reserved
    Uint16 rsvd2:1;                     // 9 Reserved
    Uint16 AUXPLLMULT:1;                // 10 Lock bit for AUXPLLMULT register
    Uint16 SYSCLKDIVSEL:1;              // 11 Lock bit for SYSCLKDIVSEL register
    Uint16 AUXCLKDIVSEL:1;              // 12 Lock bit for AUXCLKDIVSEL register
    Uint16 PERCLKDIVSEL:1;              // 13 Lock bit for PERCLKDIVSEL register
    Uint16 rsvd3:1;                     // 14 Reserved
    Uint16 LOSPCP:1;                    // 15 Lock bit for LOSPCP register
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union CLKCFGLOCK1_REG {
    Uint32  all;
    struct  CLKCFGLOCK1_BITS  bit;
};

struct CLKSRCCTL1_BITS {                // bits description
    Uint16 OSCCLKSRCSEL:2;              // 1:0 OSCCLK Source Select Bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 INTOSC2OFF:1;                // 3 Internal Oscillator 2 Off Bit
    Uint16 XTALOFF:1;                   // 4 Crystal (External) Oscillator Off Bit
    Uint16 WDHALTI:1;                   // 5 Watchdog HALT Mode Ignore Bit
    Uint16 rsvd2:10;                    // 15:6 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union CLKSRCCTL1_REG {
    Uint32  all;
    struct  CLKSRCCTL1_BITS  bit;
};

struct CLKSRCCTL2_BITS {                // bits description
    Uint16 AUXOSCCLKSRCSEL:2;           // 1:0 AUXOSCCLK Source Select Bit
    Uint16 CANABCLKSEL:2;               // 3:2 CANA Bit Clock Source Select Bit
    Uint16 CANBBCLKSEL:2;               // 5:4 CANB Bit Clock Source Select Bit
    Uint16 rsvd1:2;                     // 7:6 Reserved
    Uint16 rsvd2:2;                     // 9:8 Reserved
    Uint16 rsvd3:6;                     // 15:10 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union CLKSRCCTL2_REG {
    Uint32  all;
    struct  CLKSRCCTL2_BITS  bit;
};

struct CLKSRCCTL3_BITS {                // bits description
    Uint16 XCLKOUTSEL:3;                // 2:0 XCLKOUT Source Select Bit
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CLKSRCCTL3_REG {
    Uint32  all;
    struct  CLKSRCCTL3_BITS  bit;
};

struct SYSPLLCTL1_BITS {                // bits description
    Uint16 PLLEN:1;                     // 0 SYSPLL enable/disable bit
    Uint16 PLLCLKEN:1;                  // 1 SYSPLL bypassed or included in the PLLSYSCLK path
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SYSPLLCTL1_REG {
    Uint32  all;
    struct  SYSPLLCTL1_BITS  bit;
};

struct SYSPLLMULT_BITS {                // bits description
    Uint16 IMULT:7;                     // 6:0 SYSPLL Integer Multiplier
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 FMULT:2;                     // 9:8 SYSPLL Fractional Multiplier
    Uint16 rsvd2:6;                     // 15:10 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union SYSPLLMULT_REG {
    Uint32  all;
    struct  SYSPLLMULT_BITS  bit;
};

struct SYSPLLSTS_BITS {                 // bits description
    Uint16 LOCKS:1;                     // 0 SYSPLL Lock Status Bit
    Uint16 SLIPS:1;                     // 1 SYSPLL Slip Status Bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SYSPLLSTS_REG {
    Uint32  all;
    struct  SYSPLLSTS_BITS  bit;
};

struct AUXPLLCTL1_BITS {                // bits description
    Uint16 PLLEN:1;                     // 0 AUXPLL enable/disable bit
    Uint16 PLLCLKEN:1;                  // 1 AUXPLL bypassed or included in the AUXPLLCLK path
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union AUXPLLCTL1_REG {
    Uint32  all;
    struct  AUXPLLCTL1_BITS  bit;
};

struct AUXPLLMULT_BITS {                // bits description
    Uint16 IMULT:7;                     // 6:0 AUXPLL Integer Multiplier
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 FMULT:2;                     // 9:8 AUXPLL Fractional Multiplier
    Uint16 rsvd2:6;                     // 15:10 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union AUXPLLMULT_REG {
    Uint32  all;
    struct  AUXPLLMULT_BITS  bit;
};

struct AUXPLLSTS_BITS {                 // bits description
    Uint16 LOCKS:1;                     // 0 AUXPLL Lock Status Bit
    Uint16 SLIPS:1;                     // 1 AUXPLL Slip Status Bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union AUXPLLSTS_REG {
    Uint32  all;
    struct  AUXPLLSTS_BITS  bit;
};

struct SYSCLKDIVSEL_BITS {              // bits description
    Uint16 PLLSYSCLKDIV:6;              // 5:0 PLLSYSCLK Divide Select
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SYSCLKDIVSEL_REG {
    Uint32  all;
    struct  SYSCLKDIVSEL_BITS  bit;
};

struct AUXCLKDIVSEL_BITS {              // bits description
    Uint16 AUXPLLDIV:2;                 // 1:0 AUXPLLCLK Divide Select
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union AUXCLKDIVSEL_REG {
    Uint32  all;
    struct  AUXCLKDIVSEL_BITS  bit;
};

struct PERCLKDIVSEL_BITS {              // bits description
    Uint16 EPWMCLKDIV:2;                // 1:0 EPWM Clock Divide Select
    Uint16 rsvd1:2;                     // 3:2 Reserved
    Uint16 EMIF1CLKDIV:1;               // 4 EMIF1  Clock Divide Select
    Uint16 rsvd2:1;                     // 5 Reserved
    Uint16 EMIF2CLKDIV:1;               // 6 EMIF2 Clock Divide Select
    Uint16 rsvd3:9;                     // 15:7 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union PERCLKDIVSEL_REG {
    Uint32  all;
    struct  PERCLKDIVSEL_BITS  bit;
};

struct XCLKOUTDIVSEL_BITS {             // bits description
    Uint16 XCLKOUTDIV:2;                // 1:0 XCLKOUT Divide Select
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union XCLKOUTDIVSEL_REG {
    Uint32  all;
    struct  XCLKOUTDIVSEL_BITS  bit;
};

struct LOSPCP_BITS {                    // bits description
    Uint16 LSPCLKDIV:3;                 // 2:0 LSPCLK Divide Select
    Uint16 rsvd1:13;                    // 15:3 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union LOSPCP_REG {
    Uint32  all;
    struct  LOSPCP_BITS  bit;
};

struct MCDCR_BITS {                     // bits description
    Uint16 MCLKSTS:1;                   // 0 Missing Clock Status Bit
    Uint16 MCLKCLR:1;                   // 1 Missing Clock Clear Bit
    Uint16 MCLKOFF:1;                   // 2 Missing Clock Detect Off Bit
    Uint16 OSCOFF:1;                    // 3 Oscillator Clock Off Bit
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union MCDCR_REG {
    Uint32  all;
    struct  MCDCR_BITS  bit;
};

struct X1CNT_BITS {                     // bits description
    Uint16 X1CNT:10;                    // 9:0 X1 Counter
    Uint16 rsvd1:6;                     // 15:10 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union X1CNT_REG {
    Uint32  all;
    struct  X1CNT_BITS  bit;
};

struct CLK_CFG_REGS {
    Uint16                                   rsvd1[2];                     // Reserved
    union   CLKCFGLOCK1_REG                  CLKCFGLOCK1;                  // Lock bit for CLKCFG registers
    Uint16                                   rsvd2[4];                     // Reserved
    union   CLKSRCCTL1_REG                   CLKSRCCTL1;                   // Clock Source Control register-1
    union   CLKSRCCTL2_REG                   CLKSRCCTL2;                   // Clock Source Control register-2
    union   CLKSRCCTL3_REG                   CLKSRCCTL3;                   // Clock Source Control register-3
    union   SYSPLLCTL1_REG                   SYSPLLCTL1;                   // SYSPLL Control register-1
    Uint16                                   rsvd3[4];                     // Reserved
    union   SYSPLLMULT_REG                   SYSPLLMULT;                   // SYSPLL Multiplier register
    union   SYSPLLSTS_REG                    SYSPLLSTS;                    // SYSPLL Status register
    union   AUXPLLCTL1_REG                   AUXPLLCTL1;                   // AUXPLL Control register-1
    Uint16                                   rsvd4[4];                     // Reserved
    union   AUXPLLMULT_REG                   AUXPLLMULT;                   // AUXPLL Multiplier register
    union   AUXPLLSTS_REG                    AUXPLLSTS;                    // AUXPLL Status register
    union   SYSCLKDIVSEL_REG                 SYSCLKDIVSEL;                 // System Clock Divider Select register
    union   AUXCLKDIVSEL_REG                 AUXCLKDIVSEL;                 // Auxillary Clock Divider Select register
    union   PERCLKDIVSEL_REG                 PERCLKDIVSEL;                 // Peripheral Clock Divider Selet register
    union   XCLKOUTDIVSEL_REG                XCLKOUTDIVSEL;                // XCLKOUT Divider Select register
    Uint16                                   rsvd5[2];                     // Reserved
    union   LOSPCP_REG                       LOSPCP;                       // Low Speed Clock Source Prescalar
    union   MCDCR_REG                        MCDCR;                        // Missing Clock Detect Control Register
    union   X1CNT_REG                        X1CNT;                        // 10-bit Counter on X1 Clock
};

struct CPUSYSLOCK1_BITS {               // bits description
    Uint16 HIBBOOTMODE:1;               // 0 Lock bit for HIBBOOTMODE register
    Uint16 IORESTOREADDR:1;             // 1 Lock bit for IORESTOREADDR Register
    Uint16 PIEVERRADDR:1;               // 2 Lock bit for PIEVERRADDR Register
    Uint16 PCLKCR0:1;                   // 3 Lock bit for PCLKCR0 Register
    Uint16 PCLKCR1:1;                   // 4 Lock bit for PCLKCR1 Register
    Uint16 PCLKCR2:1;                   // 5 Lock bit for PCLKCR2 Register
    Uint16 PCLKCR3:1;                   // 6 Lock bit for PCLKCR3 Register
    Uint16 PCLKCR4:1;                   // 7 Lock bit for PCLKCR4 Register
    Uint16 PCLKCR5:1;                   // 8 Lock bit for PCLKCR5 Register
    Uint16 PCLKCR6:1;                   // 9 Lock bit for PCLKCR6 Register
    Uint16 PCLKCR7:1;                   // 10 Lock bit for PCLKCR7 Register
    Uint16 PCLKCR8:1;                   // 11 Lock bit for PCLKCR8 Register
    Uint16 PCLKCR9:1;                   // 12 Lock bit for PCLKCR9 Register
    Uint16 PCLKCR10:1;                  // 13 Lock bit for PCLKCR10 Register
    Uint16 PCLKCR11:1;                  // 14 Lock bit for PCLKCR11 Register
    Uint16 PCLKCR12:1;                  // 15 Lock bit for PCLKCR12 Register
    Uint16 PCLKCR13:1;                  // 16 Lock bit for PCLKCR13 Register
    Uint16 PCLKCR14:1;                  // 17 Lock bit for PCLKCR14 Register
    Uint16 PCLKCR15:1;                  // 18 Lock bit for PCLKCR15 Register
    Uint16 PCLKCR16:1;                  // 19 Lock bit for PCLKCR16 Register
    Uint16 SECMSEL:1;                   // 20 Lock bit for SECMSEL Register
    Uint16 LPMCR:1;                     // 21 Lock bit for LPMCR Register
    Uint16 GPIOLPMSEL0:1;               // 22 Lock bit for GPIOLPMSEL0 Register
    Uint16 GPIOLPMSEL1:1;               // 23 Lock bit for GPIOLPMSEL1 Register
    Uint16 rsvd1:8;                     // 31:24 Reserved
};

union CPUSYSLOCK1_REG {
    Uint32  all;
    struct  CPUSYSLOCK1_BITS  bit;
};

struct IORESTOREADDR_BITS {             // bits description
    Uint32 ADDR:22;                     // 21:0 restoreIO() routine address
    Uint16 rsvd1:10;                    // 31:22 Reserved
};

union IORESTOREADDR_REG {
    Uint32  all;
    struct  IORESTOREADDR_BITS  bit;
};

struct PIEVERRADDR_BITS {               // bits description
    Uint32 ADDR:22;                     // 21:0 PIE Vector Fetch Error Handler Routine Address
    Uint16 rsvd1:10;                    // 31:22 Reserved
};

union PIEVERRADDR_REG {
    Uint32  all;
    struct  PIEVERRADDR_BITS  bit;
};

struct PCLKCR0_BITS {                   // bits description
    Uint16 CLA1:1;                      // 0 CLA1 Clock Enable Bit
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 DMA:1;                       // 2 DMA Clock Enable bit
    Uint16 CPUTIMER0:1;                 // 3 CPUTIMER0 Clock Enable bit
    Uint16 CPUTIMER1:1;                 // 4 CPUTIMER1 Clock Enable bit
    Uint16 CPUTIMER2:1;                 // 5 CPUTIMER2 Clock Enable bit
    Uint16 rsvd2:10;                    // 15:6 Reserved
    Uint16 HRPWM:1;                     // 16 HRPWM Clock Enable Bit
    Uint16 rsvd3:1;                     // 17 Reserved
    Uint16 TBCLKSYNC:1;                 // 18 EPWM Time Base Clock sync
    Uint16 rsvd4:1;                     // 19 Reserved
    Uint16 rsvd5:12;                    // 31:20 Reserved
};

union PCLKCR0_REG {
    Uint32  all;
    struct  PCLKCR0_BITS  bit;
};

struct PCLKCR1_BITS {                   // bits description
    Uint16 EMIF1:1;                     // 0 EMIF1 Clock Enable bit
    Uint16 EMIF2:1;                     // 1 EMIF2 Clock Enable bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union PCLKCR1_REG {
    Uint32  all;
    struct  PCLKCR1_BITS  bit;
};

struct PCLKCR2_BITS {                   // bits description
    Uint16 EPWM1:1;                     // 0 EPWM1 Clock Enable bit
    Uint16 EPWM2:1;                     // 1 EPWM2 Clock Enable bit
    Uint16 EPWM3:1;                     // 2 EPWM3 Clock Enable bit
    Uint16 EPWM4:1;                     // 3 EPWM4 Clock Enable bit
    Uint16 EPWM5:1;                     // 4 EPWM5 Clock Enable bit
    Uint16 EPWM6:1;                     // 5 EPWM6 Clock Enable bit
    Uint16 EPWM7:1;                     // 6 EPWM7 Clock Enable bit
    Uint16 EPWM8:1;                     // 7 EPWM8 Clock Enable bit
    Uint16 EPWM9:1;                     // 8 EPWM9 Clock Enable bit
    Uint16 EPWM10:1;                    // 9 EPWM10 Clock Enable bit
    Uint16 EPWM11:1;                    // 10 EPWM11 Clock Enable bit
    Uint16 EPWM12:1;                    // 11 EPWM12 Clock Enable bit
    Uint16 rsvd1:1;                     // 12 Reserved
    Uint16 rsvd2:1;                     // 13 Reserved
    Uint16 rsvd3:1;                     // 14 Reserved
    Uint16 rsvd4:1;                     // 15 Reserved
    Uint16 rsvd5:16;                    // 31:16 Reserved
};

union PCLKCR2_REG {
    Uint32  all;
    struct  PCLKCR2_BITS  bit;
};

struct PCLKCR3_BITS {                   // bits description
    Uint16 ECAP1:1;                     // 0 ECAP1 Clock Enable bit
    Uint16 ECAP2:1;                     // 1 ECAP2 Clock Enable bit
    Uint16 ECAP3:1;                     // 2 ECAP3 Clock Enable bit
    Uint16 ECAP4:1;                     // 3 ECAP4 Clock Enable bit
    Uint16 ECAP5:1;                     // 4 ECAP5 Clock Enable bit
    Uint16 ECAP6:1;                     // 5 ECAP6 Clock Enable bit
    Uint16 rsvd1:1;                     // 6 Reserved
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 rsvd3:8;                     // 15:8 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union PCLKCR3_REG {
    Uint32  all;
    struct  PCLKCR3_BITS  bit;
};

struct PCLKCR4_BITS {                   // bits description
    Uint16 EQEP1:1;                     // 0 EQEP1 Clock Enable bit
    Uint16 EQEP2:1;                     // 1 EQEP2 Clock Enable bit
    Uint16 EQEP3:1;                     // 2 EQEP3 Clock Enable bit
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union PCLKCR4_REG {
    Uint32  all;
    struct  PCLKCR4_BITS  bit;
};

struct PCLKCR6_BITS {                   // bits description
    Uint16 SD1:1;                       // 0 SD1 Clock Enable bit
    Uint16 SD2:1;                       // 1 SD2 Clock Enable bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:1;                     // 4 Reserved
    Uint16 rsvd4:1;                     // 5 Reserved
    Uint16 rsvd5:1;                     // 6 Reserved
    Uint16 rsvd6:1;                     // 7 Reserved
    Uint16 rsvd7:8;                     // 15:8 Reserved
    Uint16 rsvd8:16;                    // 31:16 Reserved
};

union PCLKCR6_REG {
    Uint32  all;
    struct  PCLKCR6_BITS  bit;
};

struct PCLKCR7_BITS {                   // bits description
    Uint16 SCI_A:1;                     // 0 SCI_A Clock Enable bit
    Uint16 SCI_B:1;                     // 1 SCI_B Clock Enable bit
    Uint16 SCI_C:1;                     // 2 SCI_C Clock Enable bit
    Uint16 SCI_D:1;                     // 3 SCI_D Clock Enable bit
    Uint16 rsvd1:12;                    // 15:4 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union PCLKCR7_REG {
    Uint32  all;
    struct  PCLKCR7_BITS  bit;
};

struct PCLKCR8_BITS {                   // bits description
    Uint16 SPI_A:1;                     // 0 SPI_A Clock Enable bit
    Uint16 SPI_B:1;                     // 1 SPI_B Clock Enable bit
    Uint16 SPI_C:1;                     // 2 SPI_C Clock Enable bit
    Uint16 rsvd1:1;                     // 3 Reserved
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:1;                     // 16 Reserved
    Uint16 rsvd4:1;                     // 17 Reserved
    Uint16 rsvd5:14;                    // 31:18 Reserved
};

union PCLKCR8_REG {
    Uint32  all;
    struct  PCLKCR8_BITS  bit;
};

struct PCLKCR9_BITS {                   // bits description
    Uint16 I2C_A:1;                     // 0 I2C_A Clock Enable bit
    Uint16 I2C_B:1;                     // 1 I2C_B Clock Enable bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:1;                     // 16 Reserved
    Uint16 rsvd3:1;                     // 17 Reserved
    Uint16 rsvd4:14;                    // 31:18 Reserved
};

union PCLKCR9_REG {
    Uint32  all;
    struct  PCLKCR9_BITS  bit;
};

struct PCLKCR10_BITS {                  // bits description
    Uint16 CAN_A:1;                     // 0 CAN_A Clock Enable bit
    Uint16 CAN_B:1;                     // 1 CAN_B Clock Enable bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 rsvd2:1;                     // 3 Reserved
    Uint16 rsvd3:12;                    // 15:4 Reserved
    Uint16 rsvd4:16;                    // 31:16 Reserved
};

union PCLKCR10_REG {
    Uint32  all;
    struct  PCLKCR10_BITS  bit;
};

struct PCLKCR11_BITS {                  // bits description
    Uint16 McBSP_A:1;                   // 0 McBSP_A Clock Enable bit
    Uint16 McBSP_B:1;                   // 1 McBSP_B Clock Enable bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 USB_A:1;                     // 16 USB_A Clock Enable bit
    Uint16 rsvd2:1;                     // 17 Reserved
    Uint16 rsvd3:14;                    // 31:18 Reserved
};

union PCLKCR11_REG {
    Uint32  all;
    struct  PCLKCR11_BITS  bit;
};

struct PCLKCR12_BITS {                  // bits description
    Uint16 uPP_A:1;                     // 0 uPP_A Clock Enable bit
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 rsvd2:14;                    // 15:2 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union PCLKCR12_REG {
    Uint32  all;
    struct  PCLKCR12_BITS  bit;
};

struct PCLKCR13_BITS {                  // bits description
    Uint16 ADC_A:1;                     // 0 ADC_A Clock Enable bit
    Uint16 ADC_B:1;                     // 1 ADC_B Clock Enable bit
    Uint16 rsvd1:1;                     // 2 Reserved
    Uint16 ADC_D:1;                     // 3 ADC_D Clock Enable bit
    Uint16 rsvd2:12;                    // 15:4 Reserved
    Uint16 rsvd3:16;                    // 31:16 Reserved
};

union PCLKCR13_REG {
    Uint32  all;
    struct  PCLKCR13_BITS  bit;
};

struct PCLKCR14_BITS {                  // bits description
    Uint16 CMPSS1:1;                    // 0 CMPSS1 Clock Enable bit
    Uint16 CMPSS2:1;                    // 1 CMPSS2 Clock Enable bit
    Uint16 CMPSS3:1;                    // 2 CMPSS3 Clock Enable bit
    Uint16 CMPSS4:1;                    // 3 CMPSS4 Clock Enable bit
    Uint16 CMPSS5:1;                    // 4 CMPSS5 Clock Enable bit
    Uint16 CMPSS6:1;                    // 5 CMPSS6 Clock Enable bit
    Uint16 CMPSS7:1;                    // 6 CMPSS7 Clock Enable bit
    Uint16 CMPSS8:1;                    // 7 CMPSS8 Clock Enable bit
    Uint16 rsvd1:8;                     // 15:8 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union PCLKCR14_REG {
    Uint32  all;
    struct  PCLKCR14_BITS  bit;
};

struct PCLKCR16_BITS {                  // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 rsvd4:1;                     // 3 Reserved
    Uint16 rsvd5:12;                    // 15:4 Reserved
    Uint16 DAC_A:1;                     // 16 Buffered_DAC_A Clock Enable Bit
    Uint16 DAC_B:1;                     // 17 Buffered_DAC_B Clock Enable Bit
    Uint16 DAC_C:1;                     // 18 Buffered_DAC_C Clock Enable Bit
    Uint16 rsvd6:1;                     // 19 Reserved
    Uint16 rsvd7:12;                    // 31:20 Reserved
};

union PCLKCR16_REG {
    Uint32  all;
    struct  PCLKCR16_BITS  bit;
};

struct SECMSEL_BITS {                   // bits description
    Uint16 PF1SEL:2;                    // 1:0 Secondary Master Select for VBUS32_1 Bridge
    Uint16 PF2SEL:2;                    // 3:2 Secondary Master Select for VBUS32_2 Bridge
    Uint16 rsvd1:2;                     // 5:4 Reserved
    Uint16 rsvd2:2;                     // 7:6 Reserved
    Uint16 rsvd3:2;                     // 9:8 Reserved
    Uint16 rsvd4:2;                     // 11:10 Reserved
    Uint16 rsvd5:2;                     // 13:12 Reserved
    Uint16 rsvd6:2;                     // 15:14 Reserved
    Uint16 rsvd7:16;                    // 31:16 Reserved
};

union SECMSEL_REG {
    Uint32  all;
    struct  SECMSEL_BITS  bit;
};

struct LPMCR_BITS {                     // bits description
    Uint16 LPM:2;                       // 1:0 Low Power Mode setting
    Uint16 QUALSTDBY:6;                 // 7:2 STANDBY Wakeup Pin Qualification Setting
    Uint16 rsvd1:7;                     // 14:8 Reserved
    Uint16 WDINTE:1;                    // 15 Enable for WDINT wakeup from STANDBY
    Uint16 M0M1MODE:2;                  // 17:16 Configuration for M0 and M1 mode during HIB
    Uint16 rsvd2:13;                    // 30:18 Reserved
    Uint16 IOISODIS:1;                  // 31 IO Isolation Disable
};

union LPMCR_REG {
    Uint32  all;
    struct  LPMCR_BITS  bit;
};

struct GPIOLPMSEL0_BITS {               // bits description
    Uint16 GPIO0:1;                     // 0 GPIO0 Enable for LPM Wakeup
    Uint16 GPIO1:1;                     // 1 GPIO1 Enable for LPM Wakeup
    Uint16 GPIO2:1;                     // 2 GPIO2 Enable for LPM Wakeup
    Uint16 GPIO3:1;                     // 3 GPIO3 Enable for LPM Wakeup
    Uint16 GPIO4:1;                     // 4 GPIO4 Enable for LPM Wakeup
    Uint16 GPIO5:1;                     // 5 GPIO5 Enable for LPM Wakeup
    Uint16 GPIO6:1;                     // 6 GPIO6 Enable for LPM Wakeup
    Uint16 GPIO7:1;                     // 7 GPIO7 Enable for LPM Wakeup
    Uint16 GPIO8:1;                     // 8 GPIO8 Enable for LPM Wakeup
    Uint16 GPIO9:1;                     // 9 GPIO9 Enable for LPM Wakeup
    Uint16 GPIO10:1;                    // 10 GPIO10 Enable for LPM Wakeup
    Uint16 GPIO11:1;                    // 11 GPIO11 Enable for LPM Wakeup
    Uint16 GPIO12:1;                    // 12 GPIO12 Enable for LPM Wakeup
    Uint16 GPIO13:1;                    // 13 GPIO13 Enable for LPM Wakeup
    Uint16 GPIO14:1;                    // 14 GPIO14 Enable for LPM Wakeup
    Uint16 GPIO15:1;                    // 15 GPIO15 Enable for LPM Wakeup
    Uint16 GPIO16:1;                    // 16 GPIO16 Enable for LPM Wakeup
    Uint16 GPIO17:1;                    // 17 GPIO17 Enable for LPM Wakeup
    Uint16 GPIO18:1;                    // 18 GPIO18 Enable for LPM Wakeup
    Uint16 GPIO19:1;                    // 19 GPIO19 Enable for LPM Wakeup
    Uint16 GPIO20:1;                    // 20 GPIO20 Enable for LPM Wakeup
    Uint16 GPIO21:1;                    // 21 GPIO21 Enable for LPM Wakeup
    Uint16 GPIO22:1;                    // 22 GPIO22 Enable for LPM Wakeup
    Uint16 GPIO23:1;                    // 23 GPIO23 Enable for LPM Wakeup
    Uint16 GPIO24:1;                    // 24 GPIO24 Enable for LPM Wakeup
    Uint16 GPIO25:1;                    // 25 GPIO25 Enable for LPM Wakeup
    Uint16 GPIO26:1;                    // 26 GPIO26 Enable for LPM Wakeup
    Uint16 GPIO27:1;                    // 27 GPIO27 Enable for LPM Wakeup
    Uint16 GPIO28:1;                    // 28 GPIO28 Enable for LPM Wakeup
    Uint16 GPIO29:1;                    // 29 GPIO29 Enable for LPM Wakeup
    Uint16 GPIO30:1;                    // 30 GPIO30 Enable for LPM Wakeup
    Uint16 GPIO31:1;                    // 31 GPIO31 Enable for LPM Wakeup
};

union GPIOLPMSEL0_REG {
    Uint32  all;
    struct  GPIOLPMSEL0_BITS  bit;
};

struct GPIOLPMSEL1_BITS {               // bits description
    Uint16 GPIO32:1;                    // 0 GPIO32 Enable for LPM Wakeup
    Uint16 GPIO33:1;                    // 1 GPIO33 Enable for LPM Wakeup
    Uint16 GPIO34:1;                    // 2 GPIO34 Enable for LPM Wakeup
    Uint16 GPIO35:1;                    // 3 GPIO35 Enable for LPM Wakeup
    Uint16 GPIO36:1;                    // 4 GPIO36 Enable for LPM Wakeup
    Uint16 GPIO37:1;                    // 5 GPIO37 Enable for LPM Wakeup
    Uint16 GPIO38:1;                    // 6 GPIO38 Enable for LPM Wakeup
    Uint16 GPIO39:1;                    // 7 GPIO39 Enable for LPM Wakeup
    Uint16 GPIO40:1;                    // 8 GPIO40 Enable for LPM Wakeup
    Uint16 GPIO41:1;                    // 9 GPIO41 Enable for LPM Wakeup
    Uint16 GPIO42:1;                    // 10 GPIO42 Enable for LPM Wakeup
    Uint16 GPIO43:1;                    // 11 GPIO43 Enable for LPM Wakeup
    Uint16 GPIO44:1;                    // 12 GPIO44 Enable for LPM Wakeup
    Uint16 GPIO45:1;                    // 13 GPIO45 Enable for LPM Wakeup
    Uint16 GPIO46:1;                    // 14 GPIO46 Enable for LPM Wakeup
    Uint16 GPIO47:1;                    // 15 GPIO47 Enable for LPM Wakeup
    Uint16 GPIO48:1;                    // 16 GPIO48 Enable for LPM Wakeup
    Uint16 GPIO49:1;                    // 17 GPIO49 Enable for LPM Wakeup
    Uint16 GPIO50:1;                    // 18 GPIO50 Enable for LPM Wakeup
    Uint16 GPIO51:1;                    // 19 GPIO51 Enable for LPM Wakeup
    Uint16 GPIO52:1;                    // 20 GPIO52 Enable for LPM Wakeup
    Uint16 GPIO53:1;                    // 21 GPIO53 Enable for LPM Wakeup
    Uint16 GPIO54:1;                    // 22 GPIO54 Enable for LPM Wakeup
    Uint16 GPIO55:1;                    // 23 GPIO55 Enable for LPM Wakeup
    Uint16 GPIO56:1;                    // 24 GPIO56 Enable for LPM Wakeup
    Uint16 GPIO57:1;                    // 25 GPIO57 Enable for LPM Wakeup
    Uint16 GPIO58:1;                    // 26 GPIO58 Enable for LPM Wakeup
    Uint16 GPIO59:1;                    // 27 GPIO59 Enable for LPM Wakeup
    Uint16 GPIO60:1;                    // 28 GPIO60 Enable for LPM Wakeup
    Uint16 GPIO61:1;                    // 29 GPIO61 Enable for LPM Wakeup
    Uint16 GPIO62:1;                    // 30 GPIO62 Enable for LPM Wakeup
    Uint16 GPIO63:1;                    // 31 GPIO63 Enable for LPM Wakeup
};

union GPIOLPMSEL1_REG {
    Uint32  all;
    struct  GPIOLPMSEL1_BITS  bit;
};

struct TMR2CLKCTL_BITS {                // bits description
    Uint16 TMR2CLKSRCSEL:3;             // 2:0 CPU Timer 2 Clock Source Select Bit
    Uint16 TMR2CLKPRESCALE:3;           // 5:3 CPU Timer 2 Clock Pre-Scale Value
    Uint16 rsvd1:10;                    // 15:6 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union TMR2CLKCTL_REG {
    Uint32  all;
    struct  TMR2CLKCTL_BITS  bit;
};

struct RESC_BITS {                      // bits description
    Uint16 POR:1;                       // 0 POR Reset Cause Indication Bit
    Uint16 XRSn:1;                      // 1 XRSn Reset Cause Indication Bit
    Uint16 WDRSn:1;                     // 2 WDRSn Reset Cause Indication Bit
    Uint16 NMIWDRSn:1;                  // 3 NMIWDRSn Reset Cause Indication Bit
    Uint16 rsvd1:1;                     // 4 Reserved
    Uint16 HWBISTn:1;                   // 5 HWBISTn Reset Cause Indication Bit
    Uint16 HIBRESETn:1;                 // 6 HIBRESETn Reset Cause Indication Bit
    Uint16 rsvd2:1;                     // 7 Reserved
    Uint16 SCCRESETn:1;                 // 8 SCCRESETn Reset Cause Indication Bit
    Uint16 rsvd3:7;                     // 15:9 Reserved
    Uint16 rsvd4:14;                    // 29:16 Reserved
    Uint16 XRSn_pin_status:1;           // 30 XRSN Pin Status
    Uint16 TRSTn_pin_status:1;          // 31 TRSTn Status
};

union RESC_REG {
    Uint32  all;
    struct  RESC_BITS  bit;
};

struct CPU_SYS_REGS {
    union   CPUSYSLOCK1_REG                  CPUSYSLOCK1;                  // Lock bit for CPUSYS registers
    Uint16                                   rsvd1[4];                     // Reserved
    Uint32                                   HIBBOOTMODE;                  // HIB Boot Mode Register
    union   IORESTOREADDR_REG                IORESTOREADDR;                // IORestore() routine Address Register
    union   PIEVERRADDR_REG                  PIEVERRADDR;                  // PIE Vector Fetch Error Address register
    Uint16                                   rsvd2[22];                    // Reserved
    union   PCLKCR0_REG                      PCLKCR0;                      // Peripheral Clock Gating Registers
    union   PCLKCR1_REG                      PCLKCR1;                      // Peripheral Clock Gating Registers
    union   PCLKCR2_REG                      PCLKCR2;                      // Peripheral Clock Gating Registers
    union   PCLKCR3_REG                      PCLKCR3;                      // Peripheral Clock Gating Registers
    union   PCLKCR4_REG                      PCLKCR4;                      // Peripheral Clock Gating Registers
    Uint16                                   rsvd3[2];                     // Reserved
    union   PCLKCR6_REG                      PCLKCR6;                      // Peripheral Clock Gating Registers
    union   PCLKCR7_REG                      PCLKCR7;                      // Peripheral Clock Gating Registers
    union   PCLKCR8_REG                      PCLKCR8;                      // Peripheral Clock Gating Registers
    union   PCLKCR9_REG                      PCLKCR9;                      // Peripheral Clock Gating Registers
    union   PCLKCR10_REG                     PCLKCR10;                     // Peripheral Clock Gating Registers
    union   PCLKCR11_REG                     PCLKCR11;                     // Peripheral Clock Gating Registers
    union   PCLKCR12_REG                     PCLKCR12;                     // Peripheral Clock Gating Registers
    union   PCLKCR13_REG                     PCLKCR13;                     // Peripheral Clock Gating Registers
    union   PCLKCR14_REG                     PCLKCR14;                     // Peripheral Clock Gating Registers
    Uint16                                   rsvd4[2];                     // Reserved
    union   PCLKCR16_REG                     PCLKCR16;                     // Peripheral Clock Gating Registers
    Uint16                                   rsvd5[48];                    // Reserved
    union   SECMSEL_REG                      SECMSEL;                      // Secondary Master Select register for common peripherals: Selects between CLA & DMA
    union   LPMCR_REG                        LPMCR;                        // LPM Control Register
    union   GPIOLPMSEL0_REG                  GPIOLPMSEL0;                  // GPIO LPM Wakeup select registers
    union   GPIOLPMSEL1_REG                  GPIOLPMSEL1;                  // GPIO LPM Wakeup select registers
    union   TMR2CLKCTL_REG                   TMR2CLKCTL;                   // Timer2 Clock Measurement functionality control register
    Uint16                                   rsvd6[2];                     // Reserved
    union   RESC_REG                         RESC;                         // Reset Cause register
};

struct SCSR_BITS {                      // bits description
    Uint16 WDOVERRIDE:1;                // 0 WD Override for WDDIS bit
    Uint16 WDENINT:1;                   // 1 WD Interrupt Enable
    Uint16 WDINTS:1;                    // 2 WD Interrupt Status
    Uint16 rsvd1:13;                    // 15:3 Reserved
};

union SCSR_REG {
    Uint16  all;
    struct  SCSR_BITS  bit;
};

struct WDCNTR_BITS {                    // bits description
    Uint16 WDCNTR:8;                    // 7:0 WD Counter
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union WDCNTR_REG {
    Uint16  all;
    struct  WDCNTR_BITS  bit;
};

struct WDKEY_BITS {                     // bits description
    Uint16 WDKEY:8;                     // 7:0 WD KEY
    Uint16 rsvd1:8;                     // 15:8 Reserved
};

union WDKEY_REG {
    Uint16  all;
    struct  WDKEY_BITS  bit;
};

struct WDCR_BITS {                      // bits description
    Uint16 WDPS:3;                      // 2:0 WD Clock Prescalar
    Uint16 WDCHK:3;                     // 5:3 WD Check Bits
    Uint16 WDDIS:1;                     // 6 WD Disable
    Uint16 rsvd1:1;                     // 7 Reserved
    Uint16 rsvd2:8;                     // 15:8 Reserved
};

union WDCR_REG {
    Uint16  all;
    struct  WDCR_BITS  bit;
};

struct WDWCR_BITS {                     // bits description
    Uint16 MIN:8;                       // 7:0 WD Min Threshold setting for Windowed Watchdog functionality
    Uint16 FIRSTKEY:1;                  // 8 First Key Detect Flag
    Uint16 rsvd1:7;                     // 15:9 Reserved
};

union WDWCR_REG {
    Uint16  all;
    struct  WDWCR_BITS  bit;
};

struct WD_REGS {
    Uint16                                   rsvd1[34];                    // Reserved
    union   SCSR_REG                         SCSR;                         // System Control & Status Register
    union   WDCNTR_REG                       WDCNTR;                       // Watchdog Counter Register
    Uint16                                   rsvd2;                        // Reserved
    union   WDKEY_REG                        WDKEY;                        // Watchdog Reset Key Register
    Uint16                                   rsvd3[3];                     // Reserved
    union   WDCR_REG                         WDCR;                         // Watchdog Control Register
    union   WDWCR_REG                        WDWCR;                        // Watchdog Windowed Control Register
};

struct CLA1TASKSRCSELLOCK_BITS {        // bits description
    Uint16 CLA1TASKSRCSEL1:1;           // 0 CLA1TASKSRCSEL1 Register Lock bit
    Uint16 CLA1TASKSRCSEL2:1;           // 1 CLA1TASKSRCSEL2 Register Lock bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union CLA1TASKSRCSELLOCK_REG {
    Uint32  all;
    struct  CLA1TASKSRCSELLOCK_BITS  bit;
};

struct DMACHSRCSELLOCK_BITS {           // bits description
    Uint16 DMACHSRCSEL1:1;              // 0 DMACHSRCSEL1 Register Lock bit
    Uint16 DMACHSRCSEL2:1;              // 1 DMACHSRCSEL2 Register Lock bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union DMACHSRCSELLOCK_REG {
    Uint32  all;
    struct  DMACHSRCSELLOCK_BITS  bit;
};

struct CLA1TASKSRCSEL1_BITS {           // bits description
    Uint16 TASK1:8;                     // 7:0 Selects the Trigger Source for TASK1 of CLA1
    Uint16 TASK2:8;                     // 15:8 Selects the Trigger Source for TASK2 of CLA1
    Uint16 TASK3:8;                     // 23:16 Selects the Trigger Source for TASK3 of CLA1
    Uint16 TASK4:8;                     // 31:24 Selects the Trigger Source for TASK4 of CLA1
};

union CLA1TASKSRCSEL1_REG {
    Uint32  all;
    struct  CLA1TASKSRCSEL1_BITS  bit;
};

struct CLA1TASKSRCSEL2_BITS {           // bits description
    Uint16 TASK5:8;                     // 7:0 Selects the Trigger Source for TASK5 of CLA1
    Uint16 TASK6:8;                     // 15:8 Selects the Trigger Source for TASK6 of CLA1
    Uint16 TASK7:8;                     // 23:16 Selects the Trigger Source for TASK7 of CLA1
    Uint16 TASK8:8;                     // 31:24 Selects the Trigger Source for TASK8 of CLA1
};

union CLA1TASKSRCSEL2_REG {
    Uint32  all;
    struct  CLA1TASKSRCSEL2_BITS  bit;
};

struct DMACHSRCSEL1_BITS {              // bits description
    Uint16 CH1:8;                       // 7:0 Selects the Trigger and Sync Source CH1 of DMA
    Uint16 CH2:8;                       // 15:8 Selects the Trigger and Sync Source CH2 of DMA
    Uint16 CH3:8;                       // 23:16 Selects the Trigger and Sync Source CH3 of DMA
    Uint16 CH4:8;                       // 31:24 Selects the Trigger and Sync Source CH4 of DMA
};

union DMACHSRCSEL1_REG {
    Uint32  all;
    struct  DMACHSRCSEL1_BITS  bit;
};

struct DMACHSRCSEL2_BITS {              // bits description
    Uint16 CH5:8;                       // 7:0 Selects the Trigger and Sync Source CH5 of DMA
    Uint16 CH6:8;                       // 15:8 Selects the Trigger and Sync Source CH6 of DMA
    Uint16 rsvd1:16;                    // 31:16 Reserved
};

union DMACHSRCSEL2_REG {
    Uint32  all;
    struct  DMACHSRCSEL2_BITS  bit;
};

struct DMA_CLA_SRC_SEL_REGS {
    union   CLA1TASKSRCSELLOCK_REG           CLA1TASKSRCSELLOCK;           // CLA1 Task Trigger Source Select Lock Register
    Uint16                                   rsvd1[2];                     // Reserved
    union   DMACHSRCSELLOCK_REG              DMACHSRCSELLOCK;              // DMA Channel Triger Source Select Lock Register
    union   CLA1TASKSRCSEL1_REG              CLA1TASKSRCSEL1;              // CLA1 Task Trigger Source Select Register-1
    union   CLA1TASKSRCSEL2_REG              CLA1TASKSRCSEL2;              // CLA1 Task Trigger Source Select Register-2
    Uint16                                   rsvd2[12];                    // Reserved
    union   DMACHSRCSEL1_REG                 DMACHSRCSEL1;                 // DMA Channel Trigger Source Select Register-1
    union   DMACHSRCSEL2_REG                 DMACHSRCSEL2;                 // DMA Channel Trigger Source Select Register-2
};

struct SYNCSELECT_BITS {                // bits description
    Uint16 EPWM4SYNCIN:3;               // 2:0 Selects Sync Input Source for EPWM4
    Uint16 EPWM7SYNCIN:3;               // 5:3 Selects Sync Input Source for EPWM7
    Uint16 EPWM10SYNCIN:3;              // 8:6 Selects Sync Input Source for EPWM10
    Uint16 ECAP1SYNCIN:3;               // 11:9 Selects Sync Input Source for ECAP1
    Uint16 ECAP4SYNCIN:3;               // 14:12 Selects Sync Input Source for ECAP4
    Uint16 rsvd1:1;                     // 15 Reserved
    Uint16 rsvd2:11;                    // 26:16 Reserved
    Uint16 SYNCOUT:2;                   // 28:27 Select Syncout Source
    Uint16 rsvd3:3;                     // 31:29 Reserved
};

union SYNCSELECT_REG {
    Uint32  all;
    struct  SYNCSELECT_BITS  bit;
};

struct ADCSOCOUTSELECT_BITS {           // bits description
    Uint16 PWM1SOCAEN:1;                // 0 PWM1SOCAEN Enable for ADCSOCAO 
    Uint16 PWM2SOCAEN:1;                // 1 PWM2SOCAEN Enable for ADCSOCAO 
    Uint16 PWM3SOCAEN:1;                // 2 PWM3SOCAEN Enable for ADCSOCAO 
    Uint16 PWM4SOCAEN:1;                // 3 PWM4SOCAEN Enable for ADCSOCAO 
    Uint16 PWM5SOCAEN:1;                // 4 PWM5SOCAEN Enable for ADCSOCAO 
    Uint16 PWM6SOCAEN:1;                // 5 PWM6SOCAEN Enable for ADCSOCAO 
    Uint16 PWM7SOCAEN:1;                // 6 PWM7SOCAEN Enable for ADCSOCAO 
    Uint16 PWM8SOCAEN:1;                // 7 PWM8SOCAEN Enable for ADCSOCAO 
    Uint16 PWM9SOCAEN:1;                // 8 PWM9SOCAEN Enable for ADCSOCAO 
    Uint16 PWM10SOCAEN:1;               // 9 PWM10SOCAEN Enable for ADCSOCAO 
    Uint16 PWM11SOCAEN:1;               // 10 PWM11SOCAEN Enable for ADCSOCAO 
    Uint16 PWM12SOCAEN:1;               // 11 PWM12SOCAEN Enable for ADCSOCAO 
    Uint16 rsvd1:4;                     // 15:12 Reserved
    Uint16 PWM1SOCBEN:1;                // 16 PWM1SOCBEN Enable for ADCSOCBO 
    Uint16 PWM2SOCBEN:1;                // 17 PWM2SOCBEN Enable for ADCSOCBO 
    Uint16 PWM3SOCBEN:1;                // 18 PWM3SOCBEN Enable for ADCSOCBO 
    Uint16 PWM4SOCBEN:1;                // 19 PWM4SOCBEN Enable for ADCSOCBO 
    Uint16 PWM5SOCBEN:1;                // 20 PWM5SOCBEN Enable for ADCSOCBO 
    Uint16 PWM6SOCBEN:1;                // 21 PWM6SOCBEN Enable for ADCSOCBO 
    Uint16 PWM7SOCBEN:1;                // 22 PWM7SOCBEN Enable for ADCSOCBO 
    Uint16 PWM8SOCBEN:1;                // 23 PWM8SOCBEN Enable for ADCSOCBO 
    Uint16 PWM9SOCBEN:1;                // 24 PWM9SOCBEN Enable for ADCSOCBO 
    Uint16 PWM10SOCBEN:1;               // 25 PWM10SOCBEN Enable for ADCSOCBO 
    Uint16 PWM11SOCBEN:1;               // 26 PWM11SOCBEN Enable for ADCSOCBO 
    Uint16 PWM12SOCBEN:1;               // 27 PWM12SOCBEN Enable for ADCSOCBO 
    Uint16 rsvd2:4;                     // 31:28 Reserved
};

union ADCSOCOUTSELECT_REG {
    Uint32  all;
    struct  ADCSOCOUTSELECT_BITS  bit;
};

struct SYNCSOCLOCK_BITS {               // bits description
    Uint16 SYNCSELECT:1;                // 0 SYNCSEL Register Lock bit
    Uint16 ADCSOCOUTSELECT:1;           // 1 ADCSOCOUTSELECT Register Lock bit
    Uint16 rsvd1:14;                    // 15:2 Reserved
    Uint16 rsvd2:16;                    // 31:16 Reserved
};

union SYNCSOCLOCK_REG {
    Uint32  all;
    struct  SYNCSOCLOCK_BITS  bit;
};

struct SYNC_SOC_REGS {
    union   SYNCSELECT_REG                   SYNCSELECT;                   // Sync Input and Output Select Register
    union   ADCSOCOUTSELECT_REG              ADCSOCOUTSELECT;              // External ADC (Off Chip) SOC Select Register
    union   SYNCSOCLOCK_REG                  SYNCSOCLOCK;                  // SYNCSEL and EXTADCSOC Select Lock register
};

//---------------------------------------------------------------------------
// SYSCTRL External References & Function Declarations:
//
extern volatile struct WD_REGS WdRegs;
extern volatile struct SYNC_SOC_REGS SyncSocRegs;
extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;
extern volatile struct DEV_CFG_REGS DevCfgRegs;
extern volatile struct CLK_CFG_REGS ClkCfgRegs;
extern volatile struct CPU_SYS_REGS CpuSysRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_xbar.h
//
// TITLE:   F2807x Device XBAR Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// XBAR Individual Register Bit Definitions:

struct XBARFLG1_BITS {                  // bits description
    Uint16 CMPSS1_CTRIPL:1;             // 0 Input Flag for CMPSS1.CTRIPL Signal
    Uint16 CMPSS1_CTRIPH:1;             // 1 Input Flag for CMPSS1.CTRIPH Signal
    Uint16 CMPSS2_CTRIPL:1;             // 2 Input Flag for CMPSS2.CTRIPL Signal
    Uint16 CMPSS2_CTRIPH:1;             // 3 Input Flag for CMPSS2.CTRIPH Signal
    Uint16 CMPSS3_CTRIPL:1;             // 4 Input Flag for CMPSS3.CTRIPL Signal
    Uint16 CMPSS3_CTRIPH:1;             // 5 Input Flag for CMPSS3.CTRIPH Signal
    Uint16 CMPSS4_CTRIPL:1;             // 6 Input Flag for CMPSS4.CTRIPL Signal
    Uint16 CMPSS4_CTRIPH:1;             // 7 Input Flag for CMPSS4.CTRIPH Signal
    Uint16 CMPSS5_CTRIPL:1;             // 8 Input Flag for CMPSS5.CTRIPL Signal
    Uint16 CMPSS5_CTRIPH:1;             // 9 Input Flag for CMPSS5.CTRIPH Signal
    Uint16 CMPSS6_CTRIPL:1;             // 10 Input Flag for CMPSS6.CTRIPL Signal
    Uint16 CMPSS6_CTRIPH:1;             // 11 Input Flag for CMPSS6.CTRIPH Signal
    Uint16 CMPSS7_CTRIPL:1;             // 12 Input Flag for CMPSS7.CTRIPL Signal
    Uint16 CMPSS7_CTRIPH:1;             // 13 Input Flag for CMPSS7.CTRIPH Signal
    Uint16 CMPSS8_CTRIPL:1;             // 14 Input Flag for CMPSS8.CTRIPL Signal
    Uint16 CMPSS8_CTRIPH:1;             // 15 Input Flag for CMPSS8.CTRIPH Signal
    Uint16 CMPSS1_CTRIPOUTL:1;          // 16 Input Flag for CMPSS1.CTRIPOUTL Signal
    Uint16 CMPSS1_CTRIPOUTH:1;          // 17 Input Flag for CMPSS1.CTRIPOUTH Signal
    Uint16 CMPSS2_CTRIPOUTL:1;          // 18 Input Flag for CMPSS2.CTRIPOUTL Signal
    Uint16 CMPSS2_CTRIPOUTH:1;          // 19 Input Flag for CMPSS2.CTRIPOUTH Signal
    Uint16 CMPSS3_CTRIPOUTL:1;          // 20 Input Flag for CMPSS3.CTRIPOUTL Signal
    Uint16 CMPSS3_CTRIPOUTH:1;          // 21 Input Flag for CMPSS3.CTRIPOUTH Signal
    Uint16 CMPSS4_CTRIPOUTL:1;          // 22 Input Flag for CMPSS4.CTRIPOUTL Signal
    Uint16 CMPSS4_CTRIPOUTH:1;          // 23 Input Flag for CMPSS4.CTRIPOUTH Signal
    Uint16 CMPSS5_CTRIPOUTL:1;          // 24 Input Flag for CMPSS5.CTRIPOUTL Signal
    Uint16 CMPSS5_CTRIPOUTH:1;          // 25 Input Flag for CMPSS5.CTRIPOUTH Signal
    Uint16 CMPSS6_CTRIPOUTL:1;          // 26 Input Flag for CMPSS6.CTRIPOUTL Signal
    Uint16 CMPSS6_CTRIPOUTH:1;          // 27 Input Flag for CMPSS6.CTRIPOUTH Signal
    Uint16 CMPSS7_CTRIPOUTL:1;          // 28 Input Flag for CMPSS7.CTRIPOUTL Signal
    Uint16 CMPSS7_CTRIPOUTH:1;          // 29 Input Flag for CMPSS7.CTRIPOUTH Signal
    Uint16 CMPSS8_CTRIPOUTL:1;          // 30 Input Flag for CMPSS8.CTRIPOUTL Signal
    Uint16 CMPSS8_CTRIPOUTH:1;          // 31 Input Flag for CMPSS8.CTRIPOUTH Signal
};

union XBARFLG1_REG {
    Uint32  all;
    struct  XBARFLG1_BITS  bit;
};

struct XBARFLG2_BITS {                  // bits description
    Uint16 INPUT1:1;                    // 0 Input Flag for INPUT1 Signal
    Uint16 INPUT2:1;                    // 1 Input Flag for INPUT2 Signal
    Uint16 INPUT3:1;                    // 2 Input Flag for INPUT3 Signal
    Uint16 INPUT4:1;                    // 3 Input Flag for INPUT4 Signal
    Uint16 INPUT5:1;                    // 4 Input Flag for INPUT5 Signal
    Uint16 INPUT7:1;                    // 5 Input Flag for INPUT7 Signal
    Uint16 ADCSOCAO:1;                  // 6 Input Flag for ADCSOCAO Signal
    Uint16 ADCSOCBO:1;                  // 7 Input Flag for ADCSOCBO Signal
    Uint16 rsvd1:1;                     // 8 Reserved
    Uint16 rsvd2:1;                     // 9 Reserved
    Uint16 rsvd3:1;                     // 10 Reserved
    Uint16 rsvd4:1;                     // 11 Reserved
    Uint16 rsvd5:1;                     // 12 Reserved
    Uint16 rsvd6:1;                     // 13 Reserved
    Uint16 rsvd7:1;                     // 14 Reserved
    Uint16 rsvd8:1;                     // 15 Reserved
    Uint16 ECAP1_OUT:1;                 // 16 Input Flag for ECAP1.OUT Signal
    Uint16 ECAP2_OUT:1;                 // 17 Input Flag for ECAP2.OUT Signal
    Uint16 ECAP3_OUT:1;                 // 18 Input Flag for ECAP3.OUT Signal
    Uint16 ECAP4_OUT:1;                 // 19 Input Flag for ECAP4.OUT Signal
    Uint16 ECAP5_OUT:1;                 // 20 Input Flag for ECAP5.OUT Signal
    Uint16 ECAP6_OUT:1;                 // 21 Input Flag for ECAP6.OUT Signal
    Uint16 EXTSYNCOUT:1;                // 22 Input Flag for EXTSYNCOUT Signal
    Uint16 ADCAEVT1:1;                  // 23 Input Flag for ADCAEVT1 Signal
    Uint16 ADCAEVT2:1;                  // 24 Input Flag for ADCAEVT2 Signal
    Uint16 ADCAEVT3:1;                  // 25 Input Flag for ADCAEVT3 Signal
    Uint16 ADCAEVT4:1;                  // 26 Input Flag for ADCAEVT4 Signal
    Uint16 ADCBEVT1:1;                  // 27 Input Flag for ADCBEVT1 Signal
    Uint16 ADCBEVT2:1;                  // 28 Input Flag for ADCBEVT2 Signal
    Uint16 ADCBEVT3:1;                  // 29 Input Flag for ADCBEVT3 Signal
    Uint16 ADCBEVT4:1;                  // 30 Input Flag for ADCBEVT4 Signal
    Uint16 rsvd9:1;                     // 31 Reserved
};

union XBARFLG2_REG {
    Uint32  all;
    struct  XBARFLG2_BITS  bit;
};

struct XBARFLG3_BITS {                  // bits description
    Uint16 rsvd1:1;                     // 0 Reserved
    Uint16 rsvd2:1;                     // 1 Reserved
    Uint16 rsvd3:1;                     // 2 Reserved
    Uint16 ADCDEVT1:1;                  // 3 Input Flag for ADCDEVT1 Signal
    Uint16 ADCDEVT2:1;                  // 4 Input Flag for ADCDEVT2 Signal
    Uint16 ADCDEVT3:1;                  // 5 Input Flag for ADCDEVT3 Signal
    Uint16 ADCDEVT4:1;                  // 6 Input Flag for ADCDEVT4 Signal
    Uint16 SD1FLT1_COMPL:1;             // 7 Input Flag for SD1FLT1.COMPL Signal
    Uint16 SD1FLT1_COMPH:1;             // 8 Input Flag for SD1FLT1.COMPH Signal
    Uint16 SD1FLT2_COMPL:1;             // 9 Input Flag for SD1FLT2.COMPL Signal
    Uint16 SD1FLT2_COMPH:1;             // 10 Input Flag for SD1FLT2.COMPH Signal
    Uint16 SD1FLT3_COMPL:1;             // 11 Input Flag for SD1FLT3.COMPL Signal
    Uint16 SD1FLT3_COMPH:1;             // 12 Input Flag for SD1FLT3.COMPH Signal
    Uint16 SD1FLT4_COMPL:1;             // 13 Input Flag for SD1FLT4.COMPL Signal
    Uint16 SD1FLT4_COMPH:1;             // 14 Input Flag for SD1FLT4.COMPH Signal
    Uint16 SD2FLT1_COMPL:1;             // 15 Input Flag for SD2FLT1.COMPL Signal
    Uint16 SD2FLT1_COMPH:1;             // 16 Input Flag for SD2FLT1.COMPH Signal
    Uint16 SD2FLT2_COMPL:1;             // 17 Input Flag for SD2FLT2.COMPL Signal
    Uint16 SD2FLT2_COMPH:1;             // 18 Input Flag for SD2FLT2.COMPH Signal
    Uint16 SD2FLT3_COMPL:1;             // 19 Input Flag for SD2FLT3.COMPL Signal
    Uint16 SD2FLT3_COMPH:1;             // 20 Input Flag for SD2FLT3.COMPH Signal
    Uint16 SD2FLT4_COMPL:1;             // 21 Input Flag for SD2FLT4.COMPL Signal
    Uint16 SD2FLT4_COMPH:1;             // 22 Input Flag for SD2FLT4.COMPH Signal
    Uint16 rsvd4:9;                     // 31:23 Reserved
};

union XBARFLG3_REG {
    Uint32  all;
    struct  XBARFLG3_BITS  bit;
};

struct XBARCLR1_BITS {                  // bits description
    Uint16 CMPSS1_CTRIPL:1;             // 0 Input Flag Clear for CMPSS1.CTRIPL Signal
    Uint16 CMPSS1_CTRIPH:1;             // 1 Input Flag Clear for CMPSS1.CTRIPH Signal
    Uint16 CMPSS2_CTRIPL:1;             // 2 Input Flag Clear for CMPSS2.CTRIPL Signal
    Uint16 CMPSS2_CTRIPH:1;             // 3 Input Flag Clear for CMPSS2.CTRIPH Signal
    Uint16 CMPSS3_CTRIPL:1;             // 4 Input Flag Clear for CMPSS3.CTRIPL Signal
    Uint16 CMPSS3_CTRIPH:1;             // 5 Input Flag Clear for CMPSS3.CTRIPH Signal
    Uint16 CMPSS4_CTRIPL:1;             // 6 Input Flag Clear for CMPSS4.CTRIPL Signal
    Uint16 CMPSS4_CTRIPH:1;             // 7 Input Flag Clear for CMPSS4.CTRIPH Signal
    Uint16 CMPSS5_CTRIPL:1;             // 8 Input Flag Clear for CMPSS5.CTRIPL Signal
    Uint16 CMPSS5_CTRIPH:1;             // 9 Input Flag Clear for CMPSS5.CTRIPH Signal
    Uint16 CMPSS6_CTRIPL:1;             // 10 Input Flag Clear for CMPSS6.CTRIPL Signal
    Uint16 CMPSS6_CTRIPH:1;             // 11 Input Flag Clear for CMPSS6.CTRIPH Signal
    Uint16 CMPSS7_CTRIPL:1;             // 12 Input Flag Clear for CMPSS7.CTRIPL Signal
    Uint16 CMPSS7_CTRIPH:1;             // 13 Input Flag Clear for CMPSS7.CTRIPH Signal
    Uint16 CMPSS8_CTRIPL:1;             // 14 Input Flag Clear for CMPSS8.CTRIPL Signal
    Uint16 CMPSS8_CTRIPH:1;             // 15 Input Flag Clear for CMPSS8.CTRIPH Signal
    Uint16 CMPSS1_CTRIPOUTL:1;          // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal
    Uint16 CMPSS1_CTRIPOUTH:1;          // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal
    Uint16 CMPSS2_CTRIPOUTL:1;          // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal
    Uint16 CMPSS2_CTRIPOUTH:1;          // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal
    Uint16 CMPSS3_CTRIPOUTL:1;          // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal
    Uint16 CMPSS3_CTRIPOUTH:1;          // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal
    Uint16 CMPSS4_CTRIPOUTL:1;          // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal
    Uint16 CMPSS4_CTRIPOUTH:1;          // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal
    Uint16 CMPSS5_CTRIPOUTL:1;          // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal
    Uint16 CMPSS5_CTRIPOUTH:1;          // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal
    Uint16 CMPSS6_CTRIPOUTL:1;          // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal
    Uint16 CMPSS6_CTRIPOUTH:1;          // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal
    Uint16 CMPSS7_CTRIPOUTL:1;          // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal
    Uint16 CMPSS7_CTRIPOUTH:1;          // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal
    Uint16 CMPSS8_CTRIPOUTL:1;          // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal
    Uint16 CMPSS8_CTRIPOUTH:1;          // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal
};

union XBARCLR1_REG {
    Uint32  all;
    struct  XBARCLR1_BITS  bit;
};

struct XBARCLR2_BITS {                  // bits description
    Uint16 INPUT1:1;                    // 0 Input Flag Clear for INPUT1 Signal
    Uint16 INPUT2:1;                    // 1 Input Flag Clear for INPUT2 Signal
    Uint16 INPUT3:1;                    // 2 Input Flag Clear for INPUT3 Signal
    Uint16 INPUT4:1;                    // 3 Input Flag Clear for INPUT4 Signal
    Uint16 INPUT5:1;                    // 4 Input Flag Clear for INPUT5 Signal
    Uint16 INPUT7:1;                    // 5 Input Flag Clear for INPUT7 Signal
    Uint16 ADCSOCAO:1;                  // 6 Input Flag Clear for ADCSOCAO Signal
    Uint16 ADCSOCBO:1;                  // 7 Input Flag Clear for ADCSOCBO Signal
    Uint16 rsvd1:1;                     // 8 Reserved
    Uint16 rsvd2:1;                     // 9 Reserved
    Uint16 rsvd3:1;                     // 10 Reserved
    Uint16 rsvd4:1;                     // 11 Reserved
    Uint16 rsvd5:1;                     // 12 Reserved
    Uint16 rsvd6:1;                     // 13 Reserved
    Uint16 rsvd7:1;                     // 14 Reserved
    Uint16 rsvd8:1;                     // 15 Reserved
    Uint16 ECAP1_OUT:1;                 // 16 Input Flag Clear for ECAP1.OUT Signal
    Uint16 ECAP2_OUT:1;                 // 17 Input Flag Clear for ECAP2.OUT Signal
    Uint16 ECAP3_OUT:1;                 // 18 Input Flag Clear for ECAP3.OUT Signal
    Uint16 ECAP4_OUT:1;                 // 19 Input Flag Clear for ECAP4.OUT Signal
    Uint16 ECAP5_OUT:1;                 // 20 Input Flag Clear for ECAP5.OUT Signal
    Uint16 ECAP6_OUT:1;                 // 21 Input Flag Clear for ECAP6.OUT Signal
    Uint16 EXTSYNCOUT:1;                // 22 Input Flag Clear for EXTSYNCOUT Signal
    Uint16 ADCAEVT1:1;                  // 23 Input Flag Clear for ADCAEVT1 Signal
    Uint16 ADCAEVT2:1;                  // 24 Input Flag Clear for ADCAEVT2 Signal
    Uint16 ADCAEVT3:1;                  // 25 Input Flag Clear for ADCAEVT3 Signal
    Uint16 ADCAEVT4:1;                  // 26 Input Flag Clear for ADCAEVT4 Signal
    Uint16 ADCBEVT1:1;                  // 27 Input Flag Clear for ADCBEVT1 Signal
    Uint16 ADCBEVT2:1;                  // 28 Input Flag Clear for ADCBEVT2 Signal
    Uint16 ADCBEVT3:1;                  // 29 Input Flag Clear for ADCBEVT3 Signal
    Uint16 ADCBEVT4:1;                  // 30 Input Flag Clear for ADCBEVT4 Signal
    Uint16 ADCCEVT1:1;                  // 31 Input Flag Clear for ADCCEVT1 Signal
};

union XBARCLR2_REG {
    Uint32  all;
    struct  XBARCLR2_BITS  bit;
};

struct XBARCLR3_BITS {                  // bits description
    Uint16 ADCCEVT2:1;                  // 0 Input Flag Clear for ADCCEVT2 Signal
    Uint16 ADCCEVT3:1;                  // 1 Input Flag Clear for ADCCEVT3 Signal
    Uint16 ADCCEVT4:1;                  // 2 Input Flag Clear for ADCCEVT4 Signal
    Uint16 ADCDEVT1:1;                  // 3 Input Flag Clear for ADCDEVT1 Signal
    Uint16 ADCDEVT2:1;                  // 4 Input Flag Clear for ADCDEVT2 Signal
    Uint16 ADCDEVT3:1;                  // 5 Input Flag Clear for ADCDEVT3 Signal
    Uint16 ADCDEVT4:1;                  // 6 Input Flag Clear for ADCDEVT4 Signal
    Uint16 SD1FLT1_COMPL:1;             // 7 Input Flag Clear for SD1FLT1.COMPL Signal
    Uint16 SD1FLT1_COMPH:1;             // 8 Input Flag Clear for SD1FLT1.COMPH Signal
    Uint16 SD1FLT2_COMPL:1;             // 9 Input Flag Clear for SD1FLT2.COMPL Signal
    Uint16 SD1FLT2_COMPH:1;             // 10 Input Flag Clear for SD1FLT2.COMPH Signal
    Uint16 SD1FLT3_COMPL:1;             // 11 Input Flag Clear for SD1FLT3.COMPL Signal
    Uint16 SD1FLT3_COMPH:1;             // 12 Input Flag Clear for SD1FLT3.COMPH Signal
    Uint16 SD1FLT4_COMPL:1;             // 13 Input Flag Clear for SD1FLT4.COMPL Signal
    Uint16 SD1FLT4_COMPH:1;             // 14 Input Flag Clear for SD1FLT4.COMPH Signal
    Uint16 SD2FLT1_COMPL:1;             // 15 Input Flag Clear for SD2FLT1.COMPL Signal
    Uint16 SD2FLT1_COMPH:1;             // 16 Input Flag Clear for SD2FLT1.COMPH Signal
    Uint16 SD2FLT2_COMPL:1;             // 17 Input Flag Clear for SD2FLT2.COMPL Signal
    Uint16 SD2FLT2_COMPH:1;             // 18 Input Flag Clear for SD2FLT2.COMPH Signal
    Uint16 SD2FLT3_COMPL:1;             // 19 Input Flag Clear for SD2FLT3.COMPL Signal
    Uint16 SD2FLT3_COMPH:1;             // 20 Input Flag Clear for SD2FLT3.COMPH Signal
    Uint16 SD2FLT4_COMPL:1;             // 21 Input Flag Clear for SD2FLT4.COMPL Signal
    Uint16 SD2FLT4_COMPH:1;             // 22 Input Flag Clear for SD2FLT4.COMPH Signal
    Uint16 rsvd1:9;                     // 31:23 Reserved
};

union XBARCLR3_REG {
    Uint32  all;
    struct  XBARCLR3_BITS  bit;
};

struct XBAR_REGS {
    union   XBARFLG1_REG                     XBARFLG1;                     // X-Bar Input Flag Register 1
    union   XBARFLG2_REG                     XBARFLG2;                     // X-Bar Input Flag Register 2
    union   XBARFLG3_REG                     XBARFLG3;                     // X-Bar Input Flag Register 3
    Uint16                                   rsvd1[2];                     // Reserved
    union   XBARCLR1_REG                     XBARCLR1;                     // X-Bar Input Flag Clear Register 1
    union   XBARCLR2_REG                     XBARCLR2;                     // X-Bar Input Flag Clear Register 2
    union   XBARCLR3_REG                     XBARCLR3;                     // X-Bar Input Flag Clear Register 3
    Uint16                                   rsvd2[18];                    // Reserved
};

//---------------------------------------------------------------------------
// XBAR External References & Function Declarations:
//
extern volatile struct XBAR_REGS XbarRegs;
}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    F2807x_xint.h
//
// TITLE:   F2807x Device XINT Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


//---------------------------------------------------------------------------
// XINT Individual Register Bit Definitions:

struct XINT1CR_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 XINT1 Enable
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 POLARITY:2;                  // 3:2 XINT1 Polarity
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union XINT1CR_REG {
    Uint16  all;
    struct  XINT1CR_BITS  bit;
};

struct XINT2CR_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 XINT2 Enable
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 POLARITY:2;                  // 3:2 XINT2 Polarity
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union XINT2CR_REG {
    Uint16  all;
    struct  XINT2CR_BITS  bit;
};

struct XINT3CR_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 XINT3 Enable
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 POLARITY:2;                  // 3:2 XINT3 Polarity
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union XINT3CR_REG {
    Uint16  all;
    struct  XINT3CR_BITS  bit;
};

struct XINT4CR_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 XINT4 Enable
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 POLARITY:2;                  // 3:2 XINT4 Polarity
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union XINT4CR_REG {
    Uint16  all;
    struct  XINT4CR_BITS  bit;
};

struct XINT5CR_BITS {                   // bits description
    Uint16 ENABLE:1;                    // 0 XINT5 Enable
    Uint16 rsvd1:1;                     // 1 Reserved
    Uint16 POLARITY:2;                  // 3:2 XINT5 Polarity
    Uint16 rsvd2:12;                    // 15:4 Reserved
};

union XINT5CR_REG {
    Uint16  all;
    struct  XINT5CR_BITS  bit;
};

struct XINT_REGS {
    union   XINT1CR_REG                      XINT1CR;                      // XINT1 configuration register
    union   XINT2CR_REG                      XINT2CR;                      // XINT2 configuration register
    union   XINT3CR_REG                      XINT3CR;                      // XINT3 configuration register
    union   XINT4CR_REG                      XINT4CR;                      // XINT4 configuration register
    union   XINT5CR_REG                      XINT5CR;                      // XINT5 configuration register
    Uint16                                   rsvd1[3];                     // Reserved
    Uint16                                   XINT1CTR;                     // XINT1 counter register
    Uint16                                   XINT2CTR;                     // XINT2 counter register
    Uint16                                   XINT3CTR;                     // XINT3 counter register
};

//---------------------------------------------------------------------------
// XINT External References & Function Declarations:
//
extern volatile struct XINT_REGS XintRegs;
}


//===========================================================================
// End of file.
//===========================================================================

}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Cla_defines.h
//
// TITLE:  #defines used in CLA examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {

// MCTL Register
//==========================

// MMEMCFG Register
//==========================

// MIER Interrupt Enable Register
//==========================

// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register
//===========================================================================










// TODO



//---------------------------------------------------------------------------
// Useful CLA Operation Macros:
//================================












}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Cla_typedefs.h
//
// TITLE:  Variable type definitions
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################



// Macros to manipulate pre-processor to generate a header file name
// at compile time that is based on the test name and can be used as
// an argument to #include


// Suppress warnings casting CLA pointers
#pragma diag_suppress 70,770,232




// TI File $Revision: /main/1 $
// Checkin $Date: June 22, 2007   17:02:08 $
//###########################################################################
//
// FILE:  Flash2823x_API_Config.h
//
// TITLE: F2823x Flash Algo's - User Settings
//
// NOTE:  This file contains user defined settings that
//        are used by the F2823x Flash APIs.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################


extern "C" {

// Variables that can be configured by the user. 

/*-----------------------------------------------------------------------------
   1. Specify the device.
      Define the device to be programmed as "1" (no quotes).
      Define all other devices as "0" (no quotes).  
-----------------------------------------------------------------------------*/


/*-----------------------------------------------------------------------------
   2. Specify the clock rate of the CPU (SYSCLKOUT) in nS.

      Take into account the input clock frequency and the PLL multiplier
      that your application will use.
 
      Use one of the values provided, or define your own.
      The trailing L is required tells the compiler to treat 
      the number as a 64-bit value.  

      Only one statement should be uncommented.

      Example:  CLKIN is a 30MHz crystal. 
 
                If the application will set PLLCR = 0xA then the CPU clock 
                will be 150Mhz (SYSCLKOUT = 150MHz).  

                In this case, the CPU_RATE will be 6.667L
                Uncomment the line:  #define CPU_RATE  6.667L   
-----------------------------------------------------------------------------*/


//#define CPU_RATE   10.000L   // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE   13.330L   // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE   20.000L   // for a 50MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   33.333L   // for a 30MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   41.667L   // for a 24MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   50.000L   // for a 20MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   66.667L   // for a 15MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE  100.000L   // for a 10MHz CPU clock speed  (SYSCLKOUT)

//----------------------------------------------------------------------------


//-----------------------------------------------------------------------------
// **** DO NOT modify the code below this line ****
//-----------------------------------------------------------------------------


}

// TI File $Revision: /main/2 $
// Checkin $Date: February 5, 2008   11:10:00 $
//###########################################################################
//
// FILE:  Flash2823x_API_Library.h	
//
// TITLE: F2823x Flash Algo's main include file
//
// DESCRIPTION:
//
//       This file should be included in any project that uses any of the
//       the F2823x flash APIs or a fixed point project of the F2833x flash
//       APIs.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################



extern "C" {



/*---------------------------------------------------------------------------
 28x Datatypes

 For Portability, User Is Recommended To Use Following Data Type Size
 Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point
 variables:
---------------------------------------------------------------------------*/

typedef int                 int16;
typedef long                int32;
//typedef long long           int64;   
typedef unsigned int        Uint16;
typedef unsigned long       Uint32;
//typedef unsigned long long  Uint64;
typedef float               float32;
typedef long double         float64;

/*---------------------------------------------------------------------------
 API Status Messages

 The following status values are returned from the API to the calling
 program.  These can be used to determine if the API function passed
 or failed.  
---------------------------------------------------------------------------*/
 // Operation passed, no errors were flagged

// The CSM is preventing the function from performing its operation

// Device REVID does not match that required by the API
    
// Invalid address passed to the API

// Incorrect PARTID
// For example the F2806 API was used on a F2808 device. 

// API/Silicon missmatch.  An old version of the
// API is being used on silicon it is not valid for
// Please update to the latest API. 

// ---- Erase Specific errors ---- 

// ---- Program Specific errors ----  

// ---- Verify Specific errors ----

// Busy is set by each API function before it determines
// a pass or fail condition for that operation.  
// The calling function will will not receive this 
// status condition back from the API

/*---------------------------------------------------------------------------
 Flash sector mask definitions

 The following macros can be used to form a mask specifying which sectors
 will be erased by the erase API function.
 
 Bit0 = Sector A
 Bit1 = Sector B
 Bit2 = Sector C
 Bit3 = Sector D
 Bit4 = Sector E
 Bit5 = Sector F
 Bit6 = Sector G
 Bit7 = Sector H
---------------------------------------------------------------------------*/







/*---------------------------------------------------------------------------
 API Status Structure
 
 This structure is used to pass debug data back to the calling routine.
 Note that the Erase API function has 3 parts: precondition, erase and
 and compaction. Erase and compaction failures will not populate 
 the expected and actual data fields.  
---------------------------------------------------------------------------*/

typedef struct {
    Uint32  FirstFailAddr;
    Uint16  ExpectedData;
    Uint16  ActualData;
}FLASH_ST;

/*---------------------------------------------------------------------------
   Interface Function prototypes
   
   For each 28x Flash API library, the function names are of the form:
   Flash<DeviceNum>_<Operation>()
   
   Where <DeviceNum> is the device: ie 2808, 2806, 2801
         <Operation> is the operation such as Erase, Program...
         
   For portability for users who may move between the F2808, F2806 and
   F2801, the following macro definitions are supplied. 
   
   Using these macro definitions,  the user can use instead make a generic
   call:  Flash_<Operation> and the macro will map the call to the proper
   device function
   
   Note except for the toggle test function, all of the function prototypes
   are compatible with F281x devices as well. 
---------------------------------------------------------------------------*/




extern Uint16  Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat);
extern Uint16  Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus);
extern Uint16  Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
extern void    Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask);
extern Uint16  Flash_DepRecover();
extern float32 Flash_APIVersion();
extern Uint16  Flash_APIVersionHex(); 

/*---------------------------------------------------------------------------
   Frequency Scale factor:
   The calling program must provide this global parameter used
   for frequency scaling the algo's.
----------------------------------------------------------------------------*/

extern Uint32 Flash_CPUScaleFactor;

/*---------------------------------------------------------------------------
   Callback Function Pointer:
   A callback function can be specified.  This function will be called
   at safe times during erase, program and verify.  This function can
   then be used to service an external watchdog or send a communications
   packet.
   
   Note: 
   THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL.
   THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL
   DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL
----------------------------------------------------------------------------*/
//extern void (*Flash_CallbackPtr) (void);

/*---------------------------------------------------------------------------
   API load/run symbols:
   These symbols are defined by the linker during the link.  Refer to the
   Flash28_API section in the example .cmd file:

   Flash28_API:
   {
        Flash28235_API_Library.lib(.econst) 
        Flash28235_API_Library.lib(.text)
   } LOAD = FLASH, 
     RUN = SARAM, 
     LOAD_START(_Flash28_API_LoadStart),
     LOAD_END(_Flash28_API_LoadEnd),
     RUN_START(_Flash28_API_RunStart),
     PAGE = 0
   
   These are used to copy the flash API from flash to SARAM
   
----------------------------------------------------------------------------*/

//extern Uint16 Flash28_API_LoadStart;
//extern Uint16 Flash28_API_LoadEnd;
//extern Uint16 Flash28_API_RunStart;

}



// --------- END OF FILE ----------------------------------

//###########################################################################
//
// FILE:   F2807x_Examples.h
//
// TITLE:  F2807x Device Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {



//*****************************************************************************
// The following are values that can be passed to the
// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier
//*****************************************************************************



//*****************************************************************************
// The following are values that can be passed to the
// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier
//*****************************************************************************


//*****************************************************************************
// The following are values that can be passed to the
// InitSysPll() to select divsel for SYSPLL
//*****************************************************************************






//*****************************************************************************
// The following are values that can be passed to the
// InitSysPll() to select divsel for LSPCLK
//*****************************************************************************



//*****************************************************************************
// The following are values that can be passed to the
// InitAuxPll() to select divsel for AUXPLL
//*****************************************************************************

//*****************************************************************************
// The following are values that can be passed to the
// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL
//*****************************************************************************

//*****************************************************************************
// The following are values that can be passed to the
// InitSysPll() & InitAuxPll() to select clock source
//*****************************************************************************



//----------------------------------------------------------------------------

/*-----------------------------------------------------------------------------
      Specify the clock rate of the CPU (SYSCLKOUT) in nS.

      Take into account the input clock frequency and the PLL multiplier
      selected in step 1.

      Use one of the values provided, or define your own.
      The trailing L is required tells the compiler to treat
      the number as a 64-bit value.

      Only one statement should be uncommented.

      Example:   200 MHz devices:
                 CLKIN is a 10 MHz crystal or internal 10 MHz oscillator

                 In step 1 the user specified the PLL multiplier = 40 for a
                 200 MHz CPU clock (SYSCLKOUT = 200 MHz).

                 In this case, the CPU_RATE will be 5.000L
                 Uncomment the line: #define CPU_RATE 5.000L

-----------------------------------------------------------------------------*/

//#define CPU_RATE   5.00L   // for a 200MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE   5.263L   // for a 190MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   5.556L   // for a 180MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   5.882L   // for a 170MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   6.250L   // for a 160MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   6.667L   // for a 150MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   7.143L   // for a 140MHz CPU clock speed  (SYSCLKOUT)
//#define CPU_RATE   7.692L   // for a 130MHz CPU clock speed  (SYSCLKOUT)

//----------------------------------------------------------------------------

// The following pointer to a function call calibrates the ADC reference, 
// DAC offset, and internal oscillators

// The following pointers to functions calibrate the ADC linearity.  Use this
// in the AdcSetMode(...) function only

// The following pointer to a function call looks up the ADC offset trim for a 
// given condition. Use this in the AdcSetMode(...) function only.   

//---------------------------------------------------------------------------
// Include Example Header Files:
//

//###########################################################################
//
// FILE:   F2807x_GlobalPrototypes.h
//
// TITLE:  Global prototypes for F2807x Examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {

/*---- shared global function prototypes -----------------------------------*/
extern void EnableInterrupts(void);
extern void InitAPwm1Gpio(void);
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(Uint16 pin);
extern void InitECap2Gpio(Uint16 pin);
extern void InitECap3Gpio(Uint16 pin);
extern void InitECap4Gpio(Uint16 pin);
extern void InitECap5Gpio(Uint16 pin);
extern void InitECap6Gpio(Uint16 pin);
extern void InitEQep1Gpio(void);
extern void InitEQep2Gpio(void);
extern void InitEQep3Gpio(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
extern void InitEPwm4Gpio(void);
extern void InitEPwm5Gpio(void);
extern void InitEPwm6Gpio(void);
extern void InitEPwm7Gpio(void);
extern void InitEPwm8Gpio(void);
extern void InitEPwm9Gpio(void);
extern void InitEPwm10Gpio(void);
extern void InitEPwm11Gpio(void);
extern void InitEPwm12Gpio(void);
extern void InitPeripheralClocks(void);
extern void DisablePeripheralClocks(void);
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel);
extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel);

extern void ServiceDog(void);
extern void DisableDog(void);

extern Uint16 CsmUnlock(void);
extern void SysIntOsc1Sel (void);
extern void SysIntOsc2Sel (void);
extern void SysXtalOscSel (void);

extern void AuxIntOsc2Sel (void);
extern void AuxXtalOscSel (void);
extern void AuxAuxClkSel (void);

//                 CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
extern void InitFlash(void);
extern void InitFlash_Bank0(void);
extern void InitFlash_Bank1(void);
extern void FlashOff(void);
extern void FlashOff_Bank0(void);
extern void FlashOff_Bank1(void);
extern void SeizeFlashPump(void);
extern void SeizeFlashPump_Bank0(void);
extern void SeizeFlashPump_Bank1(void);
extern void ReleaseFlashPump(void);

//LPM functions in F2807x_SysCtrl.c
void IDLE();
void STANDBY();
void HALT();
void HIB();

//ADC functions
extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode);
extern void CalAdcINL(Uint16 adc);

// DMA Functions
extern void DMAInitialize(void);
// DMA Channel 1
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH1(void);
// DMA Channel 2
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH2(void);
// DMA Channel 3
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH3(void);
// DMA Channel 4
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH4(void);
// DMA Channel 5
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH5(void);
// DMA Channel 6
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
                             volatile Uint16 *DMA_Source);
extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest,
                                  volatile Uint32 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
                             int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
                             Uint16 cont, Uint16 synce, Uint16 syncsel,
                             Uint16 ovrinte, Uint16 datasize,
                             Uint16 chintmode,
                             Uint16 chinte);
extern void StartDMACH6(void);


//GPIO Functions
extern void InitGpio();
extern void GPIO_SetupPinMux(Uint16 pin, Uint16 cpu, Uint16 peripheral);
extern void GPIO_SetupPinOptions(Uint16 pin, Uint16 output, Uint16 flags);
extern void GPIO_SetupLock(Uint16 pin, Uint16 flags);
extern void GPIO_SetupXINT1Gpio(Uint16 pin);
extern void GPIO_SetupXINT2Gpio(Uint16 pin);
extern void GPIO_SetupXINT3Gpio(Uint16 pin);
extern void GPIO_SelectIpcInt(Uint16 newFlag);
extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void);
extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void);
extern void GPIO_EnableUnbondedIOPullups(void);
Uint16 GPIO_ReadPin(Uint16 pin);
void GPIO_WritePin(Uint16 pin, Uint16 outVal);


//IPC Functions
extern void InitIpc();
extern Uint64 ReadIpcTimer();
extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag);
extern void RecvIpcData(void *recv_buf, Uint16 word_length);
extern void FillIpcSendData(Uint16 fill_data);
extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag);
extern void SendIpcFlag(Uint16 flag);
extern void AckIpcFlag(Uint16 flag);
extern void CancelIpcFlag(Uint16 flag);
extern void WaitForIpcFlag(Uint16 flag);
extern void WaitForIpcAck(Uint16 flag);
extern void IpcSync(Uint16 flag);

// CAN Functions
extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin);
extern void CanAGpioConfig(Uint16 canaTxRxPin);
extern void CanBGpioConfig(Uint16 canbTxRxPin);
extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource);

// I2C Functions
extern void I2cAGpioConfig(Uint16 I2caDataClkPin);
extern void I2cBGpioConfig(Uint16 I2cbDataClkPin);

// McBSP functions
// McBSPA
extern void InitMcbspa(void);
extern void InitMcbspaInt(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
extern void InitMcbspaGpio(void);
extern void delay_loop(void);
// McBSPB
extern void InitMcbspb(void);
extern void InitMcbspbInt(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
extern void InitMcbspbGpio(void);

//Temp Sensor Functions
extern void InitTempSensor(float32 vrefhi_voltage);
extern int16 GetTemperatureC(int16 sensorSample);
extern int16 GetTemperatureK(int16 sensorSample);

//---------------------------------------------------------------------------
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in Flash to a different RUN location in internal
// RAM
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsRunEnd;
extern Uint16 RamfuncsRunSize;

extern UINT16 CriticalIntFuncsSecuredLoadStart;
extern UINT16 CriticalIntFuncsSecuredLoadEnd;
extern UINT16 CriticalIntFuncsSecuredRunStart;

extern Uint32 Cla1funcsRunStart;
extern Uint32 Cla1funcsLoadStart;
extern Uint32 Cla1funcsLoadEnd;


extern Uint16 Cla1ConstRunStart;
extern Uint16 Cla1ConstLoadStart;
extern Uint16 Cla1ConstLoadEnd;


}


//===========================================================================
// End of file.
//===========================================================================
                                               // .c files.
//###########################################################################
//
// FILE:   F2807x_Cputimers.h
//
// TITLE:  F2807x Device CPUTIMERS Register Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $   
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $   
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {

//---------------------------------------------------------------------------
// Cputimers External References & Function Declarations:
//
//---------------------------------------------------------------------------
// CPU Timer Support Variables:
//
struct CPUTIMER_VARS {
   volatile struct  CPUTIMER_REGS  *RegsAddr;
   Uint32    InterruptCount;
   float   CPUFreqInMHz;
   float   PeriodInUSec;
};

//---------------------------------------------------------------------------
// Function prototypes and external definitions:
//
void InitCpuTimers(void);
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);

extern struct CPUTIMER_VARS CpuTimer0;
extern struct CPUTIMER_VARS CpuTimer1;
extern struct CPUTIMER_VARS CpuTimer2;

//---------------------------------------------------------------------------
// Usefull Timer Operations:
//
// Start Timer:

// Stop Timer:

// Reload Timer With period Value:

// Read 32-Bit Timer Value:

// Read 32-Bit Period Value:

// Start Timer:

// Stop Timer:

// Reload Timer With period Value:

// Read 32-Bit Timer Value:

// Read 32-Bit Period Value:

}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Cmpss_defines.h
//
// TITLE:  #defines used in CMPSS examples
//
//###########################################################################


extern "C" {

	//definitions for selecting DACH reference
	
	//definitions for COMPH input selection
	

	//definitions for DAC source selection


	//definitions for CTRIPH/CTRIPOUTH output selection


}


//===========================================================================
// End of file.
//===========================================================================

//###########################################################################
//
// FILE:   F2807x_EPwm_defines.h
//
// TITLE:  #defines used in EPwm examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {

// TBCTL (Time-Base Control)
//==========================
// CTRMODE bits
// PHSEN bit
// PRDLD bit
// SYNCOSEL bits
// HSPCLKDIV and CLKDIV bits
// PHSDIR bit

// CMPCTL (Compare Control)
//==========================
// LOADAMODE and LOADBMODE bits
// SHDWAMODE and SHDWBMODE bits

// AQCTLA and AQCTLB (Action Qualifier Control)
//=============================================
// ZRO, PRD, CAU, CAD, CBU, CBD bits

// DBCTL (Dead-Band Control)
//==========================
// OUT MODE bits
// POLSEL bits
// IN MODE

// CHPCTL (chopper control)
//==========================
// CHPEN bit
// CHPFREQ bits
// CHPDUTY bits

// TZSEL (Trip Zone Select)
//==========================
// CBCn and OSHTn bits

// TZCTL (Trip Zone Control)
//==========================
// TZA and TZB bits

// TZDCSEL (Trip Zone Digital Compare)
//==========================
// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits


// ETSEL (Event Trigger Select)
//=============================

// ETPS (Event Trigger Pre-scale)
//===============================
// INTPRD, SOCAPRD, SOCBPRD bits
//--------------------------------
// HRPWM (High Resolution PWM)
// HRCNFG




//--------------------------------
// DC (Digital Compare)
//================================
// DCTRIPSEL
// DCFCTL



//DCACTL/DCBCTL


}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Adc_defines.h
//
// TITLE:  #defines used in ADC examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {

//definitions for specifying an ADC

//definitions for selecting ADC resolution

//definitions for selecting ADC signal mode
//(single-ended mode is only a valid mode for 12-bit resolution)

}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Emif_defines.h
//
// TITLE:  #defines used in EMIF examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################



extern "C" {

//cpu1 to cpu2 message for handshaking
//cpu2_to_cpu1 message ram for handshaking



// Values for ASYNC_CSx_CR Registers











// Values for ASYNC_WCCR Register



// Read mask for the registers which has reserved bits. 

//Write Mask to stop writing to control critical bit 
//None


}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:	F2807x_Gpio_defines.h
//
// TITLE:	F2807x GPIO support definitions
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//--------------------------------------------
// Defines
//--------------------------------------------

//CPU pin masters for GPIO_SelectPinMux()

//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3,
//QUAL6, and ASYNC) take up two bits and must be in the order specified.

//Flags for GPIO_SetupLock().

//Commands for the CPU2->CPU1 GPIO configuration interrupt handler

//Helpful constants for array-based access to GPIO registers




//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:	F2807x_I2c_defines.h
//
// TITLE:	F2807x I2C Common Definitions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//--------------------------------------------
// Defines
//--------------------------------------------

// Error Messages

// Clear Status Flags

// Interrupt Source Messages

// I2CMSG structure defines

// I2C Slave State defines

// I2C Slave Receiver messages defines

// I2C State defines

// I2C  Message Commands for I2CMSG struct

// Generic defines


//****************************************************************************
//   These are the Defines to select I2C pin muxing when calling the functions
//  I2cAGpioConfig() & I2cBGpioConfig() in F2807x_I2C.c
//****************************************************************************



//--------------------------------------------
// Structures
//--------------------------------------------

// I2C Message Structure
struct I2CMSG {
  Uint16 MsgStatus;				// Word stating what state msg is in:
  								//   I2C_MSGCMD_INACTIVE = do not send msg
  								//   I2C_MSGCMD_BUSY = msg start has been sent,
  								//                     awaiting stop
  								//   I2C_MSGCMD_SEND_WITHSTOP = command to send
  								//       master trans msg complete with a stop bit
  								//   I2C_MSGCMD_SEND_NOSTOP = command to send
  								//       master trans msg without the stop bit
  								//   I2C_MSGCMD_RESTART = command to send a restart
  								//       as a master receiver with a stop bit
  Uint16 SlaveAddress;			// I2C address of slave msg is intended for
  Uint16 NumOfBytes;			// Num of valid bytes in (or to be put in MsgBuffer)
  Uint16 MemoryHighAddr;		// EEPROM address of data associated with msg (high byte)
  Uint16 MemoryLowAddr;			// EEPROM address of data associated with msg (low byte)
  Uint16 MsgBuffer[4];	// Array holding msg data - max that
  										    // MAX_BUFFER_SIZE can be is 16 due to
  										    // the FIFO's
};


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Pie_defines.h
//
// TITLE:  #defines used in PIE examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


extern "C" {


}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:   F2807x_Dma_defines.h
//
// TITLE:  #defines used in DMA examples
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################



extern "C" {

// MODE
//==========================
// PERINTSEL bits










// OVERINTE bit
// PERINTE bit
// CHINTMODE bits
// ONESHOT bits
// CONTINOUS bit
// SYNCE bit
// SYNCSEL bit
// DATASIZE bit
// CHINTE bit


}


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:	F2807x_SysCtrl_defines.h
//
// TITLE:	F2807x LPM support definitions
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//--------------------------------------------
// Defines
//--------------------------------------------


//Key value used for write access to the flash pump semaphore register


//===========================================================================
// End of file.
//===========================================================================
//###########################################################################
//
// FILE:    hw_adc.h
//
// TITLE:   Definitions for the C28x ADC registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the ADC register offsets
//
//*****************************************************************************
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Stamp Register
                                              // Register
                                              // Register
                                              // Stamp Register
                                              // Stamp Register
                                              // Register
                                              // Register
                                              // Stamp Register
                                              // Stamp Register
                                              // Register
                                              // Register
                                              // Stamp Register
                                              // Stamp Register
                                              // Register
                                              // Register
                                              // Stamp Register
                                              // Result Register
                                              // Result Register
                                              // Result Register
                                              // Result Register

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCCTL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCCTL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCBURSTCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLG register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLGCLR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVF register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVFCLR register
//
//*****************************************************************************
                                              // Bits
                                              // Bits
                                              // Bits
                                              // Bits

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL1N2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL3N4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOCPRICTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL1 register
//
//*****************************************************************************
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL2 register
//
//*****************************************************************************
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select
                                              // Select

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFLG1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFRC1 register
//
//*****************************************************************************
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit
                                              // Bit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVF1 register
//
//*****************************************************************************
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag
                                              // Overflow Flag

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVFCLR1 register
//
//*****************************************************************************
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit
                                              // Overflow Bit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC0CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC1CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC2CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC3CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC4CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC5CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC6CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC7CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC8CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC9CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC10CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC11CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC12CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC13CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC14CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCSOC15CTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSTAT register
//
//*****************************************************************************
                                              // High Flag
                                              // Low Flag
                                              // Crossing Flag
                                              // High Flag
                                              // Low Flag
                                              // Crossing Flag
                                              // High Flag
                                              // Low Flag
                                              // Crossing Flag
                                              // High Flag
                                              // Low Flag
                                              // Crossing Flag

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCEVTCLR register
//
//*****************************************************************************
                                              // High Clear
                                              // Low Clear
                                              // Crossing Clear
                                              // High Clear
                                              // Low Clear
                                              // Crossing Clear
                                              // High Clear
                                              // Low Clear
                                              // Crossing Clear
                                              // High Clear
                                              // Low Clear
                                              // Crossing Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSEL register
//
//*****************************************************************************
                                              // High Event Enable
                                              // Low Event Enable
                                              // Crossing Event Enable
                                              // High Event Enable
                                              // Low Event Enable
                                              // Crossing Event Enable
                                              // High Event Enable
                                              // Low Event Enable
                                              // Crossing Event Enable
                                              // High Event Enable
                                              // Low Event Enable
                                              // Crossing Event Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCEVTINTSEL register
//
//*****************************************************************************
                                              // High Interrupt Enable
                                              // Low Interrupt Enable
                                              // Crossing Interrupt Enable
                                              // High Interrupt Enable
                                              // Low Interrupt Enable
                                              // Crossing Interrupt Enable
                                              // High Interrupt Enable
                                              // Low Interrupt Enable
                                              // Crossing Interrupt Enable
                                              // High Interrupt Enable
                                              // Low Interrupt Enable
                                              // Crossing Interrupt Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCCOUNTER register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCREV register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCOFFTRIM register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1CONFIG register
//
//*****************************************************************************
                                              // Configuration
                                              // Complement Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1STAMP register
//
//*****************************************************************************
                                              // Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1OFFCAL register
//
//*****************************************************************************
                                              // Offset Correction

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1OFFREF register
//
//*****************************************************************************
                                              // Offset Reference

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPHI register
//
//*****************************************************************************
                                              // High Limit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPLO register
//
//*****************************************************************************
                                              // Low Limit
                                              // Request Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2CONFIG register
//
//*****************************************************************************
                                              // Configuration
                                              // Complement Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2STAMP register
//
//*****************************************************************************
                                              // Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2OFFCAL register
//
//*****************************************************************************
                                              // Offset Correction

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2OFFREF register
//
//*****************************************************************************
                                              // Offset Reference

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPHI register
//
//*****************************************************************************
                                              // High Limit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPLO register
//
//*****************************************************************************
                                              // Low Limit
                                              // Request Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3CONFIG register
//
//*****************************************************************************
                                              // Configuration
                                              // Complement Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3STAMP register
//
//*****************************************************************************
                                              // Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3OFFCAL register
//
//*****************************************************************************
                                              // Offset Correction

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3OFFREF register
//
//*****************************************************************************
                                              // Offset Reference

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPHI register
//
//*****************************************************************************
                                              // High Limit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPLO register
//
//*****************************************************************************
                                              // Low Limit
                                              // Request Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4CONFIG register
//
//*****************************************************************************
                                              // Configuration
                                              // Complement Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4STAMP register
//
//*****************************************************************************
                                              // Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4OFFCAL register
//
//*****************************************************************************
                                              // Offset Correction

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4OFFREF register
//
//*****************************************************************************
                                              // Offset Reference

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPHI register
//
//*****************************************************************************
                                              // High Limit

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPLO register
//
//*****************************************************************************
                                              // Low Limit
                                              // Request Time Stamp

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT0 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT5 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT6 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT7 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT8 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT9 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT10 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT11 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT12 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT13 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT14 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCRESULT15 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1RESULT register
//
//*****************************************************************************
                                              // Result

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2RESULT register
//
//*****************************************************************************
                                              // Result

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3RESULT register
//
//*****************************************************************************
                                              // Result

//*****************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4RESULT register
//
//*****************************************************************************
                                              // Result
//###########################################################################
//
// FILE:    hw_can.h
//
// TITLE:   Definitions for the C28x CAN registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the CAN register offsets
//
//*****************************************************************************
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_CTL register
//
//*****************************************************************************
                                              // Disabled
                                              // Disabled
                                              // Retransmission
                                              // Enable
                                              // Disabled

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_ES register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_ERRC register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_BTR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_INT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TEST register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_PERR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_REL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_RAM_INIT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_EN register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_FLG register
//
//*****************************************************************************
                                              // INT0
                                              // INT1

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_CLR register
//
//*****************************************************************************
                                              // CAN INT0
                                              // for CAN INT1

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_ABOTR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ_X register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ_21 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NDAT_X register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NDAT_21 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IPEN_X register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IPEN_21 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_MVAL_X register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_MVAL_21 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IP_MUX21 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1CMD register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MSK register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1ARB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2CMD register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MSK register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2ARB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3OBS register
//
//*****************************************************************************
                                              // observation
                                              // access
                                              // read access
                                              // access
                                              // access
                                              // access

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MSK register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3ARB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3UPD register
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_cmpss.h
//
// TITLE:   Definitions for the C28x CMPSS registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the CMPSS register offsets
//
//*****************************************************************************
                                              // Register
                                              // Control Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Active Register
                                              // Shadow Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPCTL register
//
//*****************************************************************************
                                              // Select
                                              // Path Enable
                                              // Select
                                              // Path Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPHYSCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPSTS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPSTSCLR register
//
//*****************************************************************************
                                              // Clear
                                              // Enable
                                              // Clear
                                              // Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPDACCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DACHVALS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DACHVALA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPMAXREFA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPMAXREFS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPDECVALA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPDECVALS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPSTS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DACLVALS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DACLVALA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the COMPLOCK register
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_cputimer.h
//
// TITLE:   Definitions for the C28x CPUTIMER registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the CPUTIMER register offsets
//
//*****************************************************************************
                                              // High
                                              // High

//*****************************************************************************
//
// The following are defines for the bit fields in the TIM register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TIMH register
//
//*****************************************************************************
                                              // High

//*****************************************************************************
//
// The following are defines for the bit fields in the PRD register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the PRDH register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TCR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TPR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TPRH register
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_ecap.h
//
// TITLE:   Definitions for the C28x ECAP registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the ECAP register offsets
//
//*****************************************************************************
                                              // Register
                                              // Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the TSCTR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CTRPHS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAP1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAP2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAP3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CAP4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*****************************************************************************
                                              // 1
                                              // 2
                                              // 3
                                              // 4
                                              // Cap Event

//*****************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*****************************************************************************
                                              // for continuous

//*****************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*****************************************************************************
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*****************************************************************************
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable
//###########################################################################
//
// FILE:    hw_emif.h
//
// TITLE:   Definitions for the C28x EMIF registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the EMIF register offsets
//
//*****************************************************************************
                                              // Register
                                              // Register
                                              // (pad_cs_o_n[0]/pad_cs_o_n[1])
                                              // Config Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the RCSR register
//
//*****************************************************************************
                                              // half rate.

//*****************************************************************************
//
// The following are defines for the bit fields in the ASYNC_WCCR register
//
//*****************************************************************************
                                              // select 2.
                                              // select 3.
                                              // select 4.
                                              // select 5.
                                              // pad_wait_i[0].
                                              // pad_wait_i[1].
                                              // pad_wait_i[2].
                                              // pad_wait_i[3].

//*****************************************************************************
//
// The following are defines for the bit fields in the SDRAM_CR register
//
//*****************************************************************************
                                              // devices.
                                              // if this bit is set.
                                              // this bit is set.
                                              // if this bit is set
                                              // Down.

//*****************************************************************************
//
// The following are defines for the bit fields in the SDRAM_RCR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS2_CR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS3_CR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS4_CR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS5_CR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SDRAM_TR register
//
//*****************************************************************************
                                              // different bank.
                                              // timing.
                                              // Refresh/Activate timing

//*****************************************************************************
//
// The following are defines for the bit fields in the TOTAL_SDRAM_AR register
//
//*****************************************************************************
                                              // to SDRAM.

//*****************************************************************************
//
// The following are defines for the bit fields in the TOTAL_SDRAM_ACTR register
//
//*****************************************************************************
                                              // required an activate command.

//*****************************************************************************
//
// The following are defines for the bit fields in the SDR_EXT_TMNG register
//
//*****************************************************************************
                                              // command timing.

//*****************************************************************************
//
// The following are defines for the bit fields in the INT_RAW register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the INT_MSK register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the INT_MSK_SET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the INT_MSK_CLR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the IO_CTRL register
//
//*****************************************************************************
                                              // IOs

//*****************************************************************************
//
// The following are defines for the bit fields in the IO_STAT register
//
//*****************************************************************************
                                              // IOs

//*****************************************************************************
//
// The following are defines for the bit fields in the MODEL_REL_NUM register
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_epwm.h
//
// TITLE:   Definitions for the C28x EPWM registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the EPWM register offsets
//
//*****************************************************************************
                                              // Register
                                              // Register 2
                                              // Register
                                              // Register 2
                                              // Register
                                              // Source Select Register
                                              // Register
                                              // Register
                                              // Register For Output A
                                              // Control Register For Output A
                                              // Register For Output B
                                              // Control Register For Output B
                                              // Register
                                              // Force Register
                                              // Delay High Resolution Mirror
                                              // Register
                                              // Delay High Resolution Mirror
                                              // Register
                                              // Edge Delay High Resolution
                                              // Register
                                              // Edge Delay Count Register
                                              // Resolution Register
                                              // Register 2
                                              // Select Register
                                              // Register
                                              // Digital Compare A
                                              // Digital Compare B
                                              // Register
                                              // Register
                                              // Register
                                              // Pre-Scale Register
                                              // Register
                                              // Initialization Control
                                              // Register
                                              // Initialization Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Register
                                              // Counter Register
                                              // Register
                                              // Counter Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the TBCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TBCTL2 register
//
//*****************************************************************************
                                              // SYNC Event

//*****************************************************************************
//
// The following are defines for the bit fields in the TBCTR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TBSTS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPCTL register
//
//*****************************************************************************
                                              // Operating Mode
                                              // Operating Mode
                                              // Status
                                              // Status

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPCTL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DBCTL register
//
//*****************************************************************************
                                              // Control
                                              // Control

//*****************************************************************************
//
// The following are defines for the bit fields in the DBCTL2 register
//
//*****************************************************************************
                                              // Select

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCTL register
//
//*****************************************************************************
                                              // Mode
                                              // Mode

//*****************************************************************************
//
// The following are defines for the bit fields in the AQTSRCSEL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the PCCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the HRCNFG register
//
//*****************************************************************************
                                              // Bit

//*****************************************************************************
//
// The following are defines for the bit fields in the HRPWR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the HRMSTEP register
//
//*****************************************************************************
                                              // Value

//*****************************************************************************
//
// The following are defines for the bit fields in the HRPCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GLDCTL register
//
//*****************************************************************************
                                              // event control
                                              // Pulse Selection
                                              // Select Register
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the GLDCFG register
//
//*****************************************************************************
                                              // for TBPRD:TBPRDHR
                                              // for CMPA:CMPAHR
                                              // for CMPB:CMPBHR
                                              // for CMPC
                                              // for CMPD
                                              // for DBRED:DBREDHR
                                              // for DBFED:DBFEDHR
                                              // for DBCTL
                                              // for AQCTLA/A2
                                              // for AQCTLB/B2
                                              // for AQCSFRC

//*****************************************************************************
//
// The following are defines for the bit fields in the EPWMXLINK register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCTLA register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCTLA2 register
//
//*****************************************************************************
                                              // in UP-Count
                                              // in DOWN-Count
                                              // in UP-Count
                                              // in DOWN-Count

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCTLB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCTLB2 register
//
//*****************************************************************************
                                              // in UP-Count
                                              // in DOWN-Count
                                              // in UP-Count
                                              // in DOWN-Count

//*****************************************************************************
//
// The following are defines for the bit fields in the AQSFRC register
//
//*****************************************************************************
                                              // Invoked
                                              // Invoked

//*****************************************************************************
//
// The following are defines for the bit fields in the AQCSFRC register
//
//*****************************************************************************
                                              // output A
                                              // output B

//*****************************************************************************
//
// The following are defines for the bit fields in the DBREDHR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DBRED register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DBFEDHR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DBFED register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TBPHS register
//
//*****************************************************************************
                                              // Phase (8-bits)

//*****************************************************************************
//
// The following are defines for the bit fields in the TBPRDHR register
//
//*****************************************************************************
                                              // register

//*****************************************************************************
//
// The following are defines for the bit fields in the TBPRD register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPA register
//
//*****************************************************************************
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPB register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPC register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the CMPD register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GLDCTL2 register
//
//*****************************************************************************
                                              // mode
                                              // mode

//*****************************************************************************
//
// The following are defines for the bit fields in the TZSEL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TZDCSEL register
//
//*****************************************************************************
                                              // 1
                                              // 2
                                              // 1
                                              // 2

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCTL register
//
//*****************************************************************************
                                              // EPWMxA
                                              // EPWMxB

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCTL2 register
//
//*****************************************************************************
                                              // Count direction is UP
                                              // Count direction is DOWN
                                              // Count direction is UP
                                              // Count direction is DOWN

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCA register
//
//*****************************************************************************
                                              // Count direction is UP
                                              // Count direction is DOWN
                                              // Count direction is UP
                                              // Count direction is DOWN

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCB register
//
//*****************************************************************************
                                              // Count direction is UP
                                              // Count direction is DOWN
                                              // Count direction is UP
                                              // Count direction is DOWN

//*****************************************************************************
//
// The following are defines for the bit fields in the TZEINT register
//
//*****************************************************************************
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable
                                              // Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the TZFLG register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCBCFLG register
//
//*****************************************************************************
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Compare Output A Event 2
                                              // Compare Output B Event 2

//*****************************************************************************
//
// The following are defines for the bit fields in the TZOSTFLG register
//
//*****************************************************************************
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Compare Output A Event 1
                                              // Compare Output B Event 1

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCLR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the TZCBCCLR register
//
//*****************************************************************************
                                              // (CBC1) Trip Latch
                                              // (CBC2) Trip Latch
                                              // (CBC3) Trip Latch
                                              // (CBC4) Trip Latch
                                              // (CBC5) Trip Latch
                                              // (CBC6) Trip Latch
                                              // for CBC
                                              // for CBC

//*****************************************************************************
//
// The following are defines for the bit fields in the TZOSTCLR register
//
//*****************************************************************************
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // Trip Latch
                                              // for OST
                                              // for OST

//*****************************************************************************
//
// The following are defines for the bit fields in the TZFRC register
//
//*****************************************************************************
                                              // Event

//*****************************************************************************
//
// The following are defines for the bit fields in the ETSEL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETPS register
//
//*****************************************************************************
                                              // Bits
                                              // Selection Bits

//*****************************************************************************
//
// The following are defines for the bit fields in the ETFLG register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETCLR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETFRC register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETINTPS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETSOCPS register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the ETCNTINITCTL register
//
//*****************************************************************************
                                              // Force
                                              // Initialization Force
                                              // Initialization Force
                                              // Enable
                                              // Initialization Enable
                                              // Initialization Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the ETCNTINIT register
//
//*****************************************************************************
                                              // Bits
                                              // Initialization Bits
                                              // Initialization Bits

//*****************************************************************************
//
// The following are defines for the bit fields in the DCTRIPSEL register
//
//*****************************************************************************
                                              // Input Select
                                              // Input Select
                                              // Input Select
                                              // Input Select

//*****************************************************************************
//
// The following are defines for the bit fields in the DCACTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DCBCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DCFCTL register
//
//*****************************************************************************
                                              // Select
                                              // Capture Alignment

//*****************************************************************************
//
// The following are defines for the bit fields in the DCCAPCTL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DCFOFFSET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DCFOFFSETCNT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the DCFWINDOW register
//
//*****************************************************************************
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the DCFWINDOWCNT register
//
//*****************************************************************************
                                              // Counter Register

//*****************************************************************************
//
// The following are defines for the bit fields in the DCCAP register
//
//*****************************************************************************
                                              // Register

//*****************************************************************************
//
// The following are defines for the bit fields in the DCAHTRIPSEL register
//
//*****************************************************************************
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux

//*****************************************************************************
//
// The following are defines for the bit fields in the DCALTRIPSEL register
//
//*****************************************************************************
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux

//*****************************************************************************
//
// The following are defines for the bit fields in the DCBHTRIPSEL register
//
//*****************************************************************************
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux

//*****************************************************************************
//
// The following are defines for the bit fields in the DCBLTRIPSEL register
//
//*****************************************************************************
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
                                              // Mux
//###########################################################################
//
// FILE:    hw_gpio.h
//
// TITLE:   Definitions for the C28x GPIO registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the GPIO register offsets
//
//*****************************************************************************
                                              // Period Control (GPIO0 to 31)
                                              // Register (GPIO0 to 15)
                                              // Register (GPIO16 to 31)
                                              // 15)
                                              // to 31)
                                              // (GPIO0 to 31)
                                              // (GPIO0 to 31)
                                              // Registers (GPIO0 to 31)
                                              // Register (GPIO0 to GPIO31)
                                              // (GPIO0 to 15)
                                              // (GPIO16 to 31)
                                              // (GPIO0 to 7)
                                              // (GPIO8 to 15)
                                              // (GPIO16 to 23)
                                              // (GPIO24 to 31)
                                              // Register (GPIO0 to 31)
                                              // (GPIO0 to 31)
                                              // Period Control (GPIO32 to 63)
                                              // Register (GPIO32 to 47)
                                              // Register (GPIO48 to 63)
                                              // to 47)
                                              // to 63)
                                              // (GPIO32 to 63)
                                              // (GPIO32 to 63)
                                              // Registers (GPIO32 to 63)
                                              // Register (GPIO32 to GPIO63)
                                              // register (GPIO32 to GPIO63)
                                              // (GPIO32 to 47)
                                              // (GPIO48 to 63)
                                              // (GPIO32 to 39)
                                              // (GPIO40 to 47)
                                              // (GPIO48 to 55)
                                              // (GPIO56 to 63)
                                              // Register (GPIO32 to 63)
                                              // (GPIO32 to 63)
                                              // Period Control (GPIO64 to 95)
                                              // Register (GPIO64 to 79)
                                              // Register (GPIO80  to 95)
                                              // to 79)
                                              // to 95)
                                              // (GPIO64 to 95)
                                              // (GPIO64 to 95)
                                              // Registers (GPIO64 to 95)
                                              // Register (GPIO64 to GPIO95)
                                              // (GPIO64 to 79)
                                              // (GPIO80  to 95)
                                              // (GPIO64 to 71)
                                              // (GPIO72 to 79)
                                              // (GPIO80  to 87)
                                              // (GPIO88 to 95)
                                              // Register (GPIO64 to 95)
                                              // (GPIO64 to 95)
                                              // Period Control (GPIO96 to 127)
                                              // Register (GPIO96 to 111)
                                              // Register (GPIO112 to 127)
                                              // to 111)
                                              // to 127)
                                              // (GPIO96 to 127)
                                              // (GPIO96 to 127)
                                              // Registers (GPIO96 to 127)
                                              // Register (GPIO96 to GPIO127)
                                              // (GPIO96 to 111)
                                              // (GPIO112 to 127)
                                              // (GPIO96 to 103)
                                              // (GPIO104 to 111)
                                              // (GPIO112 to 119)
                                              // (GPIO120 to 127)
                                              // Register (GPIO96 to 127)
                                              // (GPIO96 to 127)
                                              // Period Control (GPIO128 to
                                              // 159)
                                              // Register (GPIO128 to 143)
                                              // Register (GPIO144  to 159)
                                              // to 143)
                                              // to 159)
                                              // (GPIO128 to 159)
                                              // (GPIO128 to 159)
                                              // Registers (GPIO128 to 159)
                                              // Register (GPIO128 to GPIO159)
                                              // (GPIO128 to 143)
                                              // (GPIO144  to 159)
                                              // (GPIO128 to 135)
                                              // (GPIO136 to 143)
                                              // (GPIO144  to 151)
                                              // (GPIO152 to 159)
                                              // Register (GPIO128 to 159)
                                              // (GPIO128 to 159)
                                              // Period Control (GPIO160 to
                                              // 168)
                                              // Register (GPIO160 to 168)
                                              // to 168)
                                              // (GPIO160 to 168)
                                              // (GPIO160 to 168)
                                              // Registers (GPIO160 to 168)
                                              // Register (GPIO160 to GPIO168)
                                              // (GPIO160 to 168)
                                              // (GPIO160 to 167)
                                              // (GPIO168)
                                              // Register (GPIO160 to 168)
                                              // (GPIO160 to 168)
                                              // 31)
                                              // to 31)
                                              // (GPIO0 to 31)
                                              // (GPIO0 to 31)
                                              // 63)
                                              // (GPIO32 to 63)
                                              // (GPIO32 to 63)
                                              // (GPIO32 to 63)
                                              // 95)
                                              // (GPIO64 to 95)
                                              // (GPIO64 to 95)
                                              // (GPIO64 to 95)
                                              // 127)
                                              // (GPIO96 to 127)
                                              // (GPIO96 to 127)
                                              // (GPIO96 to 127)
                                              // to 159)
                                              // (GPIO128 to 159)
                                              // (GPIO128 to 159)
                                              // (GPIO128 to 159)
                                              // to 168)
                                              // (GPIO160 to 168)
                                              // (GPIO160 to 168)
                                              // (GPIO160 to 168)

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACTRL register
//
//*****************************************************************************
                                              // for GPIO0 to GPIO7
                                              // for GPIO8 to GPIO15
                                              // for GPIO16 to GPIO23
                                              // for GPIO24 to GPIO31

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL1 register
//
//*****************************************************************************
                                              // for GPIO0
                                              // for GPIO1
                                              // for GPIO2
                                              // for GPIO3
                                              // for GPIO4
                                              // for GPIO5
                                              // for GPIO6
                                              // for GPIO7
                                              // for GPIO8
                                              // for GPIO9
                                              // for GPIO10
                                              // for GPIO11
                                              // for GPIO12
                                              // for GPIO13
                                              // for GPIO14
                                              // for GPIO15

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL2 register
//
//*****************************************************************************
                                              // for GPIO16
                                              // for GPIO17
                                              // for GPIO18
                                              // for GPIO19
                                              // for GPIO20
                                              // for GPIO21
                                              // for GPIO22
                                              // for GPIO23
                                              // for GPIO24
                                              // for GPIO25
                                              // for GPIO26
                                              // for GPIO27
                                              // for GPIO28
                                              // for GPIO29
                                              // for GPIO30
                                              // for GPIO31

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAMUX1 register
//
//*****************************************************************************
                                              // for GPIO0
                                              // for GPIO1
                                              // for GPIO2
                                              // for GPIO3
                                              // for GPIO4
                                              // for GPIO5
                                              // for GPIO6
                                              // for GPIO7
                                              // for GPIO8
                                              // for GPIO9
                                              // for GPIO10
                                              // for GPIO11
                                              // for GPIO12
                                              // for GPIO13
                                              // for GPIO14
                                              // for GPIO15

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAMUX2 register
//
//*****************************************************************************
                                              // for GPIO16
                                              // for GPIO17
                                              // for GPIO18
                                              // for GPIO19
                                              // for GPIO20
                                              // for GPIO21
                                              // for GPIO22
                                              // for GPIO23
                                              // for GPIO24
                                              // for GPIO25
                                              // for GPIO26
                                              // for GPIO27
                                              // for GPIO28
                                              // for GPIO29
                                              // for GPIO30
                                              // for GPIO31

//*****************************************************************************
//
// The following are defines for the bit fields in the GPADIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX1 register
//
//*****************************************************************************
                                              // for GPIO0
                                              // for GPIO1
                                              // for GPIO2
                                              // for GPIO3
                                              // for GPIO4
                                              // for GPIO5
                                              // for GPIO6
                                              // for GPIO7
                                              // for GPIO8
                                              // for GPIO9
                                              // for GPIO10
                                              // for GPIO11
                                              // for GPIO12
                                              // for GPIO13
                                              // for GPIO14
                                              // for GPIO15

//*****************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX2 register
//
//*****************************************************************************
                                              // for GPIO16
                                              // for GPIO17
                                              // for GPIO18
                                              // for GPIO19
                                              // for GPIO20
                                              // for GPIO21
                                              // for GPIO22
                                              // for GPIO23
                                              // for GPIO24
                                              // for GPIO25
                                              // for GPIO26
                                              // for GPIO27
                                              // for GPIO28
                                              // for GPIO29
                                              // for GPIO30
                                              // for GPIO31

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACSEL3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACSEL4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPALOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCTRL register
//
//*****************************************************************************
                                              // for GPIO32 to GPIO39
                                              // for GPIO40 to GPIO47
                                              // for GPIO48 to GPIO55
                                              // for GPIO56 to GPIO63

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL1 register
//
//*****************************************************************************
                                              // for GPIO32
                                              // for GPIO33
                                              // for GPIO34
                                              // for GPIO35
                                              // for GPIO36
                                              // for GPIO37
                                              // for GPIO38
                                              // for GPIO39
                                              // for GPIO40
                                              // for GPIO41
                                              // for GPIO42
                                              // for GPIO43
                                              // for GPIO44
                                              // for GPIO45
                                              // for GPIO46
                                              // for GPIO47

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL2 register
//
//*****************************************************************************
                                              // for GPIO48
                                              // for GPIO49
                                              // for GPIO50
                                              // for GPIO51
                                              // for GPIO52
                                              // for GPIO53
                                              // for GPIO54
                                              // for GPIO55
                                              // for GPIO56
                                              // for GPIO57
                                              // for GPIO58
                                              // for GPIO59
                                              // for GPIO60
                                              // for GPIO61
                                              // for GPIO62
                                              // for GPIO63

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBMUX1 register
//
//*****************************************************************************
                                              // for GPIO32
                                              // for GPIO33
                                              // for GPIO34
                                              // for GPIO35
                                              // for GPIO36
                                              // for GPIO37
                                              // for GPIO38
                                              // for GPIO39
                                              // for GPIO40
                                              // for GPIO41
                                              // for GPIO42
                                              // for GPIO43
                                              // for GPIO44
                                              // for GPIO45
                                              // for GPIO46
                                              // for GPIO47

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBMUX2 register
//
//*****************************************************************************
                                              // for GPIO48
                                              // for GPIO49
                                              // for GPIO50
                                              // for GPIO51
                                              // for GPIO52
                                              // for GPIO53
                                              // for GPIO54
                                              // for GPIO55
                                              // for GPIO56
                                              // for GPIO57
                                              // for GPIO58
                                              // for GPIO59
                                              // for GPIO60
                                              // for GPIO61
                                              // for GPIO62
                                              // for GPIO63

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBDIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBAMSEL register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX1 register
//
//*****************************************************************************
                                              // for GPIO32
                                              // for GPIO33
                                              // for GPIO34
                                              // for GPIO35
                                              // for GPIO36
                                              // for GPIO37
                                              // for GPIO38
                                              // for GPIO39
                                              // for GPIO40
                                              // for GPIO41
                                              // for GPIO42
                                              // for GPIO43
                                              // for GPIO44
                                              // for GPIO45
                                              // for GPIO46
                                              // for GPIO47

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX2 register
//
//*****************************************************************************
                                              // for GPIO48
                                              // for GPIO49
                                              // for GPIO50
                                              // for GPIO51
                                              // for GPIO52
                                              // for GPIO53
                                              // for GPIO54
                                              // for GPIO55
                                              // for GPIO56
                                              // for GPIO57
                                              // for GPIO58
                                              // for GPIO59
                                              // for GPIO60
                                              // for GPIO61
                                              // for GPIO62
                                              // for GPIO63

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBLOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCTRL register
//
//*****************************************************************************
                                              // for GPIO64 to GPIO71
                                              // for GPIO72 to GPIO79
                                              // for GPIO80 to GPIO87
                                              // for GPIO88 to GPIO95

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCQSEL1 register
//
//*****************************************************************************
                                              // for GPIO64
                                              // for GPIO65
                                              // for GPIO66
                                              // for GPIO67
                                              // for GPIO68
                                              // for GPIO69
                                              // for GPIO70
                                              // for GPIO71
                                              // for GPIO72
                                              // for GPIO73
                                              // for GPIO74
                                              // for GPIO75
                                              // for GPIO76
                                              // for GPIO77
                                              // for GPIO78
                                              // for GPIO79

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCQSEL2 register
//
//*****************************************************************************
                                              // for GPIO80
                                              // for GPIO81
                                              // for GPIO82
                                              // for GPIO83
                                              // for GPIO84
                                              // for GPIO85
                                              // for GPIO86
                                              // for GPIO87
                                              // for GPIO88
                                              // for GPIO89
                                              // for GPIO90
                                              // for GPIO91
                                              // for GPIO92
                                              // for GPIO93
                                              // for GPIO94
                                              // for GPIO95

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCMUX1 register
//
//*****************************************************************************
                                              // for GPIO64
                                              // for GPIO65
                                              // for GPIO66
                                              // for GPIO67
                                              // for GPIO68
                                              // for GPIO69
                                              // for GPIO70
                                              // for GPIO71
                                              // for GPIO72
                                              // for GPIO73
                                              // for GPIO74
                                              // for GPIO75
                                              // for GPIO76
                                              // for GPIO77
                                              // for GPIO78
                                              // for GPIO79

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCMUX2 register
//
//*****************************************************************************
                                              // for GPIO80
                                              // for GPIO81
                                              // for GPIO82
                                              // for GPIO83
                                              // for GPIO84
                                              // for GPIO85
                                              // for GPIO86
                                              // for GPIO87
                                              // for GPIO88
                                              // for GPIO89
                                              // for GPIO90
                                              // for GPIO91
                                              // for GPIO92
                                              // for GPIO93
                                              // for GPIO94
                                              // for GPIO95

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCDIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCGMUX1 register
//
//*****************************************************************************
                                              // for GPIO64
                                              // for GPIO65
                                              // for GPIO66
                                              // for GPIO67
                                              // for GPIO68
                                              // for GPIO69
                                              // for GPIO70
                                              // for GPIO71
                                              // for GPIO72
                                              // for GPIO73
                                              // for GPIO74
                                              // for GPIO75
                                              // for GPIO76
                                              // for GPIO77
                                              // for GPIO78
                                              // for GPIO79

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCGMUX2 register
//
//*****************************************************************************
                                              // for GPIO80
                                              // for GPIO81
                                              // for GPIO82
                                              // for GPIO83
                                              // for GPIO84
                                              // for GPIO85
                                              // for GPIO86
                                              // for GPIO87
                                              // for GPIO88
                                              // for GPIO89
                                              // for GPIO90
                                              // for GPIO91
                                              // for GPIO92
                                              // for GPIO93
                                              // for GPIO94
                                              // for GPIO95

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCSEL3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCSEL4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCLOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCTRL register
//
//*****************************************************************************
                                              // for GPIO96 to GPIO103
                                              // for GPIO104 to GPIO111
                                              // for GPIO112 to GPIO119
                                              // for GPIO120 to GPIO127

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDQSEL1 register
//
//*****************************************************************************
                                              // for GPIO96
                                              // for GPIO97
                                              // for GPIO98
                                              // for GPIO99
                                              // for GPIO100
                                              // for GPIO101
                                              // for GPIO102
                                              // for GPIO103
                                              // for GPIO104
                                              // for GPIO105
                                              // for GPIO106
                                              // for GPIO107
                                              // for GPIO108
                                              // for GPIO109
                                              // for GPIO110
                                              // for GPIO111

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDQSEL2 register
//
//*****************************************************************************
                                              // for GPIO112
                                              // for GPIO113
                                              // for GPIO114
                                              // for GPIO115
                                              // for GPIO116
                                              // for GPIO117
                                              // for GPIO118
                                              // for GPIO119
                                              // for GPIO120
                                              // for GPIO121
                                              // for GPIO122
                                              // for GPIO123
                                              // for GPIO124
                                              // for GPIO125
                                              // for GPIO126
                                              // for GPIO127

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDMUX1 register
//
//*****************************************************************************
                                              // for GPIO96
                                              // for GPIO97
                                              // for GPIO98
                                              // for GPIO99
                                              // for GPIO100
                                              // for GPIO101
                                              // for GPIO102
                                              // for GPIO103
                                              // for GPIO104
                                              // for GPIO105
                                              // for GPIO106
                                              // for GPIO107
                                              // for GPIO108
                                              // for GPIO109
                                              // for GPIO110
                                              // for GPIO111

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDMUX2 register
//
//*****************************************************************************
                                              // for GPIO112
                                              // for GPIO113
                                              // for GPIO114
                                              // for GPIO115
                                              // for GPIO116
                                              // for GPIO117
                                              // for GPIO118
                                              // for GPIO119
                                              // for GPIO120
                                              // for GPIO121
                                              // for GPIO122
                                              // for GPIO123
                                              // for GPIO124
                                              // for GPIO125
                                              // for GPIO126
                                              // for GPIO127

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDDIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDGMUX1 register
//
//*****************************************************************************
                                              // for GPIO96
                                              // for GPIO97
                                              // for GPIO98
                                              // for GPIO99
                                              // for GPIO100
                                              // for GPIO101
                                              // for GPIO102
                                              // for GPIO103
                                              // for GPIO104
                                              // for GPIO105
                                              // for GPIO106
                                              // for GPIO107
                                              // for GPIO108
                                              // for GPIO109
                                              // for GPIO110
                                              // for GPIO111

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDGMUX2 register
//
//*****************************************************************************
                                              // for GPIO112
                                              // for GPIO113
                                              // for GPIO114
                                              // for GPIO115
                                              // for GPIO116
                                              // for GPIO117
                                              // for GPIO118
                                              // for GPIO119
                                              // for GPIO120
                                              // for GPIO121
                                              // for GPIO122
                                              // for GPIO123
                                              // for GPIO124
                                              // for GPIO125
                                              // for GPIO126
                                              // for GPIO127

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCSEL3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCSEL4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDLOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECTRL register
//
//*****************************************************************************
                                              // for GPIO128 to GPIO135
                                              // for GPIO136 to GPIO143
                                              // for GPIO144 to GPIO151
                                              // for GPIO152 to GPIO159

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEQSEL1 register
//
//*****************************************************************************
                                              // for GPIO128
                                              // for GPIO129
                                              // for GPIO130
                                              // for GPIO131
                                              // for GPIO132
                                              // for GPIO133
                                              // for GPIO134
                                              // for GPIO135
                                              // for GPIO136
                                              // for GPIO137
                                              // for GPIO138
                                              // for GPIO139
                                              // for GPIO140
                                              // for GPIO141
                                              // for GPIO142
                                              // for GPIO143

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEQSEL2 register
//
//*****************************************************************************
                                              // for GPIO144
                                              // for GPIO145
                                              // for GPIO146
                                              // for GPIO147
                                              // for GPIO148
                                              // for GPIO149
                                              // for GPIO150
                                              // for GPIO151
                                              // for GPIO152
                                              // for GPIO153
                                              // for GPIO154
                                              // for GPIO155
                                              // for GPIO156
                                              // for GPIO157
                                              // for GPIO158
                                              // for GPIO159

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEMUX1 register
//
//*****************************************************************************
                                              // for GPIO128
                                              // for GPIO129
                                              // for GPIO130
                                              // for GPIO131
                                              // for GPIO132
                                              // for GPIO133
                                              // for GPIO134
                                              // for GPIO135
                                              // for GPIO136
                                              // for GPIO137
                                              // for GPIO138
                                              // for GPIO139
                                              // for GPIO140
                                              // for GPIO141
                                              // for GPIO142
                                              // for GPIO143

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEMUX2 register
//
//*****************************************************************************
                                              // for GPIO144
                                              // for GPIO145
                                              // for GPIO146
                                              // for GPIO147
                                              // for GPIO148
                                              // for GPIO149
                                              // for GPIO150
                                              // for GPIO151
                                              // for GPIO152
                                              // for GPIO153
                                              // for GPIO154
                                              // for GPIO155
                                              // for GPIO156
                                              // for GPIO157
                                              // for GPIO158
                                              // for GPIO159

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEDIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEGMUX1 register
//
//*****************************************************************************
                                              // for GPIO128
                                              // for GPIO129
                                              // for GPIO130
                                              // for GPIO131
                                              // for GPIO132
                                              // for GPIO133
                                              // for GPIO134
                                              // for GPIO135
                                              // for GPIO136
                                              // for GPIO137
                                              // for GPIO138
                                              // for GPIO139
                                              // for GPIO140
                                              // for GPIO141
                                              // for GPIO142
                                              // for GPIO143

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEGMUX2 register
//
//*****************************************************************************
                                              // for GPIO144
                                              // for GPIO145
                                              // for GPIO146
                                              // for GPIO147
                                              // for GPIO148
                                              // for GPIO149
                                              // for GPIO150
                                              // for GPIO151
                                              // for GPIO152
                                              // for GPIO153
                                              // for GPIO154
                                              // for GPIO155
                                              // for GPIO156
                                              // for GPIO157
                                              // for GPIO158
                                              // for GPIO159

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECSEL3 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECSEL4 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPELOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFCTRL register
//
//*****************************************************************************
                                              // for GPIO160 to GPIO167
                                              // for GPIO168

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFQSEL1 register
//
//*****************************************************************************
                                              // for GPIO160
                                              // for GPIO161
                                              // for GPIO162
                                              // for GPIO163
                                              // for GPIO164
                                              // for GPIO165
                                              // for GPIO166
                                              // for GPIO167
                                              // for GPIO168

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFMUX1 register
//
//*****************************************************************************
                                              // for GPIO160
                                              // for GPIO161
                                              // for GPIO162
                                              // for GPIO163
                                              // for GPIO164
                                              // for GPIO165
                                              // for GPIO166
                                              // for GPIO167
                                              // for GPIO168

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFDIR register
//
//*****************************************************************************
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode
                                              // in GPIO mode

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFPUD register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFINV register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFODR register
//
//*****************************************************************************
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin
                                              // this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFGMUX1 register
//
//*****************************************************************************
                                              // for GPIO160
                                              // for GPIO161
                                              // for GPIO162
                                              // for GPIO163
                                              // for GPIO164
                                              // for GPIO165
                                              // for GPIO166
                                              // for GPIO167
                                              // for GPIO168

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFCSEL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFCSEL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFLOCK register
//
//*****************************************************************************
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin
                                              // pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFCR register
//
//*****************************************************************************
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin
                                              // for this pin

//*****************************************************************************
//
// The following are defines for the bit fields in the GPADAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPASET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPACLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPATOGGLE register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBDAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBSET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBCLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPBTOGGLE register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCDAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCSET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCCLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPCTOGGLE register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDDAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDSET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDCLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPDTOGGLE register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPEDAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPESET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPECLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPETOGGLE register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFDAT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFSET register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFCLEAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the GPFTOGGLE register
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_i2c.h
//
// TITLE:   Definitions for the C28x I2C registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the I2C register offsets
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2COAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CIER register
//
//*****************************************************************************
                                              // enable
                                              // enable
                                              // enable
                                              // enable
                                              // enable
                                              // interrupt enable
                                              // enable

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CSTR register
//
//*****************************************************************************
                                              // bit
                                              // flag bit.
                                              // flag bit
                                              // flag bit.
                                              // flag bit.
                                              // bit.
                                              // bit.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CCLKL register
//
//*****************************************************************************
                                              // value.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CCLKH register
//
//*****************************************************************************
                                              // value.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CCNT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CDRR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CSAR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CDXR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CMDR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CISRC register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CEMDR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CPSC register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CFFTX register
//
//*****************************************************************************
                                              // Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the I2CFFRX register
//
//*****************************************************************************
                                              // Clear
//###########################################################################
//
// FILE:   hw_ints.h
//
// TITLE:  Definitions of interrupt numbers for use with interrupt.c.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// PIE Interrupt Numbers
//
// 0x00FF = PIE Table Row #
// 0xFF00 = PIE Table Column #
// 0xFFFF0000 = PIE Vector ID
//
//*****************************************************************************

// Lower PIE Group 1

// Lower PIE Group 2

// Lower PIE Group 3

// Lower PIE Group 4

// Lower PIE Group 5

// Lower PIE Group 6

// Lower PIE Group 7

// Lower PIE Group 8

// Lower PIE Group 9

// Lower PIE Group 10

// Lower PIE Group 11

// Lower PIE Group 12

// Upper PIE Group 1

// Upper PIE Group 2

// Upper PIE Group 3

// Upper PIE Group 4

// Upper PIE Group 5

// Upper PIE Group 6

// Upper PIE Group 8

// Upper PIE Group 9

// Upper PIE Group 10

// Upper PIE Group 11

// Upper PIE Group 12

//Workaround for  Stellaris code

//Workaround for other interrupts




//###########################################################################
//
// FILE:    hw_memmap.h
//
// TITLE:   Macros defining the memory map of the C28x.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************











//###########################################################################
//
// FILE:   hw_types.h
//
// TITLE:  Type definitions used in ALL driverlib functions.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// Define fake 8 bit types for USB related code.
//
//*****************************************************************************

typedef uint16_t uint8_t;
typedef int16_t int8_t;
	 
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
//Emulated Bitbanded write        
//Emulated Bitbanded read      

//Emulated Bitbanded write
//Emulated Bitbanded read





//###########################################################################
//
// FILE:    hw_uart.h
//
// TITLE:   Definitions for the C28x SCI registers.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the SCI register offsets
//
//*****************************************************************************
                                              // register

//*****************************************************************************
//
// The following are defines for the bit fields in the SCICCR register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCICTL1 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIHBAUD register
//
//*****************************************************************************
                                              // Registers SCIHBAUD

//*****************************************************************************
//
// The following are defines for the bit fields in the SCILBAUD register
//
//*****************************************************************************
                                              // Registers SCILBAUD

//*****************************************************************************
//
// The following are defines for the bit fields in the SCICTL2 register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIRXST register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIRXEMU register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIRXBUF register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCITXBUF register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIFFTX register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIFFRX register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIFFCT register
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the SCIPRI register
//
//*****************************************************************************
//*****************************************************************************
//
// hw_usb.h - Macros for use in accessing the USB registers.
//
// Copyright (c) 2007-2012 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 9453 of the Stellaris Firmware Development Package.
//
//*****************************************************************************


//*****************************************************************************
//
// The following are defines for the Univeral Serial Bus register offsets.
//
//*****************************************************************************
                                            // to End of Frame Timing
                                            // to End of Frame Timing
                                            // Endpoint 0
                                            // Endpoint 0
                                            // Endpoint 1
                                            // Endpoint 1
                                            // Endpoint 1
                                            // 1
                                            // Endpoint 2
                                            // Endpoint 2
                                            // Endpoint 2
                                            // 2
                                            // Endpoint 3
                                            // Endpoint 3
                                            // Endpoint 3
                                            // 3
                                            // Endpoint 4
                                            // Endpoint 4
                                            // Endpoint 4
                                            // 4
                                            // Endpoint 5
                                            // Endpoint 5
                                            // Endpoint 5
                                            // 5
                                            // Endpoint 6
                                            // Endpoint 6
                                            // Endpoint 6
                                            // 6
                                            // Endpoint 7
                                            // Endpoint 7
                                            // Endpoint 7
                                            // 7
                                            // Endpoint 8
                                            // Endpoint 8
                                            // Endpoint 8
                                            // 8
                                            // Endpoint 9
                                            // Endpoint 9
                                            // Endpoint 9
                                            // 9
                                            // Endpoint 10
                                            // Endpoint 10
                                            // 10
                                            // Endpoint 10
                                            // 10
                                            // Endpoint 11
                                            // Endpoint 11
                                            // 11
                                            // Endpoint 11
                                            // 11
                                            // Endpoint 12
                                            // Endpoint 12
                                            // 12
                                            // Endpoint 12
                                            // 12
                                            // Endpoint 13
                                            // Endpoint 13
                                            // 13
                                            // Endpoint 13
                                            // 13
                                            // Endpoint 14
                                            // Endpoint 14
                                            // 14
                                            // Endpoint 14
                                            // 14
                                            // Endpoint 15
                                            // Endpoint 15
                                            // 15
                                            // Endpoint 15
                                            // 15
                                            // 0 Low
                                            // 0 High
                                            // 0
                                            // Endpoint 1
                                            // Endpoint 1 Low
                                            // Endpoint 1 High
                                            // Endpoint 1
                                            // Endpoint 1 Low
                                            // Endpoint 1 High
                                            // 1
                                            // Endpoint 1
                                            // Endpoint 1
                                            // Endpoint 1
                                            // Interval Endpoint 1
                                            // Endpoint 2
                                            // Endpoint 2 Low
                                            // Endpoint 2 High
                                            // Endpoint 2
                                            // Endpoint 2 Low
                                            // Endpoint 2 High
                                            // 2
                                            // Endpoint 2
                                            // Endpoint 2
                                            // Endpoint 2
                                            // Interval Endpoint 2
                                            // Endpoint 3
                                            // Endpoint 3 Low
                                            // Endpoint 3 High
                                            // Endpoint 3
                                            // Endpoint 3 Low
                                            // Endpoint 3 High
                                            // 3
                                            // Endpoint 3
                                            // Endpoint 3
                                            // Endpoint 3
                                            // Interval Endpoint 3
                                            // Endpoint 4
                                            // Endpoint 4 Low
                                            // Endpoint 4 High
                                            // Endpoint 4
                                            // Endpoint 4 Low
                                            // Endpoint 4 High
                                            // 4
                                            // Endpoint 4
                                            // Endpoint 4
                                            // Endpoint 4
                                            // Interval Endpoint 4
                                            // Endpoint 5
                                            // Endpoint 5 Low
                                            // Endpoint 5 High
                                            // Endpoint 5
                                            // Endpoint 5 Low
                                            // Endpoint 5 High
                                            // 5
                                            // Endpoint 5
                                            // Endpoint 5
                                            // Endpoint 5
                                            // Interval Endpoint 5
                                            // Endpoint 6
                                            // Endpoint 6 Low
                                            // Endpoint 6 High
                                            // Endpoint 6
                                            // Endpoint 6 Low
                                            // Endpoint 6 High
                                            // 6
                                            // Endpoint 6
                                            // Endpoint 6
                                            // Endpoint 6
                                            // Interval Endpoint 6
                                            // Endpoint 7
                                            // Endpoint 7 Low
                                            // Endpoint 7 High
                                            // Endpoint 7
                                            // Endpoint 7 Low
                                            // Endpoint 7 High
                                            // 7
                                            // Endpoint 7
                                            // Endpoint 7
                                            // Endpoint 7
                                            // Interval Endpoint 7
                                            // Endpoint 8
                                            // Endpoint 8 Low
                                            // Endpoint 8 High
                                            // Endpoint 8
                                            // Endpoint 8 Low
                                            // Endpoint 8 High
                                            // 8
                                            // Endpoint 8
                                            // Endpoint 8
                                            // Endpoint 8
                                            // Interval Endpoint 8
                                            // Endpoint 9
                                            // Endpoint 9 Low
                                            // Endpoint 9 High
                                            // Endpoint 9
                                            // Endpoint 9 Low
                                            // Endpoint 9 High
                                            // 9
                                            // Endpoint 9
                                            // Endpoint 9
                                            // Endpoint 9
                                            // Interval Endpoint 9
                                            // Endpoint 10
                                            // Endpoint 10 Low
                                            // Endpoint 10 High
                                            // Endpoint 10
                                            // Endpoint 10 Low
                                            // Endpoint 10 High
                                            // 10
                                            // Endpoint 10
                                            // Endpoint 10
                                            // Endpoint 10
                                            // Interval Endpoint 10
                                            // Endpoint 11
                                            // Endpoint 11 Low
                                            // Endpoint 11 High
                                            // Endpoint 11
                                            // Endpoint 11 Low
                                            // Endpoint 11 High
                                            // 11
                                            // Endpoint 11
                                            // Endpoint 11
                                            // Endpoint 11
                                            // Interval Endpoint 11
                                            // Endpoint 12
                                            // Endpoint 12 Low
                                            // Endpoint 12 High
                                            // Endpoint 12
                                            // Endpoint 12 Low
                                            // Endpoint 12 High
                                            // 12
                                            // Endpoint 12
                                            // Endpoint 12
                                            // Endpoint 12
                                            // Interval Endpoint 12
                                            // Endpoint 13
                                            // Endpoint 13 Low
                                            // Endpoint 13 High
                                            // Endpoint 13
                                            // Endpoint 13 Low
                                            // Endpoint 13 High
                                            // 13
                                            // Endpoint 13
                                            // Endpoint 13
                                            // Endpoint 13
                                            // Interval Endpoint 13
                                            // Endpoint 14
                                            // Endpoint 14 Low
                                            // Endpoint 14 High
                                            // Endpoint 14
                                            // Endpoint 14 Low
                                            // Endpoint 14 High
                                            // 14
                                            // Endpoint 14
                                            // Endpoint 14
                                            // Endpoint 14
                                            // Interval Endpoint 14
                                            // Endpoint 15
                                            // Endpoint 15 Low
                                            // Endpoint 15 High
                                            // Endpoint 15
                                            // Endpoint 15 Low
                                            // Endpoint 15 High
                                            // 15
                                            // Endpoint 15
                                            // Endpoint 15
                                            // Endpoint 15
                                            // Interval Endpoint 15
                                            // Block Transfer Endpoint 1
                                            // Block Transfer Endpoint 2
                                            // Block Transfer Endpoint 3
                                            // Block Transfer Endpoint 4
                                            // Block Transfer Endpoint 5
                                            // Block Transfer Endpoint 6
                                            // Block Transfer Endpoint 7
                                            // Block Transfer Endpoint 8
                                            // Block Transfer Endpoint 9
                                            // Block Transfer Endpoint 10
                                            // Block Transfer Endpoint 11
                                            // Block Transfer Endpoint 12
                                            // Block Transfer Endpoint 13
                                            // Block Transfer Endpoint 14
                                            // Block Transfer Endpoint 15
                                            // Disable
                                            // Buffer Disable
                                            // Interrupt Status
                                            // Interrupt Mask
                                            // Interrupt Status and Clear
                                            // Status
                                            // Status and Clear
                                            // Status
                                            // Interrupt Status
                                            // Mask
                                            // Status and Clear
                                            // Interrupt Status
                                            // Mask
                                            // Status and Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FADDR register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_POWER register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXIE register.
//
//*****************************************************************************
                                            // Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXIE register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IE register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FRAME register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPIDX register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TEST register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO0 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FIFO15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DEVCTL register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFIFOADD
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFIFOADD
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CONTIM register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VPLEN register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_FSEOF register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_LSEOF register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR0
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT0
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBADDR15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXHUBPORT15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBADDR15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXHUBPORT15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRL0 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_CSRH0 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_COUNT0 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TYPE0 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_NAKLMT register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXCOUNT15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXINTERVAL15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXINTERVAL15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
// register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
// register.
//
//*****************************************************************************
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
// register.
//
//*****************************************************************************
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable
                                            // Disable

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPC register.
//
//*****************************************************************************
                                            // Configuration

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCRIS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCIM register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_EPCISC register.
//
//*****************************************************************************
                                            // and Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRRIS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRIM register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DRISC register.
//
//*****************************************************************************
                                            // Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_GPCS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDC register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCRIS register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCIM register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_VDCISC register.
//
//*****************************************************************************
                                            // Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVRIS register.
//
//*****************************************************************************
                                            // Status

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVIM register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_IDVISC register.
//
//*****************************************************************************
                                            // and Clear

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_DMASEL register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_PP register.
//
//*****************************************************************************
                                            // controller

//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// USB_O_TXFIFOADD register.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// USB_O_RXFIFOADD register.
//
//*****************************************************************************





// Include files not used with F/BIOS
//###########################################################################
//
// FILE:   F2807x_defaultisr.h
//
// TITLE:  F2807x Device Default Interrupt Service Routines Definitions
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

extern "C" {

//---------------------------------------------------------------------------
// Default Interrupt Service Routine Declarations:
// The following function prototypes are for the
// default ISR routines used with the default PIE vector table.
// This default vector table is found in the F2807x_pievect.h
// file.
interrupt void TIMER1_ISR(void);                      // CPU Timer 1 Interrupt
interrupt void TIMER2_ISR(void);                      // CPU Timer 2 Interrupt
interrupt void DATALOG_ISR(void);                     // Datalogging Interrupt
interrupt void RTOS_ISR(void);                        // RTOS Interrupt
interrupt void EMU_ISR(void);                         // Emulation Interrupt
interrupt void NMI_ISR(void);                         // Non-Maskable Interrupt
interrupt void ILLEGAL_ISR(void);                     // Illegal Operation Trap
interrupt void USER1_ISR(void);                       // User Defined Trap 1
interrupt void USER2_ISR(void);                       // User Defined Trap 2
interrupt void USER3_ISR(void);                       // User Defined Trap 3
interrupt void USER4_ISR(void);                       // User Defined Trap 4
interrupt void USER5_ISR(void);                       // User Defined Trap 5
interrupt void USER6_ISR(void);                       // User Defined Trap 6
interrupt void USER7_ISR(void);                       // User Defined Trap 7
interrupt void USER8_ISR(void);                       // User Defined Trap 8
interrupt void USER9_ISR(void);                       // User Defined Trap 9
interrupt void USER10_ISR(void);                      // User Defined Trap 10
interrupt void USER11_ISR(void);                      // User Defined Trap 11
interrupt void USER12_ISR(void);                      // User Defined Trap 12
interrupt void ADCA1_ISR(void);                       // 1.1 - ADCA Interrupt 1
interrupt void ADCB1_ISR(void);                       // 1.2 - ADCB Interrupt 1
interrupt void XINT1_ISR(void);                       // 1.4 - XINT1 Interrupt
interrupt void XINT2_ISR(void);                       // 1.5 - XINT2 Interrupt
interrupt void ADCD1_ISR(void);                       // 1.6 - ADCD Interrupt 1
interrupt void TIMER0_ISR(void);                      // 1.7 - Timer 0 Interrupt
interrupt void WAKE_ISR(void);                        // 1.8 - Standby and Halt Wakeup Interrupt
interrupt void EPWM1_TZ_ISR(void);                    // 2.1 - ePWM1 Trip Zone Interrupt
interrupt void EPWM2_TZ_ISR(void);                    // 2.2 - ePWM2 Trip Zone Interrupt
interrupt void EPWM3_TZ_ISR(void);                    // 2.3 - ePWM3 Trip Zone Interrupt
interrupt void EPWM4_TZ_ISR(void);                    // 2.4 - ePWM4 Trip Zone Interrupt
interrupt void EPWM5_TZ_ISR(void);                    // 2.5 - ePWM5 Trip Zone Interrupt
interrupt void EPWM6_TZ_ISR(void);                    // 2.6 - ePWM6 Trip Zone Interrupt
interrupt void EPWM7_TZ_ISR(void);                    // 2.7 - ePWM7 Trip Zone Interrupt
interrupt void EPWM8_TZ_ISR(void);                    // 2.8 - ePWM8 Trip Zone Interrupt
interrupt void EPWM1_ISR(void);                       // 3.1 - ePWM1 Interrupt
interrupt void EPWM2_ISR(void);                       // 3.2 - ePWM2 Interrupt
interrupt void EPWM3_ISR(void);                       // 3.3 - ePWM3 Interrupt
interrupt void EPWM4_ISR(void);                       // 3.4 - ePWM4 Interrupt
interrupt void EPWM5_ISR(void);                       // 3.5 - ePWM5 Interrupt
interrupt void EPWM6_ISR(void);                       // 3.6 - ePWM6 Interrupt
interrupt void EPWM7_ISR(void);                       // 3.7 - ePWM7 Interrupt
interrupt void EPWM8_ISR(void);                       // 3.8 - ePWM8 Interrupt
interrupt void ECAP1_ISR(void);                       // 4.1 - eCAP1 Interrupt
interrupt void ECAP2_ISR(void);                       // 4.2 - eCAP2 Interrupt
interrupt void ECAP3_ISR(void);                       // 4.3 - eCAP3 Interrupt
interrupt void ECAP4_ISR(void);                       // 4.4 - eCAP4 Interrupt
interrupt void ECAP5_ISR(void);                       // 4.5 - eCAP5 Interrupt
interrupt void ECAP6_ISR(void);                       // 4.6 - eCAP6 Interrupt
interrupt void EQEP1_ISR(void);                       // 5.1 - eQEP1 Interrupt
interrupt void EQEP2_ISR(void);                       // 5.2 - eQEP2 Interrupt
interrupt void EQEP3_ISR(void);                       // 5.3 - eQEP3 Interrupt
interrupt void SPIA_RX_ISR(void);                     // 6.1 - SPIA Receive Interrupt
interrupt void SPIA_TX_ISR(void);                     // 6.2 - SPIA Transmit Interrupt
interrupt void SPIB_RX_ISR(void);                     // 6.3 - SPIB Receive Interrupt
interrupt void SPIB_TX_ISR(void);                     // 6.4 - SPIB Transmit Interrupt
interrupt void MCBSPA_RX_ISR(void);                   // 6.5 - McBSPA Receive Interrupt
interrupt void MCBSPA_TX_ISR(void);                   // 6.6 - McBSPA Transmit Interrupt
interrupt void MCBSPB_RX_ISR(void);                   // 6.7 - McBSPB Receive Interrupt
interrupt void MCBSPB_TX_ISR(void);                   // 6.8 - McBSPB Transmit Interrupt
interrupt void DMA_CH1_ISR(void);                     // 7.1 - DMA Channel 1 Interrupt
interrupt void DMA_CH2_ISR(void);                     // 7.2 - DMA Channel 2 Interrupt
interrupt void DMA_CH3_ISR(void);                     // 7.3 - DMA Channel 3 Interrupt
interrupt void DMA_CH4_ISR(void);                     // 7.4 - DMA Channel 4 Interrupt
interrupt void DMA_CH5_ISR(void);                     // 7.5 - DMA Channel 5 Interrupt
interrupt void DMA_CH6_ISR(void);                     // 7.6 - DMA Channel 6 Interrupt
interrupt void I2CA_ISR(void);                        // 8.1 - I2CA Interrupt 1
interrupt void I2CA_FIFO_ISR(void);                   // 8.2 - I2CA Interrupt 2
interrupt void I2CB_ISR(void);                        // 8.3 - I2CB Interrupt 1
interrupt void I2CB_FIFO_ISR(void);                   // 8.4 - I2CB Interrupt 2
interrupt void SCIC_RX_ISR(void);                     // 8.5 - SCIC Receive Interrupt
interrupt void SCIC_TX_ISR(void);                     // 8.6 - SCIC Transmit Interrupt
interrupt void SCID_RX_ISR(void);                     // 8.7 - SCID Receive Interrupt
interrupt void SCID_TX_ISR(void);                     // 8.8 - SCID Transmit Interrupt
interrupt void SCIA_RX_ISR(void);                     // 9.1 - SCIA Receive Interrupt
interrupt void SCIA_TX_ISR(void);                     // 9.2 - SCIA Transmit Interrupt
interrupt void SCIB_RX_ISR(void);                     // 9.3 - SCIB Receive Interrupt
interrupt void SCIB_TX_ISR(void);                     // 9.4 - SCIB Transmit Interrupt
interrupt void CANA0_ISR(void);                       // 9.5 - CANA Interrupt 0
interrupt void CANA1_ISR(void);                       // 9.6 - CANA Interrupt 1
interrupt void CANB0_ISR(void);                       // 9.7 - CANB Interrupt 0
interrupt void CANB1_ISR(void);                       // 9.8 - CANB Interrupt 1
interrupt void ADCA_EVT_ISR(void);                    // 10.1 - ADCA Event Interrupt
interrupt void ADCA2_ISR(void);                       // 10.2 - ADCA Interrupt 2
interrupt void ADCA3_ISR(void);                       // 10.3 - ADCA Interrupt 3
interrupt void ADCA4_ISR(void);                       // 10.4 - ADCA Interrupt 4
interrupt void ADCB_EVT_ISR(void);                    // 10.5 - ADCB Event Interrupt
interrupt void ADCB2_ISR(void);                       // 10.6 - ADCB Interrupt 2
interrupt void ADCB3_ISR(void);                       // 10.7 - ADCB Interrupt 3
interrupt void ADCB4_ISR(void);                       // 10.8 - ADCB Interrupt 4
interrupt void CLA1_1_ISR(void);                      // 11.1 - CLA1 Interrupt 1
interrupt void CLA1_2_ISR(void);                      // 11.2 - CLA1 Interrupt 2
interrupt void CLA1_3_ISR(void);                      // 11.3 - CLA1 Interrupt 3
interrupt void CLA1_4_ISR(void);                      // 11.4 - CLA1 Interrupt 4
interrupt void CLA1_5_ISR(void);                      // 11.5 - CLA1 Interrupt 5
interrupt void CLA1_6_ISR(void);                      // 11.6 - CLA1 Interrupt 6
interrupt void CLA1_7_ISR(void);                      // 11.7 - CLA1 Interrupt 7
interrupt void CLA1_8_ISR(void);                      // 11.8 - CLA1 Interrupt 8
interrupt void XINT3_ISR(void);                       // 12.1 - XINT3 Interrupt
interrupt void XINT4_ISR(void);                       // 12.2 - XINT4 Interrupt
interrupt void XINT5_ISR(void);                       // 12.3 - XINT5 Interrupt
interrupt void VCU_ISR(void);                         // 12.6 - VCU Interrupt
interrupt void FPU_OVERFLOW_ISR(void);                // 12.7 - FPU Overflow Interrupt
interrupt void FPU_UNDERFLOW_ISR(void);               // 12.8 - FPU Underflow Interrupt
interrupt void IPC0_ISR(void);                        // 1.13 - IPC Interrupt 0
interrupt void IPC1_ISR(void);                        // 1.14 - IPC Interrupt 1
interrupt void IPC2_ISR(void);                        // 1.15 - IPC Interrupt 2
interrupt void IPC3_ISR(void);                        // 1.16 - IPC Interrupt 3
interrupt void EPWM9_TZ_ISR(void);                    // 2.9 - ePWM9 Trip Zone Interrupt
interrupt void EPWM10_TZ_ISR(void);                   // 2.10 - ePWM10 Trip Zone Interrupt
interrupt void EPWM11_TZ_ISR(void);                   // 2.11 - ePWM11 Trip Zone Interrupt
interrupt void EPWM12_TZ_ISR(void);                   // 2.12 - ePWM12 Trip Zone Interrupt
interrupt void EPWM9_ISR(void);                       // 3.9 - ePWM9 Interrupt
interrupt void EPWM10_ISR(void);                      // 3.10 - ePWM10 Interrupt
interrupt void EPWM11_ISR(void);                      // 3.11 - ePWM11 Interrupt
interrupt void EPWM12_ISR(void);                      // 3.12 - ePWM12 Interrupt
interrupt void SD1_ISR(void);                         // 5.9 - SD1 Interrupt
interrupt void SD2_ISR(void);                         // 5.10 - SD2 Interrupt
interrupt void SPIC_RX_ISR(void);                     // 6.9 - SPIC Receive Interrupt
interrupt void SPIC_TX_ISR(void);                     // 6.10 - SPIC Transmit Interrupt
interrupt void USBA_ISR(void);                        // 9.15 - USBA Interrupt
interrupt void ADCD_EVT_ISR(void);                    // 10.13 - ADCD Event Interrupt
interrupt void ADCD2_ISR(void);                       // 10.14 - ADCD Interrupt 2
interrupt void ADCD3_ISR(void);                       // 10.15 - ADCD Interrupt 3
interrupt void ADCD4_ISR(void);                       // 10.16 - ADCD Interrupt 4
interrupt void EMIF_ERROR_ISR(void);                  // 12.9 - EMIF Error Interrupt
interrupt void RAM_CORRECTABLE_ERROR_ISR(void);       // 12.10 - RAM Correctable Error Interrupt
interrupt void FLASH_CORRECTABLE_ERROR_ISR(void);     // 12.11 - Flash Correctable Error Interrupt
interrupt void RAM_ACCESS_VIOLATION_ISR(void);        // 12.12 - RAM Access Violation Interrupt
interrupt void SYS_PLL_SLIP_ISR(void);                // 12.13 - System PLL Slip Interrupt
interrupt void AUX_PLL_SLIP_ISR(void);                // 12.14 - Auxiliary PLL Slip Interrupt
interrupt void CLA_OVERFLOW_ISR(void);                // 12.15 - CLA Overflow Interrupt
interrupt void CLA_UNDERFLOW_ISR(void);               // 12.16 - CLA Underflow Interrupt

// Catch-all for PIE Reserved Locations for testing purposes:
interrupt void PIE_RESERVED_ISR(void);                // Reserved ISR
interrupt void EMPTY_ISR(void);                       // Only does a return
interrupt void NOTUSED_ISR(void);                     // Unused ISR
}


//===========================================================================
// End of file.
//===========================================================================

extern void F28x_usDelay(long LoopCount);
// DO NOT MODIFY THIS LINE.

//---------------------------------------------------------------------------
// Useful Timer Operations:
//
// Start Timer:

// Stop Timer:

// Reload Timer With period Value:

// Read 32-Bit Timer Value:

// Read 32-Bit Period Value:

// Start Timer:

// Stop Timer:

// Reload Timer With period Value:

// Read 32-Bit Timer Value:

// Read 32-Bit Period Value:

}


//===========================================================================
// End of file.
//===========================================================================

//###########################################################################
//
// FILE:  Flash2823x_API_Config.h
//
// TITLE: F2823x Flash Algo's - User Settings
//
// NOTE:  This file contains user defined settings that
//        are used by the F2823x Flash APIs.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################


extern "C" {

/*-----------------------------------------------------------------------------
CLK Config 
Clock Domain: 
CPU CLK
PLLSYSCLK

SYSCLK
PERx.SYSCLK

LSPCLK
PERx.LSPCLK

-----------------------------------------------------------------------------*/
//Osillator Clock(OSCCLK) 
//One of INTOSC1/INTOSC2/XTAL


//System Clock(PLLSYSCLK) 
//Derived from OSCCLK,used to control registers/GS RAMs/GPIO qualification/NMI watchdog timer/CPU Timer0/1/2
//Fpllsysclk = Foscclk*(SYSPLLMULT.IMULT + SYSPLLMULT.FMULT)/SYSCLKDIVSEL.PLLSYSCLKDIV

//CPU Clock(CPUCLK) = PLLSYSCLK 
//used to clock CPU/CPU coprocessor/ CPU Private RAMs(M0，M1，D0，D1)/boot ROM/ Flash wrapper

//SYSCLK/PERx.SYSCLK = PLLSYSCLK
//used to clock CLA/DMA/most peripherals
//Each peripheral clock has its own independent clock
//ePWM,EMIF1 EMIF2 clocks each have an additional/2 divider, disabled by PERCLKDIVSEL register






//LSPCLK/PERx.LSPCLK
//Derived from SYSCLK,used to clock SCI/SPI/McBSP


/*-----------------------------------------------------------------------------
Peripheral Clock Enable Config
-----------------------------------------------------------------------------*/

//PCLKCR0


//PCLKCR1

//PCLKCR2

//PCLKCR3



//PCLKCR4



//PCLKCR6


//PCLKCR7

//PCLKCR8


//PCLKCR9



//PCLKCR10




//PCLKCR11


//PCLKCR12


//PCLKCR13


//PCLKCR14

//PCLKCR16


/*-----------------------------------------------------------------------------
GPIO Config 
Clock Domain: PLLSYSCLK
-----------------------------------------------------------------------------*/

/*
#define GPIO_INPUT		0
#define GPIO_OUTPUT		1


//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3,
//QUAL6, and ASYNC) take up two bits and must be in the order specified.

//For input pins, the valid flags are:
//GPIO_PULLUP	Enable pull-up
//GPIO_INVERT	Enable input polarity inversion
//GPIO_SYNC		Synchronize the input latch to PLLSYSCLK (default -- you don't need to specify this)
//GPIO_QUAL3	Use 3-sample qualification
//GPIO_QUAL6	Use 6-sample qualification
//GPIO_ASYNC	Do not use synchronization or qualification
//(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed)


//For output pins, the valid flags are:
//GPIO_OPENDRAIN	Output in open drain mode
//GPIO_PULLUP		If open drain enabled, also enable the pull-up
//and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above.

*/
//#define Array(PinMuxTable,0,0)  PinMuxTable[][]
//#define PinMuxTable[0][0]   100         #define PinMuxTable[0][1]   GPIO_INPUT

/*-----------------------------------------------------------------------------
ADC Config 
Clock Domain: PERx.SYSCLK
-----------------------------------------------------------------------------*/
/*-----------ADCA--------------*/
//时钟分频

/*-----------ADCB--------------*/


/*-----------ADCD--------------*/

/*-----------------------------------------------------------------------------
CMPSS Config 
Clock Domain: PERx.SYSCLK
-----------------------------------------------------------------------------*/

/*-----------CMPSS1--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS2--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS3--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS4--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS5--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置


/*-----------CMPSS6--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS7--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置

/*-----------CMPSS8--------------*/
//Comparator配置


//Ramp Generator配置


//Digital Filter配置


//输出路径配置


/*-----------------------------------------------------------------------------
CAP Config 
Clock Domain: PERx.SYSCLK

-----------------------------------------------------------------------------*/



/*-----------CAP1--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择


/*-----------CAP2--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择

/*-----------CAP3--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择

/*-----------CAP4--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择

/*-----------CAP5--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择

/*-----------CAP6--------------*/
//时钟分频

//捕获沿选择

//计数器计数模式选择


/*-----------------------------------------------------------------------------
I2C Config 
Clock Domain: PERx.SYSCLK

I2C-bus clock frequecy = (I2C input clock frequency)/(IPSC + 1)[(ICCL + d)+(ICCH + d)]
	IPSC     		d
 	 0     			7
 	 1      		6
Greater than 1      5
-----------------------------------------------------------------------------*/
/*-----------I2CA--------------*/
//从机地址


//时钟分频

//FIFO Enabel

/*-----------I2CB--------------*/
//从机地址

//时钟分频

//从机地址

/*-----------------------------------------------------------------------------
McBSP Config 
Clock Domain: PERx.LSPCLK

-----------------------------------------------------------------------------*/
/*-----------McBSPA--------------*/
//SPI模式
//0-1h: clock stop mode is disabled
//2h:Clock stop mode,without clock delya
//3h:Clock stop mode,with half-cycle colck delay



//数据长度
								//12_BITS 0x1
							    //16_BITS 0x2
							    //20_BITS 0x3
								//24_BITS 0x4
				 				//32_BITS 0x5



//时钟及帧同步宽度



/*-----------McBSPB--------------*/
//SPI模式

//数据长度


//时钟及帧同步宽度


/*-----------------------------------------------------------------------------
SCI Config 
Clock Domain: PERx.LSPCLK

-----------------------------------------------------------------------------*/
/*-----------SCIA--------------*/
//波特率配置

//数据长度

//FIFO使能

/*-----------SCIB--------------*/

//波特率配置

//数据长度

//FIFO使能

/*-----------SCIC--------------*/

//波特率配置

//数据长度

//FIFO使能


/*-----------SCID--------------*/

//波特率配置

//数据长度

//FIFO使能


/*-----------------------------------------------------------------------------
SPI Config  
Clock Domain: PERx.LSPCLK

SPI Baud Rate = LSPCLK/(SPIBRR + 1)

SPI Clocking scheme      		 CLKPOLARITY         CLK_PHASE
Rising edge without delay            0                   0
Rising edge with delay               0                   1
Falling edge without delay           1                   0
Falling edge with delay              1                   1

-----------------------------------------------------------------------------*/
/*-----------SPIA--------------*/
//波特率配置

//数据长度

//时钟机制


/*-----------SPIB--------------*/
//波特率配置

//数据长度

//时钟机制

/*-----------SPIC--------------*/
//波特率配置

//数据长度

//时钟机制

/*-----------------------------------------------------------------------------
CAN Config  
Clock Domain: CAN Bit Clock

-----------------------------------------------------------------------------*/
/*-----------CANA--------------*/
//CAN时钟源选择

//时钟源频率

//波特率配置



/*-----------CANB--------------*/
//CAN时钟源选择

//时钟源频率

//波特率配置


/*-----------------------------------------------------------------------------
PWM Config 
Clock Domain: PERx.SYSCLK

-----------------------------------------------------------------------------*/

/*-----------EPWM1--------------*/

//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM2--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM3--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM4--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM5--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM6--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM7--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM8--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM9--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM10--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM11--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用

/*-----------EPWM12--------------*/
//--TB设置，关于时基的周期	

//--CC设置，计数器比较，产生计数器匹配信号


//--AQ设置

//--DB设置

//--ET设置，事件触发模块，产生事件触发信号，供其他模块使用


}




/*==========================================================*/
/* Title		:	Drivers.cpp	        	*/
/* Description	: 	ControlChip definition		   */
/* Date			:	Oct.2007		   */
/*==========================================================*/


/*==========================================================*/
/* Title		:	GPIODrv.h								*/
/* Description	: 	Class_GPIODrv definition				*/
/* Date			:	Oct.2007								*/
/*==========================================================*/


//============================================================
//	Class_GPIODrv与外部的接口
//	1)调用
//	2)
//============================================================
class Class_GPIODrv
{
	private:

	public:
		void	Drv_InitGPIO(void);		
		void 	Drv_GPIO_EnableUnbondedIOPullups(void);
		void 	Drv_InitGpioToDefaltValue(void);
		void 	Drv_GPIO_SetupPinMux(Uint16 pin, Uint16 cpu, Uint16 peripheral);
		void 	Drv_GPIO_SetupPinOptions(Uint16 pin, Uint16 output, Uint16 flags);
		void	Drv_GPIO_SetupPinDirection(Uint16 pin, Uint16 output);
		void	Drv_GPIO_SetupPinValue(Uint16 pin, Uint16 pinvalue);
             inline  void    Drv_GPIO_FPGAReset(void);           //向FPGA发送RESET信号
             inline  void    Drv_GPIO_FPGAResetClear(void);      //清除FPGARESET信号
             void       InitECap1Gpio(Uint16 pin);
             void       InitECap2Gpio(Uint16 pin);
             void       InitECap3Gpio(Uint16 pin);
             void       InitECap4Gpio(Uint16 pin);



		
		


		
};


//============================================================
// End of file.
//============================================================

/*==========================================================*/
/* Title		:	PWMDrv.h								*/
/* Description	: 	Class_PWMDrv definition					*/
/* Date			:	Oct.2007								*/
/*==========================================================*/

class Class_PWMDrv
{
	public:
		void	Drv_InitPWM(void);								//初始化

		void	Drv_Int_PWMActive(void);
		void	Drv_Int_PWMInactive(void);


};


//============================================================
// End of file.
//============================================================

/*==========================================================*/
/* Title		:	SysDrv.h								*/
/* Description	: 	Class_SysDrv definition					*/
/* Date			:	Oct.2007								*/
/*==========================================================*/



//============================================================
//	Class_SysDrv与外部的接口
//	1)调用objWatchDogDrv.Drv_DisableDog()
//	2)
//============================================================
class Class_SysDrv
{
	private:
//		struct	PIE_VECT_TABLE	m_st_PieVectTableInit;
		INT16	m_i16_ClockMissing;							//时钟丢失标志位
		UINT16	m_u16_DSPRevision;							//DSP版本号
	public:
		void	Drv_SysCtrlInit(void);		//系统初始化

		void	Drv_InitPeripherals(void);						//外设初始化		
		void	Drv_InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel);		
		void	Drv_SysIntOsc1Sel();
		void	Drv_SysIntOsc2Sel();
		void	Drv_SysXtalOscSel();


		
		//This function initializes the clocks to the peripheral modules.
		void	Drv_InitPeripheralClocks(void);
		
		//This function initializes the PIE control registers to a known state.				
		void	Drv_InitPieCtrl(void);	
		
		//This function initializes the PIE vector table to a known state.
		//This function must be executed after boot time.					
		void	Drv_InitPieVectTable(void);	
		void	Drv_InitCpuTimers(void);	
		//This function deal the PIE module and CPU interrupts,used in interrupt program				
		void	Drv_Int_InterruptFlagClear(void);	
		void	Drv_InitPIE(void);		
		void	Drv_InitInterrupts(void);					//This function enable the PIE module and CPU interrupts
		void	Drv_DSPVersionSet(void);					//DSP版本号设置

};

//============================================================
// End of file.
//============================================================
/*==========================================================*/
/* Title		:	WatchDogDrv.h							*/
/* Description	: 	Class_WatchDogDrv definition			*/
/* Date			:	Oct.2007								*/
/*==========================================================*/


//============================================================
//	Class_WatchDogDrv与外部的接口
//	1)调用
//	2)
//============================================================
class Class_WatchDogDrv
{
	private:

	public:
		void	Drv_DisableDog(void);						//This function disables the watchdog timer
		void	Drv_EnableDog(void);						//This function enables the watchdog timer.
		void	Drv_KickDog(void);							//This function resets the watchdog timer.
};


//============================================================
// End of file.
//============================================================
/*==========================================================*/
/* Title		:	RAMDrv.h								*/
/* Description	: 	Class_RAMDrv definition					*/
/* Date			:	Oct.2007								*/
/*==========================================================*/











//============================================================
//	Class_RAMDrv与外部的接口
//	1)调用
//	2)
//============================================================
class Class_RAMDrv
{
	private:
		UINT16	m_u16_RamCheckErr;		
	public:
		void	Drv_Init(void);								//初始化
		void	Drv_RamCheck(void);							//内存自检及RAM清零
		void	Drv_MemCopy(UINT16 *SourceAddr, UINT16* SourceEndAddr, UINT16* DestAddr);//程序ｃｏｐｙ函数
		void	Drv_CLAMemCopy(UINT32 *SourceAddr, UINT32* SourceEndAddr, UINT32* DestAddr);//CLA程序ｃｏｐｙ函数
};


//============================================================
// End of file.
//============================================================
/*==========================================================*/
/* Title		:	FlashDrv.h								*/
/* Description	: 	Class_FlashDrv definition				*/
/* Date			:	Oct.2007								*/
/*==========================================================*/



//============================================================
//	Class_FlashDrv与外部的接口
//	1)调用
//	2)
//============================================================
class Class_FlashDrv
{
	private:

	public:
	void Drv_InitFlash(void);								//初始化
};



//============================================================
// End of file.
//============================================================


//#include "XintfDrv.h"

//============================================================
// End of file.
//============================================================
/* =================================================================================
File name:       PARK.H (IQ version)                    
                    
Originator:	Digital Control Systems Group
			Texas Instruments

Description: 
Header file containing constants, data type definitions, and 
function prototypes for the PARK.

=====================================================================================*/
//#include "IQmathLib.h"
//#include "clarke.h"
/* =================================================================================
File name:        DMCTYPE.H                    
                    
Originator:	Digital Control Systems Group
			Texas Instruments

Description: DMC data type definition file.
=====================================================================================
 History:
-------------------------------------------------------------------------------------
 04-15-2005	Version 3.20                                                  
------------------------------------------------------------------------------*/
 

//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//

typedef int             int16;
typedef long            int32;
typedef unsigned int    Uint16;
typedef unsigned long   Uint32;
typedef float           float32;
typedef long double     float64;



//#include "park.h"
//#include "sqrt.h"
/******************************************************************************
Copyright (c)	      2007 ENPC Corporation, All Rights Reserved
Original Author:    

Latest Revision:
    Author: 
    Date: 2007/08/09
    Change: 
******************************************************************************/

//-------------------------------------------------------------------
//Head files
//------------------------------------------------------------------------------
//内存检测宏开关




//-----------------------------------------------------------------------------
// Public Constants and Macro Definitions

//----------------------------------------------------------------
//变量描述符定义 





typedef char*		   LPSTR;
typedef const char*	   LPCSTR;

typedef unsigned long  DWORD;
typedef unsigned char  BOOL;
typedef unsigned char  BYTE;
typedef unsigned short WORD;
typedef int            INT16;
//typedef unsigned int   UINT;
typedef unsigned int   UINT16;
typedef unsigned int   UINT;
typedef long           LONG;
//typedef short		   INT16;
//typedef unsigned short UINT16;

typedef UINT           WPARAM;
typedef LONG           LPARAM;
typedef LONG           LRESULT;
typedef int            HWND;
typedef int            HINSTANCE;
typedef	unsigned char  UCHAR;

typedef unsigned char* ICON;




//#define	UINT16	unsigned short
//#define   INT16	short





//----------------------------------------------------------
//数据存储类型




//-----------------------------------------------------------------
//FlashUpdate 标志
//#define	MON_FIRMWARE_UPDATE	3	//监控软件升级

//-----------------------------------------------------------------
//整流或逆变对监控量的支持情况宏定义

//----------------------------------------------------------------
//整流侧、逆变侧共用部分的DataFlag宏定义									

//整流侧DataFlag宏定义

//逆变侧Dataflag宏定义
//--------------------------------------------------------------------
//Flash Update Flag

//--------------------------------------------------------------
//位操作


//-----------------------------------------------------------------
//AC记录状态

//--------------------------------------------------------------------------
//external IO status

//--------------------------------------------------------------------------
//系统故障类型定义


//以下故障发生，将导致系统复位

//以下故障发生时，系统进入维护模式，需手动复位




//------------------------------------------------------------------------
//最大值最小值

//--------------------------------------------------------------------
//debug


//#define	DEBUG_CODE	1









 

	

//后台通信调试信息

//模块通信调试信息

//配置文件调试信息

//主线程调试信息


//dry_Temp debug info

//断言宏

//-----------------------------------------------------------------------------
//BOOL 值







/*==========================================================*/
/* Title        :   PubFuncs.h                          */
/* Description  :   PubFuncs.h   definition             */
/* Copyright     :     ENPC Corporation                            */
/* Version        :     V000                                           */
/* Author         :     Zhuo Qingfeng                             */
/* Date            :    Apr.2013                               */
/* Contributor:                                          */
/*==========================================================*/


//常用宏


extern const int16 i16_SinTab[1030];

class       Class_System;           //0x1101
class       Class_PowCANProtocol;       //0x1301
class       Class_PowCANScheduler;  //0x1201
class       Class_DigitalIO;            //0x1401
class       Class_Switches;         //0x1501
class       Class_Bypass;               //0x1601
class       Class_Inverter;         //0x1701
class       Class_Output;               //0x1801
class       Class_Parallel;             //0x1901
class       Class_DCBus;                //0x1A01
class       Class_InverterAlgorithm;    //0x1B01
class       Class_MonitorInterface;     //0x1C01
class       Class_Load;             //0x1D01
class       Class_InverterControl;      //0x1E01
class       Class_Transfer;         //0x1F01
class       Class_LBS;              //0x2001
class       Class_Service;          //0x2101
class       Class_ECO;              //0x2201
class       Class_FaultRecord;          //0x2301
class       Class_EEPROM;           //0x2401
class       Class_SelfAgingAlgorithm;   //0x2501
class       Class_Debug;                //0x2601
class       Class_FlashUpdate;      //0x2801
class       Class_FPGAFlash;            //0x2901
class       Class_FPGAConfig;           //0x2A01
class       SysCanProtocol;         //0x2B01
class       SysCanApp;              //0x2C01
class       SysCanDataExchg;

extern      Class_System                objSystem;
extern      Class_PowCANProtocol        objPowCANPro;
extern      Class_PowCANScheduler       objPowCANSched;
extern      Class_DigitalIO             objDigitalIO;
extern      Class_Switches              objSwitches;
extern      Class_Bypass                objBypass;
extern      Class_Inverter              objInverter;
extern      Class_Output                objOutput;
extern      Class_Parallel              objParallel;
extern      Class_DCBus                 objDCBus;
extern      Class_InverterAlgorithm     objInvAlg;
extern      Class_MonitorInterface      objMonInterface;
extern      Class_Load                  objLoad;
extern      Class_InverterControl       objInvCtrl;
extern      Class_Transfer              objXfer;
extern      Class_LBS                   objLBS;
extern      Class_Service               objService;
extern      Class_ECO                   objECO;
extern      Class_FaultRecord           objFaultRecord;
extern      Class_EEPROM                objEEPROM;
extern      Class_SelfAgingAlgorithm    objSelfAgingAlg;
extern      Class_Debug                 objDebug;
extern      Class_FlashUpdate           objFlashUpdate;
extern      Class_FPGAFlash             objFPGAFlash;
extern      Class_FPGAConfig            objFPGAConfig;
//-----System CAN 相关定义--------
extern      SysCanProtocol              objProtocol;
extern      SysCanApp                   objSysCanApp;
//应用层消息处理对象
extern      SysCanDataExchg             objDataExchg;

volatile unsigned long g_bErrFlag = 0;
volatile unsigned long g_ulTxMsgCount = 0;
volatile unsigned long g_ulRxMsgCount = 0;

//---------------------------------------

// 开方表的物理意义:sqrt(x*2^16),其中x为查表中的数据from 1 to 1023;开方出来的数据定标为Q12格式
// Q8输入，Q12输出
const int SqrtTab[1026]=
{
    256,256,362,443,512,572,627,677,724,768,
    810,849,887,923,958,991,1024,1056,1086,1116,
    1145,1173,1201,1228,1254,1280,1305,1330,1355,1379,
    1402,1425,1448,1471,1493,1515,1536,1557,1578,1599,
    1619,1639,1659,1679,1698,1717,1736,1755,1774,1792,
    1810,1828,1846,1864,1881,1899,1916,1933,1950,1966,
    1983,1999,2016,2032,2048,2064,2080,2095,2111,2126,
    2142,2157,2172,2187,2202,2217,2232,2246,2261,2275,
    2290,2304,2318,2332,2346,2360,2374,2388,2401,2415,
    2429,2442,2455,2469,2482,2495,2508,2521,2534,2547,
    2560,2573,2585,2598,2611,2623,2636,2648,2660,2673,
    2685,2697,2709,2721,2733,2745,2757,2769,2781,2793,
    2804,2816,2828,2839,2851,2862,2874,2885,2896,2908,
    2919,2930,2941,2952,2963,2974,2985,2996,3007,3018,
    3029,3040,3051,3061,3072,3083,3093,3104,3114,3125,
    3135,3146,3156,3167,3177,3187,3197,3208,3218,3228,
    3238,3248,3258,3268,3278,3288,3298,3308,3318,3328,
    3338,3348,3357,3367,3377,3387,3396,3406,3415,3425,
    3435,3444,3454,3463,3473,3482,3491,3501,3510,3519,
    3529,3538,3547,3556,3566,3575,3584,3593,3602,3611,
    3620,3629,3638,3647,3656,3665,3674,3683,3692,3701,
    3710,3719,3727,3736,3745,3754,3762,3771,3780,3788,
    3797,3806,3814,3823,3831,3840,3849,3857,3866,3874,
    3882,3891,3899,3908,3916,3924,3933,3941,3949,3958,
    3966,3974,3982,3991,3999,4007,4015,4023,4031,4040,
    4048,4056,4064,4072,4080,4088,4096,4104,4112,4120,
    4128,4136,4144,4152,4160,4167,4175,4183,4191,4199,
    4207,4214,4222,4230,4238,4245,4253,4261,4268,4276,
    4284,4291,4299,4307,4314,4322,4329,4337,4344,4352,
    4360,4367,4375,4382,4389,4397,4404,4412,4419,4427,
    4434,4441,4449,4456,4464,4471,4478,4485,4493,4500,
    4507,4515,4522,4529,4536,4544,4551,4558,4565,4572,
    4579,4587,4594,4601,4608,4615,4622,4629,4636,4643,
    4650,4658,4665,4672,4679,4686,4693,4700,4707,4713,
    4720,4727,4734,4741,4748,4755,4762,4769,4776,4782,
    4789,4796,4803,4810,4817,4823,4830,4837,4844,4851,
    4857,4864,4871,4877,4884,4891,4898,4904,4911,4918,
    4924,4931,4938,4944,4951,4957,4964,4971,4977,4984,
    4990,4997,5003,5010,5017,5023,5030,5036,5043,5049,
    5056,5062,5069,5075,5081,5088,5094,5101,5107,5114,
    5120,5126,5133,5139,5146,5152,5158,5165,5171,5177,
    5184,5190,5196,5203,5209,5215,5221,5228,5234,5240,
    5246,5253,5259,5265,5271,5278,5284,5290,5296,5302,
    5309,5315,5321,5327,5333,5339,5345,5352,5358,5364,
    5370,5376,5382,5388,5394,5400,5406,5412,5418,5425,
    5431,5437,5443,5449,5455,5461,5467,5473,5479,5485,
    5491,5497,5503,5508,5514,5520,5526,5532,5538,5544,
    5550,5556,5562,5568,5574,5579,5585,5591,5597,5603,
    5609,5615,5620,5626,5632,5638,5644,5649,5655,5661,
    5667,5673,5678,5684,5690,5696,5701,5707,5713,5719,
    5724,5730,5736,5741,5747,5753,5759,5764,5770,5776,
    5781,5787,5793,5798,5804,5810,5815,5821,5826,5832,
    5838,5843,5849,5855,5860,5866,5871,5877,5882,5888,
    5894,5899,5905,5910,5916,5921,5927,5932,5938,5943,
    5949,5954,5960,5965,5971,5976,5982,5987,5993,5998,
    6004,6009,6015,6020,6026,6031,6036,6042,6047,6053,
    6058,6063,6069,6074,6080,6085,6090,6096,6101,6107,
    6112,6117,6123,6128,6133,6139,6144,6149,6155,6160,
    6165,6171,6176,6181,6187,6192,6197,6202,6208,6213,
    6218,6223,6229,6234,6239,6245,6250,6255,6260,6265,
    6271,6276,6281,6286,6292,6297,6302,6307,6312,6318,
    6323,6328,6333,6338,6343,6349,6354,6359,6364,6369,
    6374,6379,6385,6390,6395,6400,6405,6410,6415,6420,
    6426,6431,6436,6441,6446,6451,6456,6461,6466,6471,
    6476,6481,6486,6492,6497,6502,6507,6512,6517,6522,
    6527,6532,6537,6542,6547,6552,6557,6562,6567,6572,
    6577,6582,6587,6592,6597,6602,6607,6612,6616,6621,
    6626,6631,6636,6641,6646,6651,6656,6661,6666,6671,
    6676,6681,6685,6690,6695,6700,6705,6710,6715,6720,
    6725,6729,6734,6739,6744,6749,6754,6759,6763,6768,
    6773,6778,6783,6788,6792,6797,6802,6807,6812,6817,
    6821,6826,6831,6836,6841,6845,6850,6855,6860,6864,
    6869,6874,6879,6883,6888,6893,6898,6903,6907,6912,
    6917,6921,6926,6931,6936,6940,6945,6950,6955,6959,
    6964,6969,6973,6978,6983,6987,6992,6997,7001,7006,
    7011,7016,7020,7025,7030,7034,7039,7043,7048,7053,
    7057,7062,7067,7071,7076,7081,7085,7090,7094,7099,
    7104,7108,7113,7118,7122,7127,7131,7136,7141,7145,
    7150,7154,7159,7163,7168,7173,7177,7182,7186,7191,
    7195,7200,7204,7209,7214,7218,7223,7227,7232,7236,
    7241,7245,7250,7254,7259,7263,7268,7272,7277,7281,
    7286,7290,7295,7299,7304,7308,7313,7317,7322,7326,
    7331,7335,7340,7344,7349,7353,7357,7362,7366,7371,
    7375,7380,7384,7389,7393,7397,7402,7406,7411,7415,
    7420,7424,7428,7433,7437,7442,7446,7450,7455,7459,
    7464,7468,7472,7477,7481,7486,7490,7494,7499,7503,
    7507,7512,7516,7520,7525,7529,7534,7538,7542,7547,
    7551,7555,7560,7564,7568,7573,7577,7581,7586,7590,
    7594,7599,7603,7607,7611,7616,7620,7624,7629,7633,
    7637,7642,7646,7650,7654,7659,7663,7667,7671,7676,
    7680,7684,7689,7693,7697,7701,7706,7710,7714,7718,
    7723,7727,7731,7735,7740,7744,7748,7752,7756,7761,
    7765,7769,7773,7778,7782,7786,7790,7794,7799,7803,
    7807,7811,7815,7820,7824,7828,7832,7836,7840,7845,
    7849,7853,7857,7861,7865,7870,7874,7878,7882,7886,
    7890,7895,7899,7903,7907,7911,7915,7919,7924,7928,
    7932,7936,7940,7944,7948,7952,7957,7961,7965,7969,
    7973,7977,7981,7985,7989,7994,7998,8002,8006,8010,
    8014,8018,8022,8026,8030,8034,8039,8043,8047,8051,
    8055,8059,8063,8067,8071,8075,8079,8083,8087,8091,
    8095,8099,8104,8108,8112,8116,8120,8124,8128,8132,
    8136,8140,8144,8148,8152,8156,8160,8164,8168,8172,
    8176,8180,8184,8188,8192,8192
};

// 开方表的物理意义:sqrt(2^23/(x*2^16)),其中x为查表中的数据from 1 to 1023,最终开方出来的数为Q11格式
// Q8输入，Q11输出
const int InvSqrtTab[1026] =
{
    32767,32767,23170,18919,16384,14654,13377,12385,11585,10923,
    10362,9880,9459,9088,8758,8461,8192,7947,7723,7517,
    7327,7151,6986,6833,6689,6554,6426,6306,6193,6085,
    5983,5885,5793,5704,5620,5539,5461,5387,5316,5247,
    5181,5118,5056,4997,4940,4885,4831,4780,4730,4681,
    4634,4588,4544,4501,4459,4418,4379,4340,4303,4266,
    4230,4196,4162,4128,4096,4064,4033,4003,3974,3945,
    3917,3889,3862,3835,3809,3784,3759,3734,3710,3687,
    3664,3641,3619,3597,3575,3554,3533,3513,3493,3473,
    3454,3435,3416,3398,3380,3362,3344,3327,3310,3293,
    3277,3261,3245,3229,3213,3198,3183,3168,3153,3139,
    3124,3110,3096,3083,3069,3056,3042,3029,3017,3004,
    2991,2979,2967,2955,2943,2931,2919,2908,2896,2885,
    2874,2863,2852,2841,2831,2820,2810,2800,2789,2779,
    2769,2760,2750,2740,2731,2721,2712,2703,2694,2684,
    2675,2667,2658,2649,2641,2632,2624,2615,2607,2599,
    2591,2582,2574,2567,2559,2551,2543,2536,2528,2521,
    2513,2506,2499,2491,2484,2477,2470,2463,2456,2449,
    2442,2436,2429,2422,2416,2409,2403,2396,2390,2384,
    2377,2371,2365,2359,2353,2347,2341,2335,2329,2323,
    2317,2311,2306,2300,2294,2289,2283,2278,2272,2267,
    2261,2256,2251,2245,2240,2235,2230,2224,2219,2214,
    2209,2204,2199,2194,2189,2185,2180,2175,2170,2165,
    2161,2156,2151,2147,2142,2138,2133,2129,2124,2120,
    2115,2111,2106,2102,2098,2093,2089,2085,2081,2077,
    2072,2068,2064,2060,2056,2052,2048,2044,2040,2036,
    2032,2028,2024,2021,2017,2013,2009,2005,2002,1998,
    1994,1991,1987,1983,1980,1976,1972,1969,1965,1962,
    1958,1955,1951,1948,1944,1941,1938,1934,1931,1928,
    1924,1921,1918,1914,1911,1908,1905,1901,1898,1895,
    1892,1889,1886,1882,1879,1876,1873,1870,1867,1864,
    1861,1858,1855,1852,1849,1846,1843,1840,1838,1835,
    1832,1829,1826,1823,1820,1818,1815,1812,1809,1807,
    1804,1801,1798,1796,1793,1790,1788,1785,1782,1780,
    1777,1774,1772,1769,1767,1764,1762,1759,1757,1754,
    1752,1749,1747,1744,1742,1739,1737,1734,1732,1729,
    1727,1725,1722,1720,1718,1715,1713,1710,1708,1706,
    1704,1701,1699,1697,1694,1692,1690,1688,1685,1683,
    1681,1679,1677,1674,1672,1670,1668,1666,1664,1661,
    1659,1657,1655,1653,1651,1649,1647,1645,1643,1640,
    1638,1636,1634,1632,1630,1628,1626,1624,1622,1620,
    1618,1616,1614,1612,1610,1609,1607,1605,1603,1601,
    1599,1597,1595,1593,1591,1589,1588,1586,1584,1582,
    1580,1578,1577,1575,1573,1571,1569,1568,1566,1564,
    1562,1560,1559,1557,1555,1553,1552,1550,1548,1546,
    1545,1543,1541,1540,1538,1536,1535,1533,1531,1529,
    1528,1526,1525,1523,1521,1520,1518,1516,1515,1513,
    1511,1510,1508,1507,1505,1503,1502,1500,1499,1497,
    1496,1494,1493,1491,1489,1488,1486,1485,1483,1482,
    1480,1479,1477,1476,1474,1473,1471,1470,1468,1467,
    1465,1464,1463,1461,1460,1458,1457,1455,1454,1452,
    1451,1450,1448,1447,1445,1444,1443,1441,1440,1438,
    1437,1436,1434,1433,1431,1430,1429,1427,1426,1425,
    1423,1422,1421,1419,1418,1417,1415,1414,1413,1411,
    1410,1409,1408,1406,1405,1404,1402,1401,1400,1399,
    1397,1396,1395,1393,1392,1391,1390,1388,1387,1386,
    1385,1383,1382,1381,1380,1379,1377,1376,1375,1374,
    1373,1371,1370,1369,1368,1367,1365,1364,1363,1362,
    1361,1359,1358,1357,1356,1355,1354,1352,1351,1350,
    1349,1348,1347,1346,1344,1343,1342,1341,1340,1339,
    1338,1337,1336,1334,1333,1332,1331,1330,1329,1328,
    1327,1326,1325,1323,1322,1321,1320,1319,1318,1317,
    1316,1315,1314,1313,1312,1311,1310,1309,1308,1307,
    1306,1304,1303,1302,1301,1300,1299,1298,1297,1296,
    1295,1294,1293,1292,1291,1290,1289,1288,1287,1286,
    1285,1284,1283,1282,1281,1280,1279,1278,1277,1276,
    1275,1275,1274,1273,1272,1271,1270,1269,1268,1267,
    1266,1265,1264,1263,1262,1261,1260,1259,1258,1258,
    1257,1256,1255,1254,1253,1252,1251,1250,1249,1248,
    1247,1247,1246,1245,1244,1243,1242,1241,1240,1239,
    1239,1238,1237,1236,1235,1234,1233,1232,1231,1231,
    1230,1229,1228,1227,1226,1225,1225,1224,1223,1222,
    1221,1220,1219,1219,1218,1217,1216,1215,1214,1214,
    1213,1212,1211,1210,1209,1209,1208,1207,1206,1205,
    1205,1204,1203,1202,1201,1201,1200,1199,1198,1197,
    1197,1196,1195,1194,1193,1193,1192,1191,1190,1189,
    1189,1188,1187,1186,1186,1185,1184,1183,1182,1182,
    1181,1180,1179,1179,1178,1177,1176,1176,1175,1174,
    1173,1173,1172,1171,1170,1170,1169,1168,1167,1167,
    1166,1165,1164,1164,1163,1162,1161,1161,1160,1159,
    1159,1158,1157,1156,1156,1155,1154,1153,1153,1152,
    1151,1151,1150,1149,1149,1148,1147,1146,1146,1145,
    1144,1144,1143,1142,1142,1141,1140,1139,1139,1138,
    1137,1137,1136,1135,1135,1134,1133,1133,1132,1131,
    1131,1130,1129,1129,1128,1127,1127,1126,1125,1125,
    1124,1123,1123,1122,1121,1121,1120,1119,1119,1118,
    1117,1117,1116,1115,1115,1114,1114,1113,1112,1112,
    1111,1110,1110,1109,1108,1108,1107,1106,1106,1105,
    1105,1104,1103,1103,1102,1101,1101,1100,1100,1099,
    1098,1098,1097,1097,1096,1095,1095,1094,1093,1093,
    1092,1092,1091,1090,1090,1089,1089,1088,1087,1087,
    1086,1086,1085,1084,1084,1083,1083,1082,1082,1081,
    1080,1080,1079,1079,1078,1077,1077,1076,1076,1075,
    1075,1074,1073,1073,1072,1072,1071,1070,1070,1069,
    1069,1068,1068,1067,1067,1066,1065,1065,1064,1064,
    1063,1063,1062,1061,1061,1060,1060,1059,1059,1058,
    1058,1057,1056,1056,1055,1055,1054,1054,1053,1053,
    1052,1052,1051,1050,1050,1049,1049,1048,1048,1047,
    1047,1046,1046,1045,1045,1044,1044,1043,1042,1042,
    1041,1041,1040,1040,1039,1039,1038,1038,1037,1037,
    1036,1036,1035,1035,1034,1034,1033,1033,1032,1032,
    1031,1031,1030,1030,1029,1029,1028,1028,1027,1027,
    1026,1026,1025,1025,1024,1024
};

// 周期点数倒数表
// Q0输入(125@80Hz~333@30Hz)，Q15输出
const int InvPointCntTab[209] =
{
    262,260,258,256,254,252,250,248,246,245,
    243,241,239,237,236,234,232,231,229,228,
    226,224,223,221,220,218,217,216,214,213,
    211,210,209,207,206,205,204,202,201,200,
    199,197,196,195,194,193,192,191,189,188,
    187,186,185,184,183,182,181,180,179,178,
    177,176,175,174,173,172,172,171,170,169,
    168,167,166,165,165,164,163,162,161,161,
    160,159,158,158,157,156,155,155,154,153,
    152,152,151,150,150,149,148,148,147,146,
    146,145,144,144,143,142,142,141,141,140,
    139,139,138,138,137,137,136,135,135,134,
    134,133,133,132,132,131,131,130,130,129,
    129,128,128,127,127,126,126,125,125,124,
    124,123,123,122,122,121,121,120,120,120,
    119,119,118,118,117,117,117,116,116,115,
    115,115,114,114,113,113,113,112,112,111,
    111,111,110,110,110,109,109,109,108,108,
    107,107,107,106,106,106,105,105,105,104,
    104,104,103,103,103,102,102,102,101,101,
    101,101,100,100,100,99,99,99,98
};


extern "C"
{
    int abs(int);
    INT32 labs(INT32);
}


//--------------------公共函数-------------------

int   igap(int curr_value, const FLAG_TABLE *f_table, int old_flag);

unsigned int u16_FPGA_Flash_CANInit;


//===========================================================================
// End of file.
//===========================================================================






/*==========================================================*/
/* Title        :   Inverter.h                                                  */
/* Description  :   Class_Inverter definition                                       */
/* Copyright     :     ENPC Corporation                            */
/* Version        :     V000                                           */
/* Author         :     Zhuo Qingfeng                             */
/* Date            :    Apr.2013                               */
/* Contributor:                                          */
/*==========================================================*/


class Class_Inverter
{
public:

    int           m_i16I1stFiltIndex1_0;
    int           m_i16I1stFiltIndex2_0;

    int           m_i16Ia1stPFiltArray1_0[95];
    INT32           m_i32Ia1stPFiltSum1_0;
    int           m_i16Ia1stQFiltArray1_0[95];
    INT32           m_i32Ia1stQFiltSum1_0;

    int           m_i16Ib1stPFiltArray1_0[95];
    INT32           m_i32Ib1stPFiltSum1_0;
    int           m_i16Ib1stQFiltArray1_0[95];
    INT32           m_i32Ib1stQFiltSum1_0;

    int           m_i16Ic1stPFiltArray1_0[95];
    INT32           m_i32Ic1stPFiltSum1_0;
    int           m_i16Ic1stQFiltArray1_0[95];
    INT32           m_i32Ic1stQFiltSum1_0;

    int           m_i16Ia1stPFiltArray2_0[105];
    INT32           m_i32Ia1stPFiltSum2_0;
    int           m_i16Ia1stQFiltArray2_0[105];
    INT32           m_i32Ia1stQFiltSum2_0;

    int           m_i16Ib1stPFiltArray2_0[105];
    INT32           m_i32Ib1stPFiltSum2_0;
    int           m_i16Ib1stQFiltArray2_0[105];
    INT32           m_i32Ib1stQFiltSum2_0;

    int           m_i16Ic1stPFiltArray2_0[105];
    INT32           m_i32Ic1stPFiltSum2_0;
    int           m_i16Ic1stQFiltArray2_0[105];
    INT32           m_i32Ic1stQFiltSum2_0;


private:
    int           m_i16DTheta;                        //显示PF正负用,一个中断所对应的度数

public:
    void                App_InvVarInit(void);

     void     Dat_Int_InvCurrPQCalc(void);


};




//===========================================================================
// End of file.
//===========================================================================








interrupt	void     EPWM_INT_ISR(void);






//



//###########################################################################
//
// FILE:    F2807x_GlobalVariableDefs.c
//
// TITLE:   F2807x Global Variables and Data Section Pragmas.
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################



//---------------------------------------------------------------------------
// Define Global Peripheral Variables:
//
//----------------------------------------
#pragma DATA_SECTION("AdcaRegsFile")
volatile struct ADC_REGS AdcaRegs;

#pragma DATA_SECTION("AdcbRegsFile")
volatile struct ADC_REGS AdcbRegs;

#pragma DATA_SECTION("AdcdRegsFile")
volatile struct ADC_REGS AdcdRegs;

//----------------------------------------
#pragma DATA_SECTION("AdcaResultFile")
volatile struct ADC_RESULT_REGS AdcaResultRegs;

//----------------------------------------
#pragma DATA_SECTION("AdcbResultFile")
volatile struct ADC_RESULT_REGS AdcbResultRegs;

//----------------------------------------
#pragma DATA_SECTION("AdcdResultFile")
volatile struct ADC_RESULT_REGS AdcdResultRegs;

//----------------------------------------
#pragma DATA_SECTION("AnalogSubsysRegsFile")
volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;


//----------------------------------------
#pragma DATA_SECTION("Cmpss1RegsFile")
volatile struct CMPSS_REGS Cmpss1Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss2RegsFile")
volatile struct CMPSS_REGS Cmpss2Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss3RegsFile")
volatile struct CMPSS_REGS Cmpss3Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss4RegsFile")
volatile struct CMPSS_REGS Cmpss4Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss5RegsFile")
volatile struct CMPSS_REGS Cmpss5Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss6RegsFile")
volatile struct CMPSS_REGS Cmpss6Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss7RegsFile")
volatile struct CMPSS_REGS Cmpss7Regs;

//----------------------------------------
#pragma DATA_SECTION("Cmpss8RegsFile")
volatile struct CMPSS_REGS Cmpss8Regs;

//----------------------------------------
#pragma DATA_SECTION("DacaRegsFile")
volatile struct DAC_REGS DacaRegs;

//----------------------------------------
#pragma DATA_SECTION("DacbRegsFile")
volatile struct DAC_REGS DacbRegs;

//----------------------------------------
#pragma DATA_SECTION("DaccRegsFile")
volatile struct DAC_REGS DaccRegs;
//----------------------------------------

#pragma DATA_SECTION("Cla1RegsFile")
volatile struct CLA_REGS Cla1Regs;
//----------------------------------------
#pragma DATA_SECTION("Cla1SoftIntRegsFile")
volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs;
//----------------------------------------
#pragma DATA_SECTION("ClkCfgRegsFile")
volatile struct CLK_CFG_REGS ClkCfgRegs;

//----------------------------------------
#pragma DATA_SECTION("CpuSysRegsFile")
volatile struct CPU_SYS_REGS CpuSysRegs;

//----------------------------------------
#pragma DATA_SECTION("CpuTimer0RegsFile")
volatile struct CPUTIMER_REGS CpuTimer0Regs;

//----------------------------------------
#pragma DATA_SECTION("CpuTimer1RegsFile")
volatile struct CPUTIMER_REGS CpuTimer1Regs;

//----------------------------------------
#pragma DATA_SECTION("CpuTimer2RegsFile")
volatile struct CPUTIMER_REGS CpuTimer2Regs;

//----------------------------------------
#pragma DATA_SECTION("DcsmZ1RegsFile")
volatile struct DCSM_Z1_REGS DcsmZ1Regs;

//----------------------------------------
#pragma DATA_SECTION("DcsmZ2RegsFile")
volatile struct DCSM_Z2_REGS DcsmZ2Regs;

//----------------------------------------
#pragma DATA_SECTION("DcsmCommonRegsFile")
volatile struct DCSM_COMMON_REGS DcsmCommonRegs;

//----------------------------------------
#pragma DATA_SECTION("DcsmZ1OtpFile")
volatile struct DCSM_Z1_OTP DcsmZ1Otp;

//----------------------------------------
#pragma DATA_SECTION("DcsmZ2OtpFile")
volatile struct DCSM_Z2_OTP DcsmZ2Otp;

//----------------------------------------
#pragma DATA_SECTION("DmaRegsFile")
volatile struct DMA_REGS DmaRegs;

//----------------------------------------
#pragma DATA_SECTION("DmaClaSrcSelRegsFile")
volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;

//----------------------------------------
#pragma DATA_SECTION("DevCfgRegsFile")
volatile struct DEV_CFG_REGS DevCfgRegs;

//----------------------------------------
#pragma DATA_SECTION("ECap1RegsFile")
volatile struct ECAP_REGS ECap1Regs;

//----------------------------------------
#pragma DATA_SECTION("ECap2RegsFile")
volatile struct ECAP_REGS ECap2Regs;

//----------------------------------------
#pragma DATA_SECTION("ECap3RegsFile")
volatile struct ECAP_REGS ECap3Regs;

//----------------------------------------
#pragma DATA_SECTION("ECap4RegsFile")
volatile struct ECAP_REGS ECap4Regs;

//----------------------------------------
#pragma DATA_SECTION("ECap5RegsFile")
volatile struct ECAP_REGS ECap5Regs;

//----------------------------------------
#pragma DATA_SECTION("ECap6RegsFile")
volatile struct ECAP_REGS ECap6Regs;

//----------------------------------------
#pragma DATA_SECTION("Emif1RegsFile")
volatile struct EMIF_REGS  Emif1Regs;

//----------------------------------------
#pragma DATA_SECTION("EQep1RegsFile")
volatile struct EQEP_REGS EQep1Regs;

//----------------------------------------
#pragma DATA_SECTION("EQep2RegsFile")
volatile struct EQEP_REGS EQep2Regs;

//----------------------------------------
#pragma DATA_SECTION("EQep3RegsFile")
volatile struct EQEP_REGS EQep3Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm1RegsFile")
volatile struct EPWM_REGS EPwm1Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm2RegsFile")
volatile struct EPWM_REGS EPwm2Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm3RegsFile")
volatile struct EPWM_REGS EPwm3Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm4RegsFile")
volatile struct EPWM_REGS EPwm4Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm5RegsFile")
volatile struct EPWM_REGS EPwm5Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm6RegsFile")
volatile struct EPWM_REGS EPwm6Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm7RegsFile")
volatile struct EPWM_REGS EPwm7Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm8RegsFile")
volatile struct EPWM_REGS EPwm8Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm9RegsFile")
volatile struct EPWM_REGS EPwm9Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm10RegsFile")
volatile struct EPWM_REGS EPwm10Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm11RegsFile")
volatile struct EPWM_REGS EPwm11Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwm12RegsFile")
volatile struct EPWM_REGS EPwm12Regs;

//----------------------------------------
#pragma DATA_SECTION("EPwmXbarRegsFile")
volatile struct EPWM_XBAR_REGS EPwmXbarRegs;

//----------------------------------------
#pragma DATA_SECTION("GpioCtrlRegsFile")
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;

//----------------------------------------
#pragma DATA_SECTION("GpioDataRegsFile")
volatile struct GPIO_DATA_REGS GpioDataRegs;

//----------------------------------------
#pragma DATA_SECTION("InputXbarRegsFile")
volatile struct INPUT_XBAR_REGS InputXbarRegs;

//----------------------------------------
#pragma DATA_SECTION("XbarRegsFile")
volatile struct XBAR_REGS XbarRegs;

//----------------------------------------
#pragma DATA_SECTION("OutputXbarRegsFile")
volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;

//----------------------------------------
#pragma DATA_SECTION("I2caRegsFile")
volatile struct I2C_REGS I2caRegs;

//----------------------------------------
#pragma DATA_SECTION("I2cbRegsFile")
volatile struct I2C_REGS I2cbRegs;

//----------------------------------------
#pragma DATA_SECTION("McbspaRegsFile")
volatile struct McBSP_REGS McbspaRegs;

//----------------------------------------
#pragma DATA_SECTION("RomPrefetchRegsFile")
volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;

//----------------------------------------
#pragma DATA_SECTION("MemCfgRegsFile")
volatile struct MEM_CFG_REGS MemCfgRegs;

//----------------------------------------
#pragma DATA_SECTION("Emif1ConfigRegsFile")
volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;

//----------------------------------------
#pragma DATA_SECTION("RomWaitStateRegsFile")
volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;

//----------------------------------------
#pragma DATA_SECTION("AccessProtectionRegsFile")
volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;

//----------------------------------------
#pragma DATA_SECTION("MemoryErrorRegsFile")
volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;

//----------------------------------------
#pragma DATA_SECTION("McbspbRegsFile")
volatile struct McBSP_REGS McbspbRegs;

//----------------------------------------
#pragma DATA_SECTION("NmiIntruptRegsFile")
volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;

//----------------------------------------
#pragma DATA_SECTION("PieCtrlRegsFile")
volatile struct PIE_CTRL_REGS PieCtrlRegs;

//----------------------------------------
#pragma DATA_SECTION("PieVectTableFile")
volatile struct PIE_VECT_TABLE PieVectTable;

//----------------------------------------
#pragma DATA_SECTION("SciaRegsFile")
volatile struct SCI_REGS SciaRegs;

//----------------------------------------
#pragma DATA_SECTION("ScibRegsFile")
volatile struct SCI_REGS ScibRegs;

//----------------------------------------
#pragma DATA_SECTION("ScicRegsFile")
volatile struct SCI_REGS ScicRegs;

//----------------------------------------
#pragma DATA_SECTION("ScidRegsFile")
volatile struct SCI_REGS ScidRegs;

//----------------------------------------
#pragma DATA_SECTION("SpiaRegsFile")
volatile struct SPI_REGS SpiaRegs;

//----------------------------------------
#pragma DATA_SECTION("SpibRegsFile")
volatile struct SPI_REGS SpibRegs;

//----------------------------------------
#pragma DATA_SECTION("SpicRegsFile")
volatile struct SPI_REGS SpicRegs;

//----------------------------------------
#pragma DATA_SECTION("Sdfm1RegsFile")
volatile struct SDFM_REGS Sdfm1Regs;

//----------------------------------------
#pragma DATA_SECTION("Sdfm2RegsFile")
volatile struct SDFM_REGS Sdfm2Regs;


//----------------------------------------
#pragma DATA_SECTION("SyncSocRegsFile")
volatile struct SYNC_SOC_REGS SyncSocRegs;

//----------------------------------------
#pragma DATA_SECTION("WdRegsFile")
volatile struct WD_REGS WdRegs;

//----------------------------------------
#pragma DATA_SECTION("XintRegsFile")
volatile struct XINT_REGS XintRegs;


//--------------------------------------
#pragma DATA_SECTION("EmuKeyVar");
Uint16 EmuKey;

//----------------------------------------
#pragma DATA_SECTION("EmuBModeVar");
Uint16 EmuBMode;

//----------------------------------------
#pragma DATA_SECTION("Flash0EccRegsFile")
volatile struct FLASH_ECC_REGS Flash0EccRegs;

//----------------------------------------
#pragma DATA_SECTION("Flash0CtrlRegsFile")
volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;


//===========================================================================
// End of file.
//===========================================================================



/*==========================================================*/
/* Title		:	Drivers.cpp	        	*/
/* Description	: 	ControlChip definition		   */
/* Date			:	Oct.2007		   */
/*==========================================================*/






//#include "XintfDrv.h"

//============================================================
// End of file.
//============================================================

Class_FlashDrv objFlashDrv;

Class_GPIODrv objGPIODrv;



Class_PWMDrv objPWMDrv;
Class_RAMDrv objRAMDrv;



Class_SysDrv objSysDrv;

 Class_WatchDogDrv objWatchDogDrv;

 



void	Class_GPIODrv::Drv_InitGPIO(void)
{
    int i16tmp;
    Drv_InitGpioToDefaltValue();

    Drv_GPIO_SetupPinMux(43, 0x0, 0);
    Drv_GPIO_SetupPinOptions(43, 1, 0);
			
}

void Class_GPIODrv::Drv_InitGpioToDefaltValue(void)
{
    volatile Uint32 *gpioBaseAddr;
    Uint16 regOffset;

    //Disable pin locks
    __asm(" EALLOW");
    GpioCtrlRegs.GPALOCK.all = 0x00000000;
    GpioCtrlRegs.GPBLOCK.all = 0x00000000;
    GpioCtrlRegs.GPCLOCK.all = 0x00000000;
    GpioCtrlRegs.GPDLOCK.all = 0x00000000;
    GpioCtrlRegs.GPELOCK.all = 0x00000000;
    GpioCtrlRegs.GPFLOCK.all = 0x00000000;

    //Fill all registers with zeros. Writing to each register separately
    //for six GPIO modules would make this function *very* long. Fortunately,
    //we'd be writing them all with zeros anyway, so this saves a lot of space.
    gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
    for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
    {
        //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
        //0x0C in each register group of 0x40 words. Since this is a
        //32-bit pointer, the addresses must be divided by 2.
        if (regOffset % (0x40/2) != (0x0C/2))
            gpioBaseAddr[regOffset] = 0x00000000;
    }

    gpioBaseAddr = (Uint32 *)&GpioDataRegs;
    for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
    {
        gpioBaseAddr[regOffset] = 0x00000000;
    }

    __asm(" EDIS");
}


void Class_GPIODrv::Drv_GPIO_SetupPinMux(Uint16 pin, Uint16 cpu, Uint16 peripheral)
{
    volatile Uint32 *gpioBaseAddr;
    volatile Uint32 *mux, *gmux, *csel;
    Uint16 pin32, pin16, pin8;

    pin32 = pin % 32;
    pin16 = pin % 16;
    pin8 = pin % 8;
    gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (pin/32)*(0x40/2);

    //Sanity check for valid cpu and peripheral values
    if (cpu > 0x3 || peripheral > 0xF)
        return;

    //Create pointers to the appropriate registers. This is a workaround
    //for the way GPIO registers are defined. The standard definition
    //in the header file makes it very easy to do named accesses of one
    //register or bit, but hard to do arbitrary numerical accesses. It's
    //easier to have an array of GPIO modules with identical registers,
    //including arrays for multi-register groups like GPyCSEL1-4. But
    //the header file doesn't define anything we can turn into an array,
    //so manual pointer arithmetic is used instead.
    mux = gpioBaseAddr + (0x6/2) + pin32/16;
    gmux = gpioBaseAddr + (0x20/2) + pin32/16;
    csel = gpioBaseAddr + (0x28/2) + pin32/8;

    //Now for the actual function
    __asm(" EALLOW");

    //To change the muxing, set the peripheral mux to 0/GPIO first to avoid
    //glitches, then change the group mux, then set the peripheral mux to
    //its target value. Finally, set the CPU select. This procedure is
    //described in the TRM. Unfortunately, since we don't know the pin in
    //advance we can't hardcode a bitfield reference, so there's some tricky
    //bit twiddling here.
    *mux &= ~(0x3UL << (2*pin16));
    *gmux &= ~(0x3UL << (2*pin16));
    *gmux |= (Uint32)((peripheral >> 2) & 0x3UL) << (2*pin16);
    *mux |= (Uint32)(peripheral & 0x3UL) << (2*pin16);

    *csel &= ~(0x3L << (4*pin8));
    *csel |= (Uint32)(cpu & 0x3L) << (4*pin8);

    //WARNING: This code does not touch the analog mode select registers,
    //which are needed to give the USB module control of its IOs.

    __asm(" EDIS");
}

void	Class_GPIODrv::Drv_GPIO_SetupPinValue(Uint16 pin, Uint16 pinvalue)
{
    volatile Uint32 *gpioBaseAddr;
    volatile Uint32 *value;
    Uint32 pin32, pinMask;

    pin32 = pin % 32;

    pinMask = 1UL << pin32;
    gpioBaseAddr = (Uint32 *)&GpioDataRegs + (pin/32)*(0x8/2);

    //Create pointers to the appropriate registers. This is a workaround
    //for the way GPIO registers are defined. The standard definition
    //in the header file makes it very easy to do named accesses of one
    //register or bit, but hard to do arbitrary numerical accesses. It's
    //easier to have an array of GPIO modules with identical registers,
    //including arrays for multi-register groups like GPyQSEL1-2. But
    //the header file doesn't define anything we can turn into an array,
    //so manual pointer arithmetic is used instead.
    value = gpioBaseAddr + (0x0/2);


    __asm(" EALLOW");

    //Set the data value
    *value &= ~pinMask;
    if (pinvalue == 1)
    {
        *value |= pinMask;
    } 
	else
    {
        *value &= ~pinMask;
    }

    __asm(" EDIS");


}



void Class_GPIODrv::Drv_GPIO_SetupPinDirection(Uint16 pin, Uint16 output)
{
    volatile Uint32 *gpioBaseAddr;
    volatile Uint32 *dir;
    Uint32 pin32,pinMask;

    pin32 = pin % 32;
   // pin16 = pin % 16;
    pinMask = 1UL << pin32;
    gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (pin/32)*(0x40/2);

    //Create pointers to the appropriate registers. This is a workaround
    //for the way GPIO registers are defined. The standard definition
    //in the header file makes it very easy to do named accesses of one
    //register or bit, but hard to do arbitrary numerical accesses. It's
    //easier to have an array of GPIO modules with identical registers,
    //including arrays for multi-register groups like GPyQSEL1-2. But
    //the header file doesn't define anything we can turn into an array,
    //so manual pointer arithmetic is used instead.
    dir = gpioBaseAddr + (0xA/2);


    __asm(" EALLOW");

    //Set the data direction
    *dir &= ~pinMask;
    if (output == 1)
    {
        //Output
        *dir |= pinMask;
    } 
	else
    {
        //Input
        *dir &= ~pinMask;
    }

    __asm(" EDIS");
}





void Class_GPIODrv::Drv_GPIO_SetupPinOptions(Uint16 pin, Uint16 output, Uint16 flags)
{
    volatile Uint32 *gpioBaseAddr;
    volatile Uint32 *dir, *pud, *inv, *odr, *qsel;
    Uint32 pin32, pin16, pinMask, qual;

    pin32 = pin % 32;
    pin16 = pin % 16;
    pinMask = 1UL << pin32;
    gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (pin/32)*(0x40/2);

    //Create pointers to the appropriate registers. This is a workaround
    //for the way GPIO registers are defined. The standard definition
    //in the header file makes it very easy to do named accesses of one
    //register or bit, but hard to do arbitrary numerical accesses. It's
    //easier to have an array of GPIO modules with identical registers,
    //including arrays for multi-register groups like GPyQSEL1-2. But
    //the header file doesn't define anything we can turn into an array,
    //so manual pointer arithmetic is used instead.
    dir = gpioBaseAddr + (0xA/2);
    pud = gpioBaseAddr + (0xC/2);
    inv = gpioBaseAddr + (0x10/2);
    odr = gpioBaseAddr + (0x12/2);
    qsel = gpioBaseAddr + (0x2/2) + pin32/16;

    __asm(" EALLOW");

    //Set the data direction
    *dir &= ~pinMask;
    if (output == 1)
    {
        //Output, with optional open drain mode and pull-up
        *dir |= pinMask;

        //Enable open drain if necessary
        if (flags & (1 << 2))
            *odr |= pinMask;
        else
            *odr &= ~pinMask;

        //Enable pull-up if necessary. Open drain mode must be active.
        if (flags & ((1 << 2) | (1 << 0)))
            *pud &= ~pinMask;
        else
            *pud |= pinMask;
    } else
    {
        //Input, with optional pull-up, qualification, and polarity inversion
        *dir &= ~pinMask;

        //Enable pull-up if necessary
        if (flags & (1 << 0))
            *pud &= ~pinMask;
        else
            *pud |= pinMask;

        //Invert polarity if necessary
        if (flags & (1 << 1))
            *inv |= pinMask;
        else
            *inv &= ~pinMask;
    }

    //Extract the qualification parameter and load it into the register. This is
    //also needed for open drain outputs, so we might as well do it all the time.
    qual = (flags & (0x3 << 4)) / (0x1 << 4);
    *qsel &= ~(0x3L << (2 * pin16));
    if (qual != 0x0)
        *qsel |= qual << (2 * pin16);

    __asm(" EDIS");
}

void Class_GPIODrv::Drv_GPIO_EnableUnbondedIOPullups(void)
{
    unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; //bits 8-10 have pin count*/
/*
 * 5 = 100 pin
 * 6 = 176 pin
 * 7 = 337 pin
 */

    if(pin_count == 5)
    {
        __asm(" EALLOW");
        GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3;  //GPIOs 0-1, 5-9, 22-31
        GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF;  //GPIOs 32-40, 44-57
        GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18;  //GPIOs 67-68, 74-77, 79-83, 93-95
        GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7;  //GPIOs 96-127
        GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF;  //GPIOs 128-159
        GpioCtrlRegs.GPFPUD.all = ~0x000001FF;  //GPIOs 160-168
        __asm(" EDIS");
    }
    else if (pin_count == 6)
    {
		__asm(" EALLOW");
		GpioCtrlRegs.GPCPUD.all = ~0x80000000;	//GPIO 95
		GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7;	//GPIOs 96-127
		GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF;	//GPIOs 128-159 except for 133
		GpioCtrlRegs.GPFPUD.all = ~0x000001FF;	//GPIOs 160-168
		__asm(" EDIS");

    }
    else
    {
        //do nothing - this is 337 pin package
    }

}

// 向FPGA发送RESET信号
inline  void    Class_GPIODrv::Drv_GPIO_FPGAReset(void)
{
    GpioDataRegs.GPBCLEAR.bit.GPIO53 = 1;
}


//清除FPGARESET信号
inline  void    Class_GPIODrv::Drv_GPIO_FPGAResetClear(void)
{
    GpioDataRegs.GPBSET.bit.GPIO53 = 1;
}

void Class_GPIODrv::InitECap1Gpio(Uint16 pin)
{
	__asm(" EALLOW");
	InputXbarRegs.INPUT7SELECT = pin; 		// Set eCAP1 source to GPIO-66
	__asm(" EDIS");
}

void Class_GPIODrv::InitECap2Gpio(Uint16 pin)
{
	__asm(" EALLOW");
	InputXbarRegs.INPUT8SELECT = pin; 		// Set eCAP2 source to GPIO-67
	__asm(" EDIS");
}

void Class_GPIODrv::InitECap3Gpio(Uint16 pin)
{
	__asm(" EALLOW");
	InputXbarRegs.INPUT9SELECT = pin; 		// Set eCAP3 source to GPIO-26
	__asm(" EDIS");
}

void Class_GPIODrv::InitECap4Gpio(Uint16 pin)
{
	__asm(" EALLOW");
	InputXbarRegs.INPUT10SELECT = pin; 		// Set eCAP4 source to GPIO-27
	__asm(" EDIS");
}



//============================================================
// End of file.
//============================================================

//	EPwm1Regs.ETSEL.bit.SOCASEL = 0;
//	EPwm1Regs.ETSEL.bit.SOCAEN = 1;


//初始化EPWM
void	Class_PWMDrv::Drv_InitPWM(void)										
{
    __asm(" EALLOW");
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    __asm(" EDIS");

    EPwm1Regs.TBPRD = 3000;                       // Set timer period   中断10K
    // Setup TBCLK
    EPwm1Regs.TBCTL.bit.CTRMODE = 0x2; // Count up
    EPwm1Regs.TBCTL.bit.PHSEN = 0x0;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.PRDLD = 0x0;
    EPwm1Regs.TBCTL2.bit.PRDLDSYNC = 0;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = 0x1;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;   // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x2;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x2;

    // Setup compare
    EPwm1Regs.CMPA.bit.CMPA = 3000;

    // Set actions
    EPwm1Regs.AQCTLA.bit.CAU = 0x1;            // Set PWM1A on Zero
    EPwm1Regs.AQCTLA.bit.CAD = 0x2;

    EPwm1Regs.AQCTLB.bit.CAU = 0x1;         // Set PWM1A on Zero
    EPwm1Regs.AQCTLB.bit.CAD = 0x2;

    // Active Low PWMs - Setup Deadband
    EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3;
    EPwm1Regs.DBCTL.bit.POLSEL = 0x3;
    EPwm1Regs.DBCTL.bit.IN_MODE = 0x0;
    EPwm1Regs.DBRED.bit.DBRED = 0;
    EPwm1Regs.DBFED.bit.DBFED = 0;


    // Interrupt where we will change the Deadband
    EPwm1Regs.ETSEL.bit.INTSEL = 0x1;    // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 1;               // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = 0x1;          // Generate INT on 1st event

    EPwm1Regs.TBPHS.bit.TBPHS = 0;                                 // Set Phase register to zero

    EPwm1Regs.TBCTR = 0;                                            // clear TB counter

    __asm(" EALLOW");
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    __asm(" EDIS");

}

//============================================================
// End of file.
//============================================================




interrupt void EPWM1_PERIOD_INT_ISR(void);
interrupt void c_int5(void);


interrupt void PIE_RESERVED(void)
 {


    __asm(" EALLOW");
    WdRegs.WDCR.all = 0x0028;
    __asm(" EDIS");

    while(1)
    {
        ;//wait for watchdog reset
    }
}


void	Class_SysDrv::Drv_SysCtrlInit(void)
{
		// Disable the watchdog
	   objWatchDogDrv.Drv_DisableDog();
	
	
	// Copy time critical code and Flash setup code to RAM
	// This includes the following functions:  InitFlash();
	// The	RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
	// symbols are created by the linker. Refer to the device .cmd file.
		objRAMDrv.Drv_MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
	//    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
	// Call Flash Initialization to setup flash waitstates
	// This function must reside in RAM
		//objFlashDrv.Drv_InitFlash();
	
	
		// *IMPORTANT*
		// The Device_cal function, which copies the ADC & oscillator calibration values
		// from TI reserved OTP into the appropriate trim registers, occurs automatically
		// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
		// following function MUST be called for the ADC and oscillators to function according
		// to specification. The clocks to the ADC MUST be enabled before calling this
		// function.
		// See the device data manual and/or the ADC Reference
		// Manual for more information.
	
		__asm(" EALLOW");
	
		//enable pull-ups on unbonded IOs as soon as possible to reduce power consumption.
		objGPIODrv.Drv_GPIO_EnableUnbondedIOPullups();
	
		CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
		CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
		CpuSysRegs.PCLKCR13.bit.ADC_D = 1;
	
		//check if device is trimmed
		/*if(*((Uint16 *)0x5D1B6) == 0x0000){
			//device is not trimmed, apply static calibration values
			AnalogSubsysRegs.ANAREFTRIMA.all = 31709;
			AnalogSubsysRegs.ANAREFTRIMB.all = 31709;
			AnalogSubsysRegs.ANAREFTRIMD.all = 31709;
		}*/
	
		CpuSysRegs.PCLKCR13.bit.ADC_A = 0;
		CpuSysRegs.PCLKCR13.bit.ADC_B = 0;
		CpuSysRegs.PCLKCR13.bit.ADC_D = 0;
		__asm(" EDIS");
	
		// Initialize the PLL control: PLLCR and CLKINDIV
		// F28_PLLCR and F28_CLKINDIV are defined in F2807x_Examples.h
		// Note: The internal oscillator CANNOT be used as the PLL source if the
		// PLLSYSCLK is configured to frequencies above 194 MHz.
		objSysDrv.Drv_InitSysPll(1,12,0,1);    // 120M  for 20M OSC
	
		//Turn on all peripherals
		objSysDrv.Drv_InitPeripheralClocks();

}

void	Class_SysDrv::Drv_InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel)
{
    if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)    &&
      (imult         == ClkCfgRegs.SYSPLLMULT.bit.IMULT)           &&
      (fmult         == ClkCfgRegs.SYSPLLMULT.bit.FMULT)           &&
      (divsel        == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
    {
        //everything is set as required, so just return
        return;
    }

    if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)
    {
        switch (clock_source)
        {
            case 2:
                Drv_SysIntOsc1Sel();
                break;

            case 0:
                Drv_SysIntOsc2Sel();
                break;

            case 1:
               	Drv_SysXtalOscSel();
                break;
        }
    }

    __asm(" EALLOW");
     // first modify the PLL multipliers
    if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT)
    {
        // Bypass PLL and set dividers to /1
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;

        // Program PLL multipliers
        Uint32 temp_syspllmult = ClkCfgRegs.SYSPLLMULT.all;
        ClkCfgRegs.SYSPLLMULT.all = ((temp_syspllmult & ~(0x37FU)) | 
                                     ((fmult << 8U) | imult));
                                     
        ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1;            // Enable SYSPLL

        // Wait for the SYSPLL lock
        while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
        {
            // Uncomment to service the watchdog
            // ServiceDog();
        }

        // Write a multiplier again to ensure proper PLL initialization
        // This will force the PLL to lock a second time
        ClkCfgRegs.SYSPLLMULT.bit.IMULT = imult;        // Setting integer multiplier

        // Wait for the SYSPLL re-lock
        while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
        {
            // Uncomment to service the watchdog
            // ServiceDog();
        }
    }

    // Set divider to produce slower output frequency to limit current increase
    if(divsel != 63)
    {
         ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1;
    }else
    {
         ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
    }

    // Enable PLLSYSCLK is fed from system PLL clock
    ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;

    // Small 100 cycle delay
    asm(" RPT #100 || NOP");

    // Set the divider to user value
    ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;


    __asm(" EDIS");
}


// This function switches to Internal Oscillator 1 and turns off all other clock
// sources to minimize power consumption

void Class_SysDrv::Drv_SysIntOsc1Sel (void) {
    __asm(" EALLOW");
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1
    __asm(" EDIS");
}


// This function switches to Internal oscillator 2 from External Oscillator
// and turns off all other clock sources to minimize power consumption
// NOTE: If there is no external clock connection, when switching from
//       INTOSC1 to INTOSC2, EXTOSC and XLCKIN must be turned OFF prior
//       to switching to internal oscillator 1

void Class_SysDrv::Drv_SysIntOsc2Sel (void) {

    __asm(" EALLOW");
    ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0;     // Turn on INTOSC2
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2
    __asm(" EDIS");

}


// This function switches to External CRYSTAL oscillator and turns off all other clock
// sources to minimize power consumption. This option may not be available on all
// device packages

void Class_SysDrv::Drv_SysXtalOscSel (void)  {

    __asm(" EALLOW");
    ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0;        // Turn on XTALOSC
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL
    __asm(" EDIS");

}



//This function initializes the clocks to the peripheral modules.
void	Class_SysDrv::Drv_InitPeripheralClocks(void)		
{
	__asm(" EALLOW");

	//EPWM时钟divider配置
	ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; // PLLSYSCLK/2= 60M

	//低速时钟配置
      //ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0x2;  // 010 on reset
      ClkCfgRegs.LOSPCP.all = 2;//LSPCLKDIV;  // SYSCLKOUT/1 (120M)
      
	CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
	CpuSysRegs.PCLKCR0.bit.DMA = 0;
	CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
	CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 0;
	CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 0;
	CpuSysRegs.PCLKCR0.bit.HRPWM = 0;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

	CpuSysRegs.PCLKCR1.bit.EMIF1 = 0;
	CpuSysRegs.PCLKCR1.bit.EMIF2 = 0;

	CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
	CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
	CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
	CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
	CpuSysRegs.PCLKCR2.bit.EPWM5 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
	CpuSysRegs.PCLKCR2.bit.EPWM7 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM8 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM9 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM10 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM11 = 0;
	CpuSysRegs.PCLKCR2.bit.EPWM12 = 0;

	CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
	CpuSysRegs.PCLKCR3.bit.ECAP2 = 1;
	CpuSysRegs.PCLKCR3.bit.ECAP3 = 1;
	CpuSysRegs.PCLKCR3.bit.ECAP4 = 1;
	CpuSysRegs.PCLKCR3.bit.ECAP5 = 0;
	CpuSysRegs.PCLKCR3.bit.ECAP6 = 0;

	CpuSysRegs.PCLKCR4.bit.EQEP1 = 0;
	CpuSysRegs.PCLKCR4.bit.EQEP2 = 0;
	CpuSysRegs.PCLKCR4.bit.EQEP3 = 0;

	CpuSysRegs.PCLKCR6.bit.SD1 = 0;
	CpuSysRegs.PCLKCR6.bit.SD2 = 0;

	CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
	CpuSysRegs.PCLKCR7.bit.SCI_B = 1;
	CpuSysRegs.PCLKCR7.bit.SCI_C = 0;
	CpuSysRegs.PCLKCR7.bit.SCI_D = 0;

	CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
	CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
	CpuSysRegs.PCLKCR8.bit.SPI_C = 0;

	CpuSysRegs.PCLKCR9.bit.I2C_A = 0;
	CpuSysRegs.PCLKCR9.bit.I2C_B = 0;

	CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
	CpuSysRegs.PCLKCR10.bit.CAN_B = 1;

	CpuSysRegs.PCLKCR11.bit.McBSP_A = 0;
	CpuSysRegs.PCLKCR11.bit.McBSP_B = 0;
	CpuSysRegs.PCLKCR11.bit.USB_A = 0;

	CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
	CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
	CpuSysRegs.PCLKCR13.bit.ADC_D = 1;

	CpuSysRegs.PCLKCR14.bit.CMPSS1 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS2 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS3 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS4 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS5 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS6 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS7 = 0;
	CpuSysRegs.PCLKCR14.bit.CMPSS8 = 0;

	CpuSysRegs.PCLKCR16.bit.DAC_A = 1;
	CpuSysRegs.PCLKCR16.bit.DAC_B = 1;
	CpuSysRegs.PCLKCR16.bit.DAC_C = 1;
	
	__asm(" EDIS");
}



//This function initializes the PIE control registers to a known state.
void	Class_SysDrv::Drv_InitPieCtrl(void)		
{
    // Disable Interrupts at the CPU level:
    __asm(" setc INTM");

    // Disable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;

	// Clear all PIEIER registers:
	PieCtrlRegs.PIEIER1.all = 0;
	PieCtrlRegs.PIEIER2.all = 0;
       PieCtrlRegs.PIEIER3.bit.INTx1 = 1;       // Enable EPWM1 Interrupt
	PieCtrlRegs.PIEIER4.all = 0;
	PieCtrlRegs.PIEIER5.all = 0;
	PieCtrlRegs.PIEIER6.all = 0;
	PieCtrlRegs.PIEIER7.all = 0;
	PieCtrlRegs.PIEIER8.all = 0;
//  PieCtrlRegs.PIEIER9.all = 3;            // Enable SCI-A TXD&RXD Interrupt
    PieCtrlRegs.PIEIER9.bit.INTx5 = 1;          // Enable eCAN A0
	PieCtrlRegs.PIEIER10.all = 0;
	PieCtrlRegs.PIEIER11.all = 0;
	PieCtrlRegs.PIEIER12.all = 0;

	// Clear all PIEIFR registers:
	PieCtrlRegs.PIEIFR1.all = 0;
	PieCtrlRegs.PIEIFR2.all = 0;
	PieCtrlRegs.PIEIFR3.all = 0;	
	PieCtrlRegs.PIEIFR4.all = 0;
	PieCtrlRegs.PIEIFR5.all = 0;
	PieCtrlRegs.PIEIFR6.all = 0;
	PieCtrlRegs.PIEIFR7.all = 0;
	PieCtrlRegs.PIEIFR8.all = 0;
    PieCtrlRegs.PIEIFR9.all = 0;
	PieCtrlRegs.PIEIFR10.all = 0;
	PieCtrlRegs.PIEIFR11.all = 0;
	PieCtrlRegs.PIEIFR12.all = 0;

}

const struct PIE_VECT_TABLE PieVectTableInit = {
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // Reserved 
    (PINT)TIMER1_ISR,                                       // CPU Timer 1 Interrupt 
    (PINT)TIMER2_ISR,                                       // CPU Timer 2 Interrupt 
    (PINT)DATALOG_ISR,                                      // Datalogging Interrupt 
    (PINT)RTOS_ISR,                                         // RTOS Interrupt 
    (PINT)EMU_ISR,                                          // Emulation Interrupt 
    (PINT)NMI_ISR,                                          // Non-Maskable Interrupt 
    (PINT)ILLEGAL_ISR,                                      // Illegal Operation Trap 
    (PINT)USER1_ISR,                                        // User Defined Trap 1 
    (PINT)USER2_ISR,                                        // User Defined Trap 2 
    (PINT)USER3_ISR,                                        // User Defined Trap 3 
    (PINT)USER4_ISR,                                        // User Defined Trap 4 
    (PINT)USER5_ISR,                                        // User Defined Trap 5 
    (PINT)USER6_ISR,                                        // User Defined Trap 6 
    (PINT)USER7_ISR,                                        // User Defined Trap 7 
    (PINT)USER8_ISR,                                        // User Defined Trap 8 
    (PINT)USER9_ISR,                                        // User Defined Trap 9 
    (PINT)USER10_ISR,                                       // User Defined Trap 10 
    (PINT)USER11_ISR,                                       // User Defined Trap 11 
    (PINT)USER12_ISR,                                       // User Defined Trap 12 
    (PINT)ADCA1_ISR,                                        // 1.1 - ADCA Interrupt 1 
    (PINT)ADCB1_ISR,                                        // 1.2 - ADCB Interrupt 1 
    (PINT)PIE_RESERVED_ISR,                                 // 1.3 - Reserved 
    (PINT)XINT1_ISR,                                        // 1.4 - XINT1 Interrupt 
    (PINT)XINT2_ISR,                                        // 1.5 - XINT2 Interrupt 
    (PINT)ADCD1_ISR,                                        // 1.6 - ADCD Interrupt 1 
    (PINT)TIMER0_ISR,                                       // 1.7 - Timer 0 Interrupt 
    (PINT)WAKE_ISR,                                         // 1.8 - Standby and Halt Wakeup Interrupt 
    (PINT)EPWM1_TZ_ISR,                                     // 2.1 - ePWM1 Trip Zone Interrupt 
    (PINT)EPWM2_TZ_ISR,                                     // 2.2 - ePWM2 Trip Zone Interrupt 
    (PINT)EPWM3_TZ_ISR,                                     // 2.3 - ePWM3 Trip Zone Interrupt 
    (PINT)EPWM4_TZ_ISR,                                     // 2.4 - ePWM4 Trip Zone Interrupt 
    (PINT)EPWM5_TZ_ISR,                                     // 2.5 - ePWM5 Trip Zone Interrupt 
    (PINT)EPWM6_TZ_ISR,                                     // 2.6 - ePWM6 Trip Zone Interrupt 
    (PINT)EPWM7_TZ_ISR,                                     // 2.7 - ePWM7 Trip Zone Interrupt 
    (PINT)EPWM8_TZ_ISR,                                     // 2.8 - ePWM8 Trip Zone Interrupt 
    (PINT)EPWM_INT_ISR,                                      // 3.1 - ePWM1 Interrupt 
    //(PINT)EPWM1_ISR,                                        // 3.1 - ePWM1 Interrupt 
    (PINT)EPWM2_ISR,                                        // 3.2 - ePWM2 Interrupt 
    (PINT)EPWM3_ISR,                                        // 3.3 - ePWM3 Interrupt 
    (PINT)EPWM4_ISR,                                        // 3.4 - ePWM4 Interrupt 
    (PINT)EPWM5_ISR,                                        // 3.5 - ePWM5 Interrupt 
    (PINT)EPWM6_ISR,                                        // 3.6 - ePWM6 Interrupt 
    (PINT)EPWM7_ISR,                                        // 3.7 - ePWM7 Interrupt 
    (PINT)EPWM8_ISR,                                        // 3.8 - ePWM8 Interrupt 
    (PINT)ECAP1_ISR,                                        // 4.1 - eCAP1 Interrupt 
    (PINT)ECAP2_ISR,                                        // 4.2 - eCAP2 Interrupt 
    (PINT)ECAP3_ISR,                                        // 4.3 - eCAP3 Interrupt 
    (PINT)ECAP4_ISR,                                        // 4.4 - eCAP4 Interrupt 
    (PINT)ECAP5_ISR,                                        // 4.5 - eCAP5 Interrupt 
    (PINT)ECAP6_ISR,                                        // 4.6 - eCAP6 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 4.7 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.8 - Reserved 
    (PINT)EQEP1_ISR,                                        // 5.1 - eQEP1 Interrupt 
    (PINT)EQEP2_ISR,                                        // 5.2 - eQEP2 Interrupt 
    (PINT)EQEP3_ISR,                                        // 5.3 - eQEP3 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 5.4 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.5 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.6 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.7 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.8 - Reserved 
   (PINT)SPIA_RX_ISR,                                      // 6.1 - SPIA Receive Interrupt 
    (PINT)SPIA_TX_ISR,                                      // 6.2 - SPIA Transmit Interrupt 
    (PINT)SPIB_RX_ISR,                                      // 6.3 - SPIB Receive Interrupt 
    (PINT)SPIB_TX_ISR,                                      // 6.4 - SPIB Transmit Interrupt 
    (PINT)MCBSPA_RX_ISR,                                    // 6.5 - McBSPA Receive Interrupt 
    (PINT)MCBSPA_TX_ISR,                                    // 6.6 - McBSPA Transmit Interrupt 
    (PINT)MCBSPB_RX_ISR,                                    // 6.7 - McBSPB Receive Interrupt 
    (PINT)MCBSPB_TX_ISR,                                    // 6.8 - McBSPB Transmit Interrupt 
    (PINT)DMA_CH1_ISR,                                      // 7.1 - DMA Channel 1 Interrupt 
    (PINT)DMA_CH2_ISR,                                      // 7.2 - DMA Channel 2 Interrupt 
    (PINT)DMA_CH3_ISR,                                      // 7.3 - DMA Channel 3 Interrupt 
    (PINT)DMA_CH4_ISR,                                      // 7.4 - DMA Channel 4 Interrupt 
    (PINT)DMA_CH5_ISR,                                      // 7.5 - DMA Channel 5 Interrupt 
    (PINT)DMA_CH6_ISR,                                      // 7.6 - DMA Channel 6 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 7.7 - Reserved 
   (PINT)PIE_RESERVED_ISR,                                 // 7.8 - Reserved 
    (PINT)I2CA_ISR,                                         // 8.1 - I2CA Interrupt 1 
    (PINT)I2CA_FIFO_ISR,                                    // 8.2 - I2CA Interrupt 2 
    (PINT)I2CB_ISR,                                         // 8.3 - I2CB Interrupt 1 
    (PINT)I2CB_FIFO_ISR,                                    // 8.4 - I2CB Interrupt 2 
    (PINT)SCIC_RX_ISR,                                      // 8.5 - SCIC Receive Interrupt 
    (PINT)SCIC_TX_ISR,                                      // 8.6 - SCIC Transmit Interrupt 
    (PINT)SCID_RX_ISR,                                      // 8.7 - SCID Receive Interrupt 
    (PINT)SCID_TX_ISR,                                      // 8.8 - SCID Transmit Interrupt 
    (PINT)SCIA_RX_ISR,                                      // 9.1 - SCIA Receive Interrupt 
    (PINT)SCIA_TX_ISR,                                      // 9.2 - SCIA Transmit Interrupt 
    (PINT)SCIB_RX_ISR,                                      // 9.3 - SCIB Receive Interrupt 
    (PINT)SCIB_TX_ISR,                                      // 9.4 - SCIB Transmit Interrupt 
    //(PINT)ECAN0INTA_ISR,                                        // 9.5 - CANA Interrupt 0
    (PINT)CANA1_ISR,                                        // 9.6 - CANA Interrupt 1
    (PINT)CANB0_ISR,                                        // 9.7 - CANB Interrupt 0
    (PINT)CANB1_ISR,                                        // 9.8 - CANB Interrupt 1
    (PINT)ADCA_EVT_ISR,                                     // 10.1 - ADCA Event Interrupt 
    (PINT)ADCA2_ISR,                                        // 10.2 - ADCA Interrupt 2 
    (PINT)ADCA3_ISR,                                        // 10.3 - ADCA Interrupt 3 
    (PINT)ADCA4_ISR,                                        // 10.4 - ADCA Interrupt 4 
    (PINT)ADCB_EVT_ISR,                                     // 10.5 - ADCB Event Interrupt 
    (PINT)ADCB2_ISR,                                        // 10.6 - ADCB Interrupt 2 
    (PINT)ADCB3_ISR,                                        // 10.7 - ADCB Interrupt 3 
    (PINT)ADCB4_ISR,                                        // 10.8 - ADCB Interrupt 4 
    (PINT)CLA1_1_ISR,                                       // 11.1 - CLA1 Interrupt 1 
    (PINT)CLA1_2_ISR,                                       // 11.2 - CLA1 Interrupt 2 
    (PINT)CLA1_3_ISR,                                       // 11.3 - CLA1 Interrupt 3 
    (PINT)CLA1_4_ISR,                                       // 11.4 - CLA1 Interrupt 4 
    (PINT)CLA1_5_ISR,                                       // 11.5 - CLA1 Interrupt 5 
    (PINT)CLA1_6_ISR,                                       // 11.6 - CLA1 Interrupt 6 
    (PINT)CLA1_7_ISR,                                       // 11.7 - CLA1 Interrupt 7 
    (PINT)CLA1_8_ISR,                                       // 11.8 - CLA1 Interrupt 8 
    (PINT)XINT3_ISR,                                        // 12.1 - XINT3 Interrupt 
    (PINT)XINT4_ISR,                                        // 12.2 - XINT4 Interrupt 
    (PINT)XINT5_ISR,                                        // 12.3 - XINT5 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 12.4 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 12.5 - Reserved 
    (PINT)VCU_ISR,                                          // 12.6 - VCU Interrupt 
    (PINT)FPU_OVERFLOW_ISR,                                 // 12.7 - FPU Overflow Interrupt 
    (PINT)FPU_UNDERFLOW_ISR,                                // 12.8 - FPU Underflow Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 1.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 1.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 1.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 1.12 - Reserved 
    (PINT)IPC0_ISR,                                         // 1.13 - IPC Interrupt 0 
    (PINT)IPC1_ISR,                                         // 1.14 - IPC Interrupt 1 
    (PINT)IPC2_ISR,                                         // 1.15 - IPC Interrupt 2 
    (PINT)IPC3_ISR,                                         // 1.16 - IPC Interrupt 3 
    (PINT)EPWM9_TZ_ISR,                                     // 2.9 - ePWM9 Trip Zone Interrupt 
    (PINT)EPWM10_TZ_ISR,                                    // 2.10 - ePWM10 Trip Zone Interrupt 
    (PINT)EPWM11_TZ_ISR,                                    // 2.11 - ePWM11 Trip Zone Interrupt 
    (PINT)EPWM12_TZ_ISR,                                    // 2.12 - ePWM12 Trip Zone Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 2.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 2.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 2.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 2.16 - Reserved 
    (PINT)EPWM9_ISR,                                        // 3.9 - ePWM9 Interrupt 
    (PINT)EPWM10_ISR,                                       // 3.10 - ePWM10 Interrupt 
    (PINT)EPWM11_ISR,                                       // 3.11 - ePWM11 Interrupt 
    (PINT)EPWM12_ISR,                                       // 3.12 - ePWM12 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 3.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 3.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 3.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 3.16 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 4.16 - Reserved 
    (PINT)SD1_ISR,                                          // 5.9 - SD1 Interrupt 
    (PINT)SD2_ISR,                                          // 5.10 - SD2 Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 5.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 5.16 - Reserved 
    (PINT)SPIC_RX_ISR,                                      // 6.9 - SPIC Receive Interrupt 
    (PINT)SPIC_TX_ISR,                                      // 6.10 - SPIC Transmit Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 6.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 6.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 6.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 6.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 6.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 6.16 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 7.16 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 8.16 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 9.14 - Reserved 
    (PINT)USBA_ISR,                                         // 9.15 - USBA Interrupt 
    (PINT)PIE_RESERVED_ISR,                                 // 9.16 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 10.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 10.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 10.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 10.12 - Reserved 
    (PINT)ADCD_EVT_ISR,                                     // 10.13 - ADCD Event Interrupt 
    (PINT)ADCD2_ISR,                                        // 10.14 - ADCD Interrupt 2 
    (PINT)ADCD3_ISR,                                        // 10.15 - ADCD Interrupt 3 
    (PINT)ADCD4_ISR,                                        // 10.16 - ADCD Interrupt 4 
    (PINT)PIE_RESERVED_ISR,                                 // 11.9 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.10 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.11 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.12 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.13 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.14 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.15 - Reserved 
    (PINT)PIE_RESERVED_ISR,                                 // 11.16 - Reserved 
    (PINT)EMIF_ERROR_ISR,                                   // 12.9 - EMIF Error Interrupt 
    (PINT)RAM_CORRECTABLE_ERROR_ISR,                        // 12.10 - RAM Correctable Error Interrupt 
    (PINT)FLASH_CORRECTABLE_ERROR_ISR,                      // 12.11 - Flash Correctable Error Interrupt 
    (PINT)RAM_ACCESS_VIOLATION_ISR,                         // 12.12 - RAM Access Violation Interrupt 
    (PINT)SYS_PLL_SLIP_ISR,                                 // 12.13 - System PLL Slip Interrupt 
    (PINT)AUX_PLL_SLIP_ISR,                                 // 12.14 - Auxiliary PLL Slip Interrupt 
    (PINT)CLA_OVERFLOW_ISR,                                 // 12.15 - CLA Overflow Interrupt 
    (PINT)CLA_UNDERFLOW_ISR                                 // 12.16 - CLA Underflow Interrupt 
};

//This function initializes the PIE vector table to a known state.This function must be executed after boot time.
void	Class_SysDrv::Drv_InitPieVectTable(void)
{
	Uint16	i;	
	Uint32	*Source  =	(Uint32  *)  &PieVectTableInit;
	Uint32	*Dest  =  (Uint32  *)  &PieVectTable;

// Do not write over first 3 32-bit locations (these locations are
// initialized by Boot ROM with boot variables)

	Source	=  Source  +  3;  
	Dest  =  Dest  +  3;  

	__asm(" EALLOW");  
	for(i  =  0;  i  <	221;  i++)	
	{  
	*Dest++  =	*Source++;	
	}  
	__asm(" EDIS");  

// Enable the PIE Vector Table
	PieCtrlRegs.PIECTRL.bit.ENPIE  =  1;
}



	
		
void	Class_SysDrv::Drv_InitPIE(void)
{
		__asm(" setc INTM");
	
	// Initialize the PIE control registers to their default state.
	// The default state is all PIE interrupts disabled and flags
	// are cleared.
		objSysDrv.Drv_InitPieCtrl();
	
		// Disable CPU interrupts and clear all CPU interrupt flags:
		IER = 0x0000;
		IFR = 0x0000;
	
		// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
		// This will populate the entire table, even if the interrupt
		objSysDrv.Drv_InitPieVectTable();
	

}


//This function enable the PIE module and CPU interrupts
void	Class_SysDrv::Drv_InitInterrupts(void)					
{
		//EALLOW;

		//PieVectTable.EPWM1_INT = &EPWM_INT_ISR;
		//PieVectTable.CANA0_INT = &ECAN0INTA_ISR;
		//PieVectTable.ILLEGAL_INT = &ILLEGAL_ISR;

		
		__asm(" EDIS");
	
		// Enable the PWM interrupt on the processor (PIE).
		PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
  		//PieCtrlRegs.PIEIER9.bit.INTx5 = 1;          // Enable eCAN A0		
		IER |= (0x0004); // Enable CPU INT3 INT9 and clear all CPU interrupt flags:

}


//============================================================
// End of file.
//============================================================



// This function resets the watchdog timer.
void Class_WatchDogDrv::Drv_KickDog(void)
{
    __asm(" EALLOW");
    WdRegs.WDKEY.bit.WDKEY = 0x0055;
    WdRegs.WDKEY.bit.WDKEY = 0x00AA;
    __asm(" EDIS");
}


// This function disables the watchdog timer.
void Class_WatchDogDrv::Drv_DisableDog(void)
{
	volatile Uint16 tmp;
    __asm(" EALLOW");
    //Grab the clock config so we don't clobber it
    tmp = WdRegs.WDCR.all & 0x0007;
    WdRegs.WDCR.all = 0x0068 | tmp;
    __asm(" EDIS");

}

// This function enables the watchdog timer.
void Class_WatchDogDrv::Drv_EnableDog(void)
{
// Enable the watchdog
	__asm(" EALLOW");
	WdRegs.WDCR.all = 0x0028;
	__asm(" EDIS");

}


//============================================================
// End of file.
//============================================================



void	Class_RAMDrv::Drv_RamCheck(void)
{
	volatile unsigned int *addr;
	unsigned int u16_i;


									//memery check L0&L1&L2&L3[0x08000,0x0BFFB]
	addr = (unsigned int *) 0x08000;
	for (u16_i = 0x0000; u16_i < 0x3FFC; u16_i++)
	{
		*(addr + u16_i) = 0x5555;
		if (*(addr + u16_i) != 0x5555)
		{
			m_u16_RamCheckErr = 1;
		}
		*(addr + u16_i) = 0xaaaa;
		if (*(addr + u16_i) != 0xaaaa)
		{
			m_u16_RamCheckErr = 1;
		}
		*(addr + u16_i) = 0x0000;
	}

        addr = (unsigned int *) 0xBFFC;
        for (u16_i = 0x0000; u16_i < 0x4; u16_i++)
        {
            *(addr + u16_i) = 0x5555;

            if (*(addr + u16_i) != 0x5555)
            {
                m_u16_RamCheckErr=1;
            }

            *(addr + u16_i) = 0xaaaa;

            if (*(addr + u16_i) != 0xaaaa)
            {
                m_u16_RamCheckErr=1;
            }

            *(addr + u16_i) = 0x0000;
        }

										//memery check L4&L5&L6&L7[0xC000,0x10000]
	addr = (Uint16 *) 0xC000;
	for (u16_i = 0x0000; u16_i < 0x03FF9; u16_i++)
	{
		*(addr + u16_i) = 0x5555;
		if (*(addr + u16_i) != 0x5555)
		{
			m_u16_RamCheckErr = 1;
		}
		*(addr + u16_i) = 0xaaaa;
		if (*(addr + u16_i) != 0xaaaa)
		{
			m_u16_RamCheckErr = 1;
		}
		*(addr + u16_i) = 0x0000;
	}
	
	if(m_u16_RamCheckErr == 1)
	{
		while(1)
		{
			asm(" nop");
		}
	}
}
//程序ｃｏｐｙ函数
void	Class_RAMDrv::Drv_MemCopy(unsigned int *SourceAddr, unsigned int* SourceEndAddr, unsigned int* DestAddr)
{

	/******DSP RUN TRACE************************/	
	*(volatile unsigned int *)0x00013FFD = *(volatile unsigned int *)0x00013FFC;
	*(volatile unsigned int *)0x00013FFC = 0x0B03;
	/*******************************************/
	while(SourceAddr < SourceEndAddr)
    	{
       	*DestAddr++ = *SourceAddr++;
   	}
    return;
}


//============================================================
// End of file.
//============================================================



//#include "Drivers\XintfDrv.cpp" 		//0x0Fxx

/************************************************************************************
//函数名称：    公共函数实现及类变量定义
***********************************************************************************/

int   g_i16_IntCnt1Per2_0;
int   g_i16_IntCnt1Per4_0;

Class_Inverter          objInverter;        // 0x1701


// 0x2E01 控制中断函数EPWM_INT_ISR轨迹
unsigned int  g_u16_MainRunTime;      // 主函数运行时间测量
unsigned int  g_u16_MainRunTimeMax;   // 主函数最大运行时间

unsigned int  g_u16_INTRunTime;       // 中断运行时间测量
unsigned int  g_u16_INTRunTimeMax;    // 中断最大运行时间
unsigned int  g_u16ServiceModeCount;

//------------------------------
int igap(int curr_value, const FLAG_TABLE *f_table, int old_flag)
{
    /******DSP RUN TRACE************************/
    *(volatile unsigned int *)0x00013FFD = *(volatile unsigned int *)0x00013FFC;
    *(volatile unsigned int *)0x00013FFC = 0x0D02;
    /*******************************************/
    unsigned int i, j;

    /*reseach range table.*/
    for(i = 0; i <= (*f_table).num; i++)
    {
        if (curr_value < (*f_table).range[i])
            break;
    }
    /*if reseach failure, return old flag.*/
    if (i == 0 || i > (*f_table).num)
    {
        return(old_flag);
    }

    /*reseach flags table.*/
    for(j = 1; j <= (*f_table).num; j++)
    {
        if (old_flag == (*f_table).flags[j-1])
            break;
    }
    /*if reseach failure, return curr flag.*/
    if ( j> (*f_table).num )
    {
        return((*f_table).flags[i-1]);
    }

    /*judge igap acrossed.*/
    if (i < j && curr_value > ((*f_table).range[i] - (*f_table).half_gap) )
    {
        i++;
    }
    else if (i > j && curr_value < ((*f_table).range[i-1] + (*f_table).half_gap) )
    {
        i--;
    }

    /*return ture flag.*/
    return((*f_table).flags[i-1]);
}


//===========================================================================
// End of file.
//===========================================================================


	






//###########################################################################
//
// FILE:   F2807x_DefaultISR.c
//
// TITLE:  F2807x Device Default Interrupt Service Routines
//
//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//#include "F2807x_device.h"       // F2807x Header File Include File
//#include "F2807x_Examples.h"     // F2807x Examples Include File

//---------------------------------------------------------------------------
// CPU Timer 1 Interrupt
interrupt void TIMER1_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// CPU Timer 2 Interrupt
interrupt void TIMER2_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// Datalogging Interrupt
interrupt void DATALOG_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// RTOS Interrupt
interrupt void RTOS_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// Emulation Interrupt
interrupt void EMU_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// Non-Maskable Interrupt
interrupt void NMI_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// Illegal Operation Trap
interrupt void ILLEGAL_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 1
interrupt void USER1_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 2
interrupt void USER2_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 3
interrupt void USER3_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 4
interrupt void USER4_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 5
interrupt void USER5_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 6
interrupt void USER6_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 7
interrupt void USER7_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 8
interrupt void USER8_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 9
interrupt void USER9_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 10
interrupt void USER10_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 11
interrupt void USER11_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// User Defined Trap 12
interrupt void USER12_ISR(void)
{
    // Insert ISR Code here

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.1 - ADCA Interrupt 1
interrupt void ADCA1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.2 - ADCB Interrupt 1
interrupt void ADCB1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.4 - XINT1 Interrupt
interrupt void XINT1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.5 - XINT2 Interrupt
interrupt void XINT2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.6 - ADCD Interrupt 1
interrupt void ADCD1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.7 - Timer 0 Interrupt
interrupt void TIMER0_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.8 - Standby and Halt Wakeup Interrupt
interrupt void WAKE_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.1 - ePWM1 Trip Zone Interrupt
interrupt void EPWM1_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.2 - ePWM2 Trip Zone Interrupt
interrupt void EPWM2_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.3 - ePWM3 Trip Zone Interrupt
interrupt void EPWM3_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.4 - ePWM4 Trip Zone Interrupt
interrupt void EPWM4_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.5 - ePWM5 Trip Zone Interrupt
interrupt void EPWM5_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.6 - ePWM6 Trip Zone Interrupt
interrupt void EPWM6_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.7 - ePWM7 Trip Zone Interrupt
interrupt void EPWM7_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.8 - ePWM8 Trip Zone Interrupt
interrupt void EPWM8_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.1 - ePWM1 Interrupt
interrupt void EPWM1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.2 - ePWM2 Interrupt
interrupt void EPWM2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.3 - ePWM3 Interrupt
interrupt void EPWM3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.4 - ePWM4 Interrupt
interrupt void EPWM4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.5 - ePWM5 Interrupt
interrupt void EPWM5_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.6 - ePWM6 Interrupt
interrupt void EPWM6_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.7 - ePWM7 Interrupt
interrupt void EPWM7_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.8 - ePWM8 Interrupt
interrupt void EPWM8_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.1 - eCAP1 Interrupt
interrupt void ECAP1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.2 - eCAP2 Interrupt
interrupt void ECAP2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.3 - eCAP3 Interrupt
interrupt void ECAP3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.4 - eCAP4 Interrupt
interrupt void ECAP4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.5 - eCAP5 Interrupt
interrupt void ECAP5_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 4.6 - eCAP6 Interrupt
interrupt void ECAP6_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 5.1 - eQEP1 Interrupt
interrupt void EQEP1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 5.2 - eQEP2 Interrupt
interrupt void EQEP2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 5.3 - eQEP3 Interrupt
interrupt void EQEP3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.1 - SPIA Receive Interrupt
interrupt void SPIA_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.2 - SPIA Transmit Interrupt
interrupt void SPIA_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.3 - SPIB Receive Interrupt
interrupt void SPIB_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.4 - SPIB Transmit Interrupt
interrupt void SPIB_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.5 - McBSPA Receive Interrupt
interrupt void MCBSPA_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.6 - McBSPA Transmit Interrupt
interrupt void MCBSPA_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.7 - McBSPB Receive Interrupt
interrupt void MCBSPB_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.8 - McBSPB Transmit Interrupt
interrupt void MCBSPB_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.1 - DMA Channel 1 Interrupt
interrupt void DMA_CH1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.2 - DMA Channel 2 Interrupt
interrupt void DMA_CH2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.3 - DMA Channel 3 Interrupt
interrupt void DMA_CH3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.4 - DMA Channel 4 Interrupt
interrupt void DMA_CH4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.5 - DMA Channel 5 Interrupt
interrupt void DMA_CH5_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 7.6 - DMA Channel 6 Interrupt
interrupt void DMA_CH6_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.1 - I2CA Interrupt 1
interrupt void I2CA_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.2 - I2CA Interrupt 2
interrupt void I2CA_FIFO_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.3 - I2CB Interrupt 1
interrupt void I2CB_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.4 - I2CB Interrupt 2
interrupt void I2CB_FIFO_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.5 - SCIC Receive Interrupt
interrupt void SCIC_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.6 - SCIC Transmit Interrupt
interrupt void SCIC_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.7 - SCID Receive Interrupt
interrupt void SCID_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 8.8 - SCID Transmit Interrupt
interrupt void SCID_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.1 - SCIA Receive Interrupt
interrupt void SCIA_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.2 - SCIA Transmit Interrupt
interrupt void SCIA_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.3 - SCIB Receive Interrupt
interrupt void SCIB_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.4 - SCIB Transmit Interrupt
interrupt void SCIB_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.5 - CANA Interrupt 0
interrupt void CANA0_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.6 - CANA Interrupt 1
interrupt void CANA1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.7 - CANB Interrupt 0
interrupt void CANB0_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.8 - CANB Interrupt 1
interrupt void CANB1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.1 - ADCA Event Interrupt
interrupt void ADCA_EVT_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.2 - ADCA Interrupt 2
interrupt void ADCA2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.3 - ADCA Interrupt 3
interrupt void ADCA3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.4 - ADCA Interrupt 4
interrupt void ADCA4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.5 - ADCB Event Interrupt
interrupt void ADCB_EVT_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.6 - ADCB Interrupt 2
interrupt void ADCB2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.7 - ADCB Interrupt 3
interrupt void ADCB3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.8 - ADCB Interrupt 4
interrupt void ADCB4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.1 - CLA1 Interrupt 1
interrupt void CLA1_1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.2 - CLA1 Interrupt 2
interrupt void CLA1_2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.3 - CLA1 Interrupt 3
interrupt void CLA1_3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.4 - CLA1 Interrupt 4
interrupt void CLA1_4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.5 - CLA1 Interrupt 5
interrupt void CLA1_5_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.6 - CLA1 Interrupt 6
interrupt void CLA1_6_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.7 - CLA1 Interrupt 7
interrupt void CLA1_7_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 11.8 - CLA1 Interrupt 8
interrupt void CLA1_8_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.1 - XINT3 Interrupt
interrupt void XINT3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.2 - XINT4 Interrupt
interrupt void XINT4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.3 - XINT5 Interrupt
interrupt void XINT5_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.6 - VCU Interrupt
interrupt void VCU_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.7 - FPU Overflow Interrupt
interrupt void FPU_OVERFLOW_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.8 - FPU Underflow Interrupt
interrupt void FPU_UNDERFLOW_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.13 - IPC Interrupt 0
interrupt void IPC0_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.14 - IPC Interrupt 1
interrupt void IPC1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.15 - IPC Interrupt 2
interrupt void IPC2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 1.16 - IPC Interrupt 3
interrupt void IPC3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.9 - ePWM9 Trip Zone Interrupt
interrupt void EPWM9_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.10 - ePWM10 Trip Zone Interrupt
interrupt void EPWM10_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.11 - ePWM11 Trip Zone Interrupt
interrupt void EPWM11_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 2.12 - ePWM12 Trip Zone Interrupt
interrupt void EPWM12_TZ_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.9 - ePWM9 Interrupt
interrupt void EPWM9_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.10 - ePWM10 Interrupt
interrupt void EPWM10_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.11 - ePWM11 Interrupt
interrupt void EPWM11_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 3.12 - ePWM12 Interrupt
interrupt void EPWM12_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 5.9 - SD1 Interrupt
interrupt void SD1_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 5.10 - SD2 Interrupt
interrupt void SD2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.9 - SPIC Receive Interrupt
interrupt void SPIC_RX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 6.10 - SPIC Transmit Interrupt
interrupt void SPIC_TX_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 9.15 - USBA Interrupt
interrupt void USBA_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.13 - ADCD Event Interrupt
interrupt void ADCD_EVT_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.14 - ADCD Interrupt 2
interrupt void ADCD2_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.15 - ADCD Interrupt 3
interrupt void ADCD3_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 10.16 - ADCD Interrupt 4
interrupt void ADCD4_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.9 - EMIF Error Interrupt
interrupt void EMIF_ERROR_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.10 - RAM Correctable Error Interrupt
interrupt void RAM_CORRECTABLE_ERROR_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.11 - Flash Correctable Error Interrupt
interrupt void FLASH_CORRECTABLE_ERROR_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.12 - RAM Access Violation Interrupt
interrupt void RAM_ACCESS_VIOLATION_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.13 - System PLL Slip Interrupt
interrupt void SYS_PLL_SLIP_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.14 - Auxiliary PLL Slip Interrupt
interrupt void AUX_PLL_SLIP_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.15 - CLA Overflow Interrupt
interrupt void CLA_OVERFLOW_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

// 12.16 - CLA Underflow Interrupt
interrupt void CLA_UNDERFLOW_ISR(void)
{
    // Insert ISR Code here

    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    asm ("      ESTOP0");
    for(;;);
}

//---------------------------------------------------------------------------
// Catch-all Default ISRs:

// Reserved ISR
interrupt void PIE_RESERVED_ISR(void)
{
    asm ("      ESTOP0");
    for(;;);
}

// Only does a return
interrupt void EMPTY_ISR(void)
{

}

// Unused ISR
interrupt void NOTUSED_ISR(void)
{
    asm ("      ESTOP0");
    for(;;);
}



/*==========================================================*/

/*==========================================================*/



#pragma CODE_SECTION(".CriticalIntFuncsNOTSecured")
 void Class_Inverter::Dat_Int_InvCurrPQCalc(void)
{
    int   i16tmpPQ_0, i16tmpPQFilt1_0;

    m_i32Ia1stPFiltSum1_0 = m_i32Ia1stPFiltSum1_0 - m_i16Ia1stPFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ia1stPFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ia1stPFiltSum2_0 = m_i32Ia1stPFiltSum2_0 - m_i16Ia1stPFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ia1stPFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;

    m_i32Ia1stQFiltSum1_0 = m_i32Ia1stQFiltSum1_0 - m_i16Ia1stQFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ia1stQFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ia1stQFiltSum2_0 = m_i32Ia1stQFiltSum2_0 - m_i16Ia1stQFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ia1stQFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;

    m_i32Ib1stPFiltSum1_0 = m_i32Ib1stPFiltSum1_0 - m_i16Ib1stPFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ib1stPFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ib1stPFiltSum2_0 = m_i32Ib1stPFiltSum2_0 - m_i16Ib1stPFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ib1stPFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;

    m_i32Ib1stQFiltSum1_0 = m_i32Ib1stQFiltSum1_0 - m_i16Ib1stQFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ib1stQFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ib1stQFiltSum2_0 = m_i32Ib1stQFiltSum2_0 - m_i16Ib1stQFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ib1stQFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;
    
    m_i32Ic1stPFiltSum1_0 = m_i32Ic1stPFiltSum1_0 - m_i16Ic1stPFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ic1stPFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ic1stPFiltSum2_0 = m_i32Ic1stPFiltSum2_0 - m_i16Ic1stPFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ic1stPFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;

    m_i32Ic1stQFiltSum1_0 = m_i32Ic1stQFiltSum1_0 - m_i16Ic1stQFiltArray1_0[m_i16I1stFiltIndex1_0] + i16tmpPQ_0;
    m_i16Ic1stQFiltArray1_0[m_i16I1stFiltIndex1_0] = i16tmpPQ_0;

    m_i32Ic1stQFiltSum2_0 = m_i32Ic1stQFiltSum2_0 - m_i16Ic1stQFiltArray2_0[m_i16I1stFiltIndex2_0] + i16tmpPQFilt1_0;
    m_i16Ic1stQFiltArray2_0[m_i16I1stFiltIndex2_0] = i16tmpPQFilt1_0;

}



//===========================================================================
// End of file.
//===========================================================================






/*==========================================================*/
/* Title        :   FlashUpdate.h                           */
/* Description  :   Class_FlashUpdate definition                */
/* Copyright     :     ENPC Corporation                            */
/* Version        :     V000                                           */
/* Author         :     Zhuo Qingfeng                             */
/* Date            :    Apr.2013                               */
/* Contributor:                                          */
/*==========================================================*/




extern Uint16 Flash28_API_LoadStart;
extern Uint16 Flash28_API_LoadEnd;
extern Uint16 Flash28_API_RunStart;

// 全局变量定义




//============================================================
//  Class_FlashUpdate与外部的接口
//  1)
//  2)
//  3)调用
//  4)调用
//============================================================
class Class_FlashUpdate
{
private:

public:

    void    MainSwitch(void);  //所有程序入口

};


//============================================================
// End of file.
//============================================================




//所有程序入口
#pragma CODE_SECTION("Flash28Funcs");
void Class_FlashUpdate::MainSwitch(void)
{
    asm(" .label _MainSwitch");

    // 完成C语言运行环境初始化
    asm(" MOV     @SP,#0x0000");
    asm(" SPM     0");
    asm(" SETC    OBJMODE");
    asm(" CLRC    AMODE");
    asm(" SETC    M0M1MAP");
    asm(" CLRC    PAGE0");
    asm(" MOVW    DP,#0x0000");
    asm(" CLRC    OVM");
    asm(" ASP");

    int i16us,i16ms,i;

    for(i =0; i<1000; i++)
    {
        asm(" RPT #119 || NOP");
    }


    // 0x3F3FFF存放程序分支标志:0x5500-收到flashupdate命令;
    // 0x55AA-flash烧写完成;0xFFFF-flash已被擦除
    if (*((unsigned int *) 0x33BFFF) == 0x55BB)                   // 正常主程序分支
    {
        asm(" LB 33BFFCH");
    }
    
}



//###########################################################################
// $TI Release: F2807x Support Library v180 $
// $Release Date: Fri Nov  6 16:33:02 CST 2015 $
// $Copyright: Copyright (C) 2014-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

extern unsigned int CriticalIntFuncsSecuredLoadStart;
extern unsigned int CriticalIntFuncsSecuredLoadEnd;
extern unsigned int CriticalIntFuncsSecuredRunStart;

extern unsigned int CriticalIntFuncsNOTSecuredLoadStart;
extern unsigned int CriticalIntFuncsNOTSecuredLoadEnd;
extern unsigned int CriticalIntFuncsNOTSecuredRunStart;


extern Uint16 Flash28_API_LoadStart;
extern Uint16 Flash28_API_LoadEnd;
extern Uint16 Flash28_API_RunStart;



void main(void)
{


    objSysDrv.Drv_SysCtrlInit();

    objSysDrv.Drv_InitPIE();

    objSysDrv.Drv_InitInterrupts();

    objRAMDrv.Drv_RamCheck();

    objRAMDrv.Drv_MemCopy(&CriticalIntFuncsNOTSecuredLoadStart, &CriticalIntFuncsNOTSecuredLoadEnd, &CriticalIntFuncsNOTSecuredRunStart);
    objRAMDrv.Drv_MemCopy(&CriticalIntFuncsSecuredLoadStart, &CriticalIntFuncsSecuredLoadEnd, &CriticalIntFuncsSecuredRunStart);

    objGPIODrv.Drv_InitGPIO();	
	
 objPWMDrv.Drv_InitPWM();

    __asm(" clrc INTM");

    objWatchDogDrv.Drv_EnableDog();

    g_u16_INTRunTimeMax = 0;

    while(1)
    {

        if (g_u16_INTRunTimeMax <= 32000)
        {
            g_u16ServiceModeCount++;

            if (g_u16ServiceModeCount == 30000)
            {
                g_u16ServiceModeCount = 0;
            }
        }
    }
}


//===========================================================================
// End of file.
//===========================================================================

extern unsigned int CriticalIntFuncsSecuredLoadStart;
extern unsigned int CriticalIntFuncsSecuredLoadEnd;
extern unsigned int CriticalIntFuncsSecuredRunStart;


#pragma CODE_SECTION(".CriticalIntFuncsSecured")            // 必须放在加密区

interrupt void EPWM_INT_ISR(void)                           // 下溢中断
{

    EPwm1Regs.ETCLR.bit.INT = 1;						
    PieCtrlRegs.PIEACK.all = 0x0004; 				

    GpioDataRegs.GPBSET.bit.GPIO43 = 1;
    objInverter.Dat_Int_InvCurrPQCalc();
    GpioDataRegs.GPBCLEAR.bit.GPIO43 = 1;
}

	


