// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File 
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are. 
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMLS0_0         : origin = 0x008000, length = 0x000300
   RAMLS0_1         : origin = 0x008300, length = 0x000500
   RAMLS12345	: origin = 0x008800, length = 0x002800
   RAMD0			: origin = 0x00B000, length = 0x000050
   RAMD01		: origin = 0x00B050, length = 0x000FB0

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   RAMGS4567	     : origin = 0x00F000, length = 0x004000

   /* Flash sectors */
   FLASHACONST      : origin = 0x080002, length = 0x000FFE	/* on-chip Flash */
   FLASHAB           : origin = 0x081000, length = 0x003000	/* on-chip Flash */  

//   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
//   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
//   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
//   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
//   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
//   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
//   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
//  FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
//   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
//   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
//   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
//   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
   FLASHCTON        : origin = 0x084000, length = 0x03C000	/* on-chip Flash */


PAGE 1 :

   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

  CRAZYDSPRAM : origin = 0x00BFFC, length = 0x000004     /* at on-chip SARAM block D1 */
  RAMGS012       : origin = 0x00C000, length = 0x002800
   RAMGS3           : origin = 0x00E800, length = 0x000800
   //RAMGS7         : origin = 0x013000, length = 0x001000

                    
   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080
   /* on-chip RAM block GS4 Devided into 2 parts*/
   /* RAMDSPFLASHDATA used for DSP CAN-flashupdate and SCI-flashupdate*/
   /* RAMFPGAFLASHDATA used for FPGA CAN-flashupdate and SCI-flashupdate*/
   RAMFLASHDATA    : origin = 0x012000, length = 0x0F00     /* on-chip RAM block L7 2k*/
   RAMEEPROMDATA	: origin = 0x012F00, length = 0x100     /* on-chip RAM block L7 */    

   
}


SECTIONS
{
   /* Allocate program areas: */
   .cinit           : > FLASHCTON      PAGE = 0, ALIGN(4)
   .pinit           : > FLASHCTON,     PAGE = 0, ALIGN(4)
   .text            : > FLASHCTON      PAGE = 0, ALIGN(4)
   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs         : LOAD = FLASHCTON,
                      RUN = RAMD0,
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)

    UNION:          RUN = RAMD01
    {
        .CriticalIntFuncsSecured      : LOAD = FLASHCTON,
                                        LOAD_START(_CriticalIntFuncsSecuredLoadStart),
                                        LOAD_END(_CriticalIntFuncsSecuredLoadEnd),
                                        RUN_START(_CriticalIntFuncsSecuredRunStart),
                                        PAGE = 0

        Flash28_API:
			LOAD = FLASHAB,
            LOAD_START(_Flash28_API_LoadStart),
            LOAD_END(_Flash28_API_LoadEnd),
            RUN_START(_Flash28_API_RunStart),
            PAGE = 0
    }

    .CriticalIntFuncsNOTSecured             : LOAD = FLASHCTON,
                                            RUN = RAMGS4567,
                                            LOAD_START(_CriticalIntFuncsNOTSecuredLoadStart),
                                            LOAD_END(_CriticalIntFuncsNOTSecuredLoadEnd),
                                            RUN_START(_CriticalIntFuncsNOTSecuredRunStart),
                                            PAGE = 0

					 
   /* Allocate uninitalized data sections: */
   .stack           : > RAMM1        PAGE = 1
   .ebss            : > RAMGS012     PAGE = 1
   .esysmem         : > RAMGS3       PAGE = 1

   /* Initalized sections go in Flash */
   .econst          : > FLASHCTON      PAGE = 0, ALIGN(4)
   .switch          : > FLASHCTON      PAGE = 0, ALIGN(4)
   
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */


    /* CLA specific sections */
   Cla1Prog         : LOAD = FLASHCTON,
                      RUN = RAMLS12345,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      LOAD_SIZE(_Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(4)

   CLADataLS0		: > RAMLS0_0, PAGE=0

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1


  /*allocate three sections in the same address*/

    UNION: > RAMFLASHDATA       PAGE = 1
    {
        .FaultRecord
        .DSPflashdata
        .FPGAflashdata
    }
 


   .FPGAEEPROMdata   : > RAMEEPROMDATA		     PAGE = 1 
   
	/***Consts in  FlashA allocated here ***/
	   .FlashAconst 	   : > FLASHACONST     PAGE = 0
	   
#ifdef CLA_C

   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS0_0,  PAGE = 0

   .scratchpad      : > RAMLS0_0,       PAGE = 0
   .bss_cla		    : > RAMLS0_0,       PAGE = 0
   .const_cla	    :  LOAD = FLASHCTON,
                       RUN = RAMLS0_1,
                       RUN_START(_Cla1ConstRunStart),
                       LOAD_START(_Cla1ConstLoadStart),
                       LOAD_END(_Cla1ConstLoadEnd),
                       LOAD_SIZE(_Cla1ConstLoadSize),
                       PAGE = 0, ALIGN(4)
#endif //CLA_C
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/
