reg_value codec_inst[] = {  
    {  0,0x00},
//          # reg[0][1]   = 0x01     ; S/W Reset
    {  1,0x01},
//          # reg[0][4]   = 0x03   ; PLL_CLKIN = MCLK = 11.2896 MHz., CODEC_CLKIN=PLL_CLK
    {  4,0x03},
//          # reg[0][5]   = 0x91   ; PLL Power Up, P = 1, R = 1
    {  5,0x91},
//          # reg[0][6]   = 0x08   ; J = 8
    {  6,0x08},
//          # reg[0][7]   = 0x00   ; D(13:8) = 0
    {  7,0x00},
//          # reg[0][8]   = 0x00   ; D(7:0) = 0 (CODEC_CLKIN = (PLL_CLKIN * R * J.D) / P = 90.3168 MHz.
    {  8,0x00},
//          # reg[0][27]  = 0x00   ; Mode = I2S, wordlength = 16
    { 27,0x00},
    {  0,0x2B},
//          # reg[43][95]     = 0x00  ; (Bit 23-16) ------------ MSB ADC INST No. 383
    { 95,0x00},
//          # reg[43][96]     = 0x00  ; (Bit 15-8)
    { 96,0x00},
//          # reg[43][97]     = 0x00  ; (Bit 7-0)
    { 97,0x00},
    {  0,0x5F},
//          # reg[95][95]     = 0x00  ; (Bit 23-16) ------------ MSB DAC INST No. 1023
    { 95,0x00},
//          # reg[95][96]     = 0x00  ; (Bit 15-8)
    { 96,0x00},
//          # reg[95][97]     = 0x00  ; (Bit 7-0)
    { 97,0x00},
    {  0,0x00},
//          
    { 21,0xB8},
//          
    { 15,0x5C},
//          # reg[0][60]  = 0x40   ; DAC programmable mode, DAC miniDSP powered up even if DAC is powered down
    { 60,0x40},
//          # reg[0][61]  = 0x00   ; PRB_R5 05
    { 61,0x00},
//          # reg[0][63]  = 0xD4   ;
    { 63,0xD4},
//          # reg[0][64]  = 0x02   ;
    { 64,0x02},
    {255,0x00},
    {255,0x01},
    {  0,0x00},
//          # reg[0][13]  = 0x00   ; DOSR = 32, DOSR(9:8) = 0; DOSR = 32, DOSR(7:0) = 32 (DAC Fs = 5.6448 / 32 = 176.4 KHz.); Interpolation Ratio = 2; AOSR = 32 (ADC Fs = 5.6448 / 32 = 176.4 KHz.); Decimation Ratio = 1; DOSR = 64, DOSR(9:8) = 0; DOSR = 64, DOSR(7:0) = 64 (DAC Fs = 5.6448 / 64 = 88.2 KHz.); Interpolation Ratio = 2; AOSR = 64 (ADC Fs = 5.6448 / 64 = 88.2 KHz.); Decimation Ratio = 2; DOSR = 128, DOSR(9:8) = 0
    { 13,0x00},
//          # reg[0][14]  = 0x80   ; DOSR = 128, DOSR(7:0) = 32 (DAC Fs = 5.6448 / 128 = 44.1 KHz.)
    { 14,0x80},
//          # reg[0][16]  = 0x08   ; Interpolation Ratio = 8
    { 16,0x08},
//          # reg[0][20]  = 0x80   ; AOSR = 128 (ADC Fs = 5.6448 / 128 = 44.1 KHz.)
    { 20,0x80},
//          # reg[0][22]  = 0x04   ; Decimation Ratio = 4
    { 22,0x04},
    {  0,0x01},
//          # reg[1][33]  = 0x4e   ; De-pop, Power on = 800 ms., Step time = 4 ms.
    { 33,0x4E},
//          # reg[1][31]  = 0xc6   ; HPL and HPR powered up
    { 31,0xC6},
//          # reg[1][32]  = 0xc6   ; SPL on
    { 32,0xC6},
//          # reg[1][35]  = 0x50   ; LDAC routed to mixer, LMIC
    { 35,0x65},
//          # reg[1][36]  = 0x80   ; HPL on
    { 36,0x80},
		{ 37,0x80},
//          # reg[1][38]  = 0x94   ; -20 SPL vol 0dB
    { 38,0x94},
//          # reg[1][40]  = 0x16
    { 40,0x16},
//          # reg[1][42]  = 0x04   ; SPL unmute, gain 6dB
    { 42,0x04},
//          # reg[1][46]  = 0x0b   ; MICBIAS
    { 46,0x0B},
    {  0,0x00},
//          # reg[0][83]  = 0x1e   ; ADC GAIN 15dB
    { 83,0x28},
    {  0,0x01},
//          # reg[1][48]  = 0x40   ; MIC is selected for left Mic PGA P @ 10k input impedance
    { 48,0x40},
//          # reg[1][49]  = 0x40   ; CM is selected for left Mic PGA M @ 10k input impedance
    { 49,0x40},
    {  0,0x00},
//          # reg[0][63]  = 0xd6   ; Powerup DAC left and right channels (soft step disable)
    { 63,0xD6},
//          # reg[0][64]  = 0x00   ; Unmute DAC left and right channels
    { 64,0x00},
//          # reg[0][81]  = 0x80   ; Powerup ADC channel
    { 81,0x80},
//          # reg[0][82]  = 0x00   ; Unmute ADC channel
    { 82,0x00},
//          # reg[0][11]  = 0x84   ; DAC Powerup NDAC = 2 (DAC_MAC_CLK = 90.3168 MHz/2 = 45.1584 MHz.); DAC Powerup MDAC = 8 (DAC_MOD_CLK = 45.1584/8 = 5.6448 MHz.); ADC Powerup NADC = 4 (ADC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.); DAC Powerup MADC = 4 (ADC_MOD_CLK = 22.5792/4 = 5.6448 MHz.); DAC Powerup NDAC = 4 (DAC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.)
    { 11,0x84},
//          # reg[0][12]  = 0x84   ; DAC Powerup MDAC = 4 (DAC_MOD_CLK = 22.5792/4 = 5.6448 MHz.)
    { 12,0x84},
//          # reg[0][18]  = 0x84   ; ADC Powerup NADC = 4 (ADC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.)
    { 18,0x84},
//          # reg[0][19]  = 0x84   ; DAC Powerup MADC = 4 (ADC_MOD_CLK = 22.5792/4 = 5.6448 MHz.)
    { 19,0x84},
    {  0,0x08},
//          # reg[8][1]   = 0x04   ; Adaptive mode enabled for DAC
    {  1,0x04},
    {  0,0x00},
//          # reg[  0][  5] = 0x91  ; P=1, R=1, J=8
    {  5,0x91},
//          # reg[  0][  6] = 0x08  ; P=1, R=1, J=8
    {  6,0x08},
//          # reg[  0][  7] = 0x00  ; D=0000 (MSB)
    {  7,0x00},
//          # reg[  0][  8] = 0x00  ; D=0000 (LSB)
    {  8,0x00},
//          # reg[  0][  4] = 0x03  ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    {  4,0x03},
//          # reg[  0][ 12] = 0x88  ; MDAC = 8, divider powered on
    { 12,0x88},
//          # reg[  0][ 13] = 0x00  ; DOSR = 128 (MSB)
    { 13,0x00},
//          # reg[  0][ 14] = 0x80  ; DOSR = 128 (LSB)
    { 14,0x80},
//          # reg[  0][ 18] = 0x02  ; NADC = 2, divider powered off
    { 18,0x02},
//          # reg[  0][ 19] = 0x88  ; MADC = 8, divider powered on
    { 19,0x88},
//          # reg[  0][ 20] = 0x80  ; AOSR = 128
    { 20,0x80},
//          # reg[  0][ 11] = 0x82  ; NDAC = 2, divider powered on
    { 11,0x82},
//          # reg[0][82] = 0
    { 82,0x00},
//          # reg[0][83] = 0
    { 83,0x00},
//          # reg[0][86] = 32
    { 86,0x20},
//          # reg[0][87] = 254
    { 87,0xFE},
//          # reg[0][88] = 0
    { 88,0x00},
//          # reg[0][89] = 104
    { 89,0x68},
//          # reg[0][90] = 168
    { 90,0xA8},
//          # reg[0][91] = 6
    { 91,0x06},
//          # reg[0][92] = 0
    { 92,0x00},
};