++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 25March2019 MCU SW Version - 2.3.1 NOTES: 1) There are separate *.hexout, *.hex (generic SPI), and *.bin files to support 64 Mbit and 128 Mbit serial SPI flash devices. *.hexout and *.hex files are for loading blank PROMs before installation, and bin files are for field updates over USB/SPI. 2) 128 Mbit MCU 2.3.0 programmed PROMS CANNOT be field updated using the MCU 2.3.1 128 Mbit *.bin file. Please ensure you are using the appropriate file based on your system! 3) The *.hex files were tested using a generic SPI programmer and should work with most generic SPI programmers. ************************************ WARNING: **************************************** The 128 Mbit and 64 Mbit *.bin files are the same size. Loading a *.bin file targeting the wrong size flash PROM will render the system inoperable. The PROM will have to be removed and replaced with a PROM that has been pre-programmed with *.hexout or *.hex file that matches the correct PROM size. ************************************************************************************** Bug Fixes 1. ALC_DLPC200-123 - Fixed - Does not switch back to Structured Light Pattern mode directly from EXP port video. 2. ALC_DLPC200-127 - The SPI WriteImageOrderLut does not accept more than one packet (250 entries). [USB command works up to available number of patterns] Known issues: 1. ALC_DLPC200-126 - Some customers have experienced failure to initialize if an active signal is connnected to the HDMI input and/or the USB port during initialization. Workaround - do not enable HDMI hot plug and/or USB enumeration cycle until after the DLPC200 has completed initialization. 2. ALC_DLPC200-136 - Some customer have experienced Image order corruption after loading a single image over SPI. 3. Newer parallel flash parts write at 1/2 the speed of the original parallel flash part. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 08December2017 MCU SW Version - 2.3.0 New request(s) implemented 1. ALC_DLPC200-118 & ALC DLPC200-119 - Add support and .hexout file for 128 MB PROM 2. ALC_DLPC200-112 - Test with replacement part numbers for EOL flash (P/N documented in DLPC200 datasheet) Bug Fixes 1. ALC_DLPC200-114 - Load from flash to memory over SPI 2. ALC_DLPC200-108 & ALC_DLPC200-109 - Intermittently missing sync output signal Known issues: 1. ALC_DLPC200-123 - Does not switch back to Structured Light Pattern mode directly from EXP port video. Workaround - switch first to DVI video port then to Structured Light Pattern mode. 2. ALC_DLPC200-126 - Some customers have experienced failure to initialize if an active signal is connnected to the HDMI input and/or the USB port during initialization. Workaround - do not enable HDMI hot plug and/or USB enumeration cycle until after the DLPC200 has completed initialization. 3. ALC_DLPC200-127 - The SPI WriteImageOrderLut does not accept more than one packet (250 entries). [USB command works up to available number of patterns] ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 18September2013 MCU SW Version - 2.2.0 New request(s) implemented 1. CQ16877 - Changes requested in DLPC200 reset initialization steps 2. CQ16992 - DMD RSC_DRC Reset Waveform Control LUT update needed Bug Fixes 1. CQ15078 - DLPC200 reset initialization failure 2. CQ16876 - FPGA build #455, periodic one line vertical observed in the displayed image ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 17September2012 MCU SW Version - 2.1.7 Bug Fixes 1. CQ15407 - AMD command type flash support, modify Altera HAL driver to allow flash read ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 13July2012 MCU SW Version - 2.1.6 (refreeze) New request(s) implemented 1. CR15079 - Support added detect other 0.55" XGA S450 DMD Version 1 DMDs with device hard wired ID 0x53 and 0x54. And new Version 2 0.55" XGA S450 DMD with device hard wired ID 0x5E. Bug Fixes 1. CQ15078 - DLPC200 reset initialization condition garbage is displayed on the DMD. [Issue detected on Keyence,Japan hardware]. 2. CQ15080 - MCU attempts communicating with LED Driver over SPI master port even if LED Driver is not connected. 3. CQ15081 - Run-pattern-once feature will NOT work if LED driver is not connected. 4. CQ15148 - In the MCU code as part of EEPROM EDID verification any I2C message read/write error occuring is ignored. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 30March2012 MCU SW Version - 2.1.6 New request(s) implemented 1. CR14434 - Add support for controlling four PWM ports on the DLPC200 IC 2. CR14435 - SW VSYNC generation support added Bug Fixes 1. CQ14466 - Negative Polarity selection is not working for SYNC o/p signals 2. CQ14676 - When communicating via SPI slave port validation is done in the code to check if the lentgh of packet exceeds 512 bytes. This results in MCU waiting until all the bytes are received. For example - If Length info in packet sent as 65535 then MCU wait until all 633535 bytes received before responding. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 04August2011 MCU SW Version - 2.1.5 New request(s) implemented 1. CR14156 - Reduce max output current of Red LED to 5.0Amps in structured light mode 2. CR14159 - Reduce the code size by removing the debug messages in release build ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 18July2011 MCU SW Version - 2.1.4 Bug-fixes - 1. CQ14005 - Calling DLP_Display_DisplayPatternAutoStepForSinglePass API starts with random pattern number instead of first pattern. 2. CQ14019 - First pattern skipped when single pass or multiple pass is called. 3. CQ14028 - At 6Hz speed the DLP_LED_SetLEDintensity is failing sometimes. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 27April2011 MCU SW Version - 2.1.3 New Things: 1. Support added for run-patterns-once, a new Extended Packet added DisplayPatternAutoStepForSinglePass (EP ID 0x0033) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 12November2010 MCU SW Version - 2.1.2 New Things: 1. New Extended Packet added for PWMSequence Enable/Disable. CR #DLP00013532 Bug-fixes - 1. DLP00013524 fixed. When trying to run EP Cmd#0xA to *Get* LED intensity works iff *Set* LED intensity called first. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 6September2010 MCU SW Version - 2.1.1 Bug-fixes - 1. CRDLP00013395 fixed. Read from Parallel Flash does not work when number of bytes to read increased beyond 2048 bytes. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 11August2010 MCU SW Version - 2.1.0 New Things: 1. Support added for two new extended packets(see below) refer LightCommander_Extended_Packet_Def_v1.1.doc specification a) DownloadBPPfromFlashToExtMem (0x0030) b) LoadSolutionFromFlash (0x0031) Bug-fixes - 1. SetDataSource extended packet (id = 0x000E) fails to update SSF_CONTROL register[0x0480] when source is selected as SL_AUTO, SL_EXT3P3, SL_EXT1P8, and SL_SW. CR #DLP00013228 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 29June2010 MCU SW Version - 2.0.0 This is the first draft version of the Phase1.1 baseline. This code base is basically taken from MCU Version 1.3.0 and new things added as part of Phase 1.1 release. This build is tested with fpga build #363. Note, phase 1 dot 1 mcu version starts from 2.x.x New Things: 1. Low level PC APIv1.6.0 interfaces moved into MCU SW; the documentation for the new packets are called as Extended packets; the latest version v0.4 of document is copied under release directory. 2. Added functionality to read data from ANY given memory location on the system. The memory locations are H/W LUT/mailbox, EDID EEPROM, Serial Flash, and Parallel Flash. Please refer MMK_SW_Packet_Def_v12.doc (under ...\discovery\__PROJECTS\MM_Kit\_400__Design\Software\) path. This is useful in system debug. 3. Parallel Flash writes speed improvements; mcu software now uses buffered programming capability of the flash device. Modifications: 1. Modified debug output logic to first, buffer the data second, print when idle task (SystemMainTask) is running. This will avoid calling the JTAG-UART/UART driver functions in the middle of other functions to print the log which will avoid unnecessary time. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ************************************************************************************** ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 25May2010 MCU SW Version - 1.3.0 This build is tested with fpga build #363 New feature 1. Init from flash and load solution from flash functions return more detailed information via SW_FLASH_INIT_PASS register [0x0CA4]. The meaning of each bit/flag in the register #define INIT_FRM_FLSH_PASS BIT0 //Will be SET on Init from flash or load solution success #define INIT_FRM_FLSH_ATTEMPTED BIT1 //Will be SET when init or load attempt made #define INIT_FRM_FLSH_FAIL_DEV_ACCESS BIT2 //Will be SET when parallel flash could not be accessed #define INIT_FRM_FLSH_FAIL_SIG_MISMATCH BIT3 //Will be SET when flash signature mismatch detected #define INIT_FRM_FLSH_BF_FAIL_TI_PWR_UP BIT4 //Will be SET if failures detected while BF exe from TI power section #define INIT_FRM_FLSH_BF_FAIL_USR_PWR_UP BIT5 //Will be SET if failures detected while BF exe from user power section #define INIT_FRM_FLSH_BF_FAIL_LD_SOL BIT6 //Will be SET if failures detected while BF exe from user requested solution record #define INIT_FRM_FLSH_BF_RSVD BIT7 //Unused reserved for future 2. For the load solution if solution offset address could not be found or invalid; in the command response (16bit word in the response packet) BIT12 will be set i.e., error response code CMD_ERR_INVALID_ADD_OFST [0x1000] will be sent. Bug Fixes 1. SeqDLL version still returns 8bit value. 2. Pattern DMA setup sometimes causes ghosting of image; this happens with repeated Load Solution attempt. Modifications - 1. Updated fpga_reg.h map file as per fpga build #363 pbc spec. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 20May2010 MCU SW Version - 1.2.2 Bugfix - 1. If Flash download setup containg information regarding Parallel Flash as target and CRC16 skip flag selected; MCU erases serial flash instead of parallel flash. 2. Default RWC lut setup is not loading for all the w/f LUTs. Changes - There seems to be problem with pattern not downloading properly with DMA operation. Few files reverted back (barring code format changes) to v1.2.0 baseline; the reverted changes file names are fpga_reg.h, i2.c, init_from_flash.c. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 19May2010 MCU SW Version - 1.2.1 This software baseline is tested with FPGA build #363 Modifications - 1. RWC LUT updated as per instructions from Tsega. The value first value “0x0000040C” to “0x00000414” in other two RWC LUT is changed. Bugfix - 1. Load solution not work if the last record offset address in the flash is sent. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 18May2010 MCU SW Version - 1.2.0 This software baseline is tested with FPGA build #363 New feature added - 1. Load Solution from flash is supported w/o complete system reset. 2. Init from flash status enhanced to report whether flash init attempt made. This will be known from of BIT1 of [0x0ca4] SW_FLASH_INIT_PASS (Init from flash success), where '1' = Attempt made '0' = No attempt made. BIT0 defn remains unchanged. 3. Writing into [0x0ca4] SW_FLASH_INIT_PASS will clear the initialization status; this is useful to get status in case of load solution. Modifications - 1. RWC LUT updated as per instructions from Tsega. The first value in your table below is changed from “0x0000040C” to “0x00000414”; this will basically increase VCC2 setup time for XGA device. 2. fpga_reg map updated as per fpga build#363 Others - The source code is formatted using http://astyle.sourceforge.net/astyle.html free software. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 07May2010 MCU SW Version - 1.1.2 This software baseline is tested with FPGA build #348 New feature added - 1. Init from flash status will now be reflected as SUCESS '1' or FAIL '0' for API driver access. This is available via MCU register [0x0ca4] SW_RFU65 (RFU66) BIT0. Modifications - 1. The DRC_PVCC_LEVEL parameter in the RSC_DRC_PARK_VCC_CONTROL [0x0388] register changed back to VCC instead of VCC2. Bug fixes (from SW DVT) - 1. Whenever a valid EEPROM packet found in the flash during initialization; MCU takes long time to update (almost 2-3 seconds). 2. In the EEPROM packet, if the "offset" and the actual length of data passed goes beyond 128, MCU does not return error. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 05May2010 MCU SW Version - 1.1.1 This software baseline is tested with FPGA build #348 Modification - 1. Added default setup for another DMD Park control register, [0x0388] RSC_drc_park_vcc_control (Park VCC Control) where VCC_SETUP (4:0) is 0x0C (12) and the PVCC_LEVEL (bit 8) should to set to 1 (1 = VCC2). ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 22April2010 MCU SW Version - 1.1.0 This software baseline is tested with FPGA build #307 Issues Fixed - 1) Error not reported when erroneous packets sent a) Invalid CMD4 error not reported when there is invalid CMD4 in the cmd packet. b) Invalid CMD3 error not reported. When b.1) #number of address, data pairs in “Unmasked register write” NOT matching to actual data length in the packet b.2) #number of address, mask and data pairs in “Masked register write” NOT matching to actual data length in the packet b.3) #number of addresses in “Register read” NOT matching to actual data length in the packet Modification - 1. For DMD Device Id = 0x39, .55XGA type device; offset voltage modified to 8.5V from earlier 7.0V 2. LED Driver initialization; modified driver init routine enable LED_ENZ signal once. 3. main() function will know have default settings for DMD park control registers - [0x038c] = 0xC, [0x0390] = 0x8, [0x0394] = 0x208 (520) 4. Modified LED Driver status register [0xC98] query to return IR led driver status. Note - FPGA register needs modification to allow storing status of IR led. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 12April2010 MCU SW Version - 1.0.0 This software baseline is tested with FPGA build #307 Issues Fixed - 1. LED_LIT bit is system status register [0x0ca0] BIT9 set even though leds are off; this happens whenever DMD is parked. Modification - 1. MCU SW Version returns modified as per PBC is spec 4bits-8bits-4bits (Major - Minor - Patch) earlier it was (4bits-4bits-4bits) 2. Masked register write functionality is modified to handle 'software registers' register # 0x0C00 thru 0x0CD8 3. Added logic to shutdown LED Driver completely whenever system enters in flash programming mode. Previously LED driver is just disabled via SPI packet. Now LED_ENZ signal will be pulled HIGH to shutdown led driver completely. 4. Added 5Second timeout for each pattern DMA completion (previously no timeout specified) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 05April2010 MCU SW Version - 0.8.3 This software baseline is tested with FPGA build #289 Issues Fixed - 1. In the packet processing; register write updates stop once a software register is encountered. Modification - 1. Pattern DMA request from the flash is modified to handle multiple pattern download requests in a single packet. 2. Added LOGIC to talk to LED Drive only if LED_Driver initialization successfull. This is required as there is a chace of LED Driver setup related packets present in flash. This logic will be used when LED Driver initalization failed or skipped (because of DMD parked). 3. Added LOGIC to apply default drive values only when Red, Green and Blue led drive level shows ZERO after intialization from flash. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 29March2010 MCU SW Version - 0.8.2 This software baseline is tested with FPGA build #289 Issues Fixed - 1. 2x default current on 10BIT LED Driver. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 26March2010 MCU SW Version - 0.8.1 This software baseline is tested with FPGA build #289 Issues Fixed - 1. LEDs start flickering when driver current sent in quick succession 2. Modifed software reset is now done via SSF_CONTROL[0x0480] register BIT3, SSF_SW_RESET ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 24March2010 MCU SW Version - 0.8.0 This software baseline is tested with FPGA build #289 New feature added - 1. Auto reset by MCU upon flash download completion. 2. Updated register map as per FPGA build #289 Issues fixed - 1. # pkts received in flash download response pkt overwriting crc16 data bytes. 2. PAT LUT Mailbox not closing after download completion. 3. ABF disable register[0x0424] is always set to 0x00. Known Issues - 1. Upon auto reset BIST test shows FAIL; may be related to UMC setup on reset without powering down DDR2 memory. Normal power cycle shows BIST passed. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 12March2010 MCU SW Version - 0.7.0 This software baseline is tested with FPGA build #274 Changes - 1. Added support to inform pc software if a corrupt packet received as part of multipacket transaction. 2. fpga register maps updated as per build #274. 3. New functionality added to reapply (or refresh) the LED Driver Level settings whenever the LED Current settings are changed. 4. In the init as part of tpg_setup the register default changed form Reg[0x0028] = 0x800 to 0x00. 5. Increased BIST test timeout from 1Second to 5 Second. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 05March2010 MCU SW Version - 0.6.2 This software baseline is tested with FPGA build #249. Modifications - 1. Added support to include number of bytes received in the response packet for multipacket transaction. This needed to detect dropped packets after bulk transfer (or mutlipacket). 2. Added option to skip CRC16 computation; for this FlashEraseSetup cmd packet (CMD2=0x07) sent with CMD3 BIT1 = '1'. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 02March2010 MCU SW Version - 0.6.1 This software baseline is tested with FPGA build #249. New things - 1. Rebuild the application with modified BSP settings to output debug logs via UART output port instead of UARTJTAG debugger port. To see the log, uart settings should be set to data_bits = 8, baud_rate = 115200, stop_bits = 1, parity = none, flow_control = none. 2. Dynamic debug output log capability added; this feature will allow user to selective display debug logs from modules like system_init, serial_flash, edid_eeprom, packet_processing, usb_if, spi_slave_if. Modifications - 1. Removed custom timer driver code timer.c/.h which instead Altera's standard timer driver used. Issues fixed - 1. LED Driver current packets sent more than twice whenever user updates the drive level; otherwise flickering of LEDs seen. 2. Whenever DMD is parked; shadow light seen on the wall. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 23Feb2010 MCU SW Version - 0.6.0 This software baseline is tested with FPGA build #249. New things - 1. SPI Slave interface support added. Now, user can send commands via SPI Slave port. 2. IR LED Control support added. (un-tested) 3. CMT LUT loaded as part of system power-up routine. 4. Support added to Numonyx serial flash part. 5. BIST added as part of system power-up routine. Modifications - 1. LED Driver is enable in system_init is moved to the end of initialization step; i.e., after BIST, default_initialization, init_from_flash. 2. LED Drive level is set to 50%,75%,50% respectively for R,G,B LEDs 3. References to alt_printf and alt_putstr is replaced with generic printf() functions. These are used as part of debug statements. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 15Feb2010 MCU SW Version - 0.5.0 This software baseline is tested with FPGA build #236 and #237. New things - 1. EDID info update support added. Hot Plug Detect pin held low until EDID verification/update is complete. Enhancements - 1. LED SPI packet communication to detect SPI failure for every packet transaction 2. LED Driver current updated as follows - Led max operating current - 8.1Amps for R, G, B Leds LED Driver max o/p current - 15.0 Amps 3. Now default LED drive level current is modified to 10% of max level. 4. In case of flash erase failure return failed response immediately. For example – missing parallel flash on the board. Issue Fixes- 1.USB communication hangs when System is powered with LED SPI cable disconnected. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 08Feb2010 MCU SW Version - 0.4.3 This software baseline is tested with FPGA build #236 and #237. Fixes - CRC16 value not returned properly by the MCU in response packet. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 05Feb2010 MCU SW Version - 0.4.2 This software baseline is tested with FPGA build #236 and #237. New things - Highlights: 1.Supports CRC16 value generation after flash content download. CRC16 generation will match to the LOGIC APP computed CRC16. 2.SW registers related to Sequence i.e., REG# 0x0CC4 to 0x0CD8 is now made available to API access. Note, MCU will not take action when register is updated. 3.Updated rtr_allocation table. Issues/Fixes: 1.Resolved issue related to MCU continuously sending LED Current updates in idle state. Now, MCU sends current level whenever user updates 'current level settings'. 2.LED_SPI Status failure detection made more robust; now after every packet sent check is made whether led_spi link is working fine. 3.SystemStatus register readback function in the mcu code is modified to return 'latest' status; earlier the status presented used to be from system_task, which will collect the information when the task is active. 4.Modified system_init routine; first, default hard_coded intialization will happen, later on the setting would be overwritten by the user cfg data stored in the flash (init from the flash). 5.In the usb data transfer functionality; timeout is added while sending the response packe. Further, usb task is modified usb_task to send the packet to command_handler task if it detects packet is corrupted i.e., packet header_mismatch. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 29Jan2010 MCU SW Version - 0.4.1 This software release is tested with FPGA build #236. 1. System init from parallel flash is supported. Fixes/Enhacements - 1. System init modified to check DMD_Park state; if the DMD is parked then DAD/DMD and LED Driver intialization will be skipped. Once the switch on board is flipped to un-park; system comes up properly. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 23Jan2010 MCU SW Version - v0.4.0 This software will be work with FPGA build #195 and above; this has been tested with latest FPGA build #221 with associated PBC Spec. 1. Flash Erase support (separte packet) added for flash download speed improvement. 2. LED Driver supports DAC Level adjustment 8-bit or 10-bit based on the manufacturer's HW ID and FW ID. 3. LED Driver failure system_status flag updated. Flag will be set when a) whenever LED SPI failures are detected b) LED_LIT signal goes LOW. 4. System Idle task modified to run periodically 500mSec; note this task kicks in only when there is no activity on USB port. 5. SW_Version format changed to x.x.x format (where 'x' is 1-nibble) 6. DMD_NOT_DETECT flag added in system status when MCU fails to read DMD_Device ID. 7. Parallel Flash support added. 8. DMA support added; this will enable pattern DMA from parallel flash to DDR2 memory. PI: Refer instructions before using Pattern download over parallel flash then performing DMA. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 07thjan2010 MCU SW Version - v0.3.9 This SW baseline will work with FPGA build #195 equivalent PBC Spec v6.8 1. Serial Flash (SPI Flash) support is provided. 2. System Status register is not accessible; reg details - [0x0ca0] SW_SYSTEM_STATUS (Software system status) 3. Internal Code review is done in TII; the review comments are incorporated. Major changes include 3.1 File names changed to more meaningful names. Example rtos.c/.h to resources_rtos.c/.h pakcetCreator.c/.h to packet_creator.c/.h 3.2 Data copy from/to USB HW FIFO is improved by copying word instead of byte. 3.3 Data Copy function that copied data from USB HW FIFO is now moved from USB_IRQ_Handler to USB Task. 3.4 Unused code (earlier used for debuggging) is commented out. 3.5 Local and global functions arranged seprately in each file. 3.6 DMD_DAD_SPI low level interfaces spi_read/write are modified i.e., semaphore reserve and release added. This was earlier in dmd.c and dad.c which is redundant. 3.7 common error code file adde ret_error_codes.h 3.8 Function return type modified to return ERROR_T (which is typedef int08) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 17thDec2009 MCU SW Version - v0.3.8 ---------------------------------------------- Support user setting LED Currents and changing LED_Drive_Level (intensity) from 0 to 255. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 16thDec2009 MCU SW Version - v0.3.7 --------------------------------------------- 1. rtr_alloc.c file changed, this as per suggestion from Jonathan Lucas. As compared to previous file the table enables DDR2 refreshes. The user can see artifacts in "Pattern mode" if the table is not updated. 2. EDID program supported, now eeprom chip is will be programmed with below mentioned info. MCU software takes care of not overwriting the info everytime. EDID Version 1.3 =============== Vendor ID – TII (it allows three chars only so I programmed as TII) Product ID - 0001 Serial Number - 0 Mfg week - 51 Mfg year - 2009 Digital - source Display type - RGB color Gamma - 100 Established timings - 1024*768 @ 60Hz Known issues: There is limited testing done wrt programming of EDID device. So far looks good. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Date: 15thDec2009 MCU SW Version - v0.3.6 ---------------------------------------------- 1. The software version naming convention is now changed from 0.0.3(5) type to 0.3.6 format. Now you should be able to read the version from sw register as 0.3.6. 2. This MCU software version will support PBC_Spec 6.8 however few register(s) are not completly implemented. Non-implemented SW registers - 2.1 Whatever values written into these register will not be taken into effect. 0x0c30 SW_LED_CURRENT_RED SW_LED_CURRENT_RED 0x0c34 SW_LED_CURRENT_GREEN SW_LED_CURRENT_GREEN 0x0c38 SW_LED_CURRENT_BLUE SW_LED_CURRENT_BLUE 0x0c3c SW_LED_CURRENT_IR SW_LED_CURRENT_IR 0x0cac SW_SCRPAD_X MCU X Scratchpad Register 0x0cb0 SW_SCRPAD_Y MCU Y Scratchpad Register 0x0cb4 SW_SCRPAD_SET MCU Scratchpad SET Register 0x0cb8 SW_FLSH_PACKET_ADDR MCU Flash Packet Addr Register 0x0cbc SW_FLSH_PACKET_NBYTES MCU Flash Packet Nbytes Register 0x0cc0 SW_FLSH_PACKET_RUN MCU Flash Packet Run Register 0x0cc4 SW_SEQDAT_MODE Seq Dat mode register 0x0cc8 SW_SEQDAT_NPATS Seq Dat Number of patterns Register 0x0ccc SW_SEQDAT_BPP Seq Dat Number of bits per-pixel Register 0x0cd0 SW_SEQDAT_FRMRATE Frame Rate Register 0x0cd4 SW_SEQDAT_EXP Seq Dat SL Exposure Register 0x0cd8 SW_SEQDAT_DLLVER Seq Dat DLL Version Register 2.2 You can change the LED_levels b/w 0-100 but try to restric below 80. 3. FPGA build to use #184 4. Features not implemented or not working 4.1 EEPROM Program or EDID 4.2 Serial Flash 4.3 Parellel Flash 4.4 Anything related SPI Slave 4. Rest of the features are supported except the things mentioned in #4 above