I noticed that the technical reference document (rev b, dec 2008) for the OMAP-L137 shows documentation for the AINTC memory map for ECR[0]-ECR[3] with 16 bytes, but documents only ECR[1] through ECR[3]. Making me more curious is the fact that ESR[0]-ESR[3] is documented with only 12 bytes. Again the documentation is for only 3 registers.
Am I to assume that ECR1 is at 0xfffee300? or is it at 0xfffee304?
Hi Flamingo,
Please see page 201 of the document:
OMAP-L137 Applications Processor System Reference Guide
http://www-s.ti.com/sc/techlit/SPRUG84
And also see page 73 of the datasheet:
http://www.ti.com/lit/gpn/omap-l137
So offset 0 in the first document is 0xFFFE E000 in the memory map (see datasheet).
ECR1 is at 0xFFFEE380
Hi Mariana,
Is there any example code using the ARM interrupts without Linux? I need to implement interrupts on "bare" omap-l137
Not really. Our software offering for the ARM is Linux dependent.
Earlier in the year I did a port of the ARM side of OMAP-L137 to FreeRTOS and was posted to SourceForge. The source will show you how to implement interrupts using the AINTC on a "bare" omap-l137. Includes full startup code, assembler, etc...
Link is in below thread. Do a search and you will find other discussions:
https://community.ti.com/forums/p/2031/14396.aspx#14396
Kev
Thank you very much ! I'll try it
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