Part Number: LM4819
My customer have the pop noise issue when power down timing.
Output waveforms and schematics are below,
The condition2 is little bit improved the pop noise than conditon1. However. customer have to decrease the pop noise more.
Could you please give me your advice for improvement method?
Condition1: Ci=0.22uF, Ri=47kΩ, Cb=1uF
(Ch1：VDD(5V) Ch3：Vo2＋ Ch4：Vo1- Math：Ch3-Ch4)
Condition2: Ci=0.1uF, Ri=100kΩ, Cb=1uF
Schematics (same circuit in datasheet)
I missed the attached file.
In reply to Yusuke Mukuno:
In reply to José Luis:
Customer try device shutdown before Vdd power down. They use SHUTDOWN pin. SHUTDOWN pin is active-high. In this case, the pop noise is improved.
Shutdown pin is pulled up other 5V power supply. (Controled by MCU)
At that time. It will become VDD pin voltage < Shutdown pin voltage .
Is it no problem?
I willl try to suggest pull-up to Vdd to customer.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.