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Audio Amplifiers Forum
TAS5630 abnormal failure
Can anybody help me?
I have made one PCB for TAS5630DKD testing, using all TI recomended layout. I also have added to my board one preamplifier to filter the audio input signal (Low pass and high pass). The TAS5630 stage is powered by +49V DC (PVDD) and +12V by an 7812 regulator for GVDD supply, and my preamplifier is supplied by +/-15V simmetric supply.
A problem was occurred, result in failure of TAS5630 chip (i have burned about five chips in my tests), when I plug the audio signal cable on the RCA jack of preamplifier with the TAS5630 active (READY). I know, in this condition one large transient is generated - in another amps, also in TAS5630PHD evaluation board this generate a great POP noise into speaker, but in my board this action results in a chip failure.
The problem occur also when I disconnect the preamplifier output from TAS5630 amp and insert the audio signal direct into inputs (by electrolytic capacitor and 100R resistor as recommended) - Any transient generated by cable "plug and unplug" when the chip is active (READY) causes a serious failure of TAS5630...
Junho, if one of the decoupling caps is not soldered, or if it is broken, it probably will not function as it should. Then the PVDD pin to which it is supposed to connect will have no close decoupling, and switching spikes there could be very high. This could be destructive to the IC.
Please also see my post earlier today, to you and Paulo.
You certainly can reduce OPA1632 power supply voltage, but OPA1632 cannot operate with a power supply below 5V (see page 4 of data sheet SBOS286B, which says minimum operating voltage is +/-2.5V for the power supply, or 5V for single-ended supply).
I recommend using 6V so that OPA1632 output voltage after saturation drops is enough to drive TAS5630 into clipping to provide full output. (OPA1632 output saturation drops can be around 1.5V (see page 3 of the data sheet, which says voltage output swing is a maximum of 1.9V above negative power supply and 1.9V below positive power supply with 2k load - input impedance of TAS5630 is 33k, so I think maximum output saturation drops with TAS5630 input as the load are around 1.5V).
I have tried this and it works very well. Of course, it requires a 6V power supply in addition to the GVDD 12V supply.
Dear Steve,Thank you for fast reply.Due to layout limitation, the decoupling 2,2uF caps was placed about 5mm far from the IC. But I think so improve the layout when as possible - but not close as the EVM because some layout mechanical issues (in my project I cannot use double-sided component placing because the PCB is double-sided but components are assembled only in TOP layer, different of Texas EVM wich have components assembled in both sides).You can't see the thermal grease because the IC was carefully cleaned before I taking the picture. And the IC have a direct contact with aluminum heatsink, without thermal pads, only a thin layer of thermal grease is applied. When this failure occurred, the IC had heatsink attached.I remember which only the first procedure of board testing is made without heatsink - At this step, we check only the input / output signals without load into output. If pass, the heatsink is attached and the board is tested again, with load and at rated power.Can the first test procedure damage the device?Best regardsPaulo
Paulo, I will recommend copying the EVM as completely as possible when you improve the layout. You can bring the BST caps to the top layer, but please push the close decoupling caps as close to the IC as possible, and please follow the routing of outputs, PVDD and PGND in the EVM to produce the lowest inductance connections.
Connections to the BST caps are not so critical, because they do not carry the heavy currents that the output and power traces carry. Of course, keep BST traces as short as possible, but it is OK to use a short trace on bottom layer with a via at each end for BST caps A and D.
I think it may be possible to damage an IC in the test condition you described above, so that it fails later. We don't know this for certain, though. An open load condition is not benign - there is an impedance notch at the resonant frequency of the filter, and this can generate very high currents if the output signal contains any harmonic at the resonant frequency. This can happen with outputs in clipping, because those signals include a very strong harmonic series.
We can't be sure if this test condition could damage ICs, but it is not a good condition. Maybe the heatsink can be grounded temporarily somehow during the test?
How are you...
It's me again.
1) Tahnk you for your assist. but I still want to know about "SD LED's turning itself ON.
What, if there is any, causes the damage on pin55?
2) About C25, thank you so much.
3) About the power supply voltage. Thank you very much. 5 or 6Volt was ok.
when I use supply voltage 5volt,should I need to change each polarity of C14,C15?
Junho, I recall that you said this in another post: --- After 4 hours of general operation "SD" LED turn on itself. I found that R29 (3.3ohms) connecting to GVDD_A (pin 55 of TAS 5630 PHD) changed its color black as if it got burnt out. The voltage of the pin 55 was 6 volt (12V is a normal voltage). ---
There is certainly damage to the IC if GVDD_A is stuck at 6Vdc. That will drive /SD low, and that will turn on the SD LED. But I think the damage starts with some overvoltage or other problem. I think it does not start at GVDD_A.
I have not seen what voltage you are using for PVDD, but if it is 40 or 50 V I think maybe a 5V power supply to OPA1632 is a little low. OPA1632 saturation drops are typically about 2V total with the TAS5630 as load, but they may somewhat higher. But with a 5V power supply even 2V saturation loss leaves only 3V differential output. TAS5630 minimum gain is around 23dB, ~x14. With that gain, when OPA1632 clips TAS5630 will output only ~42V peak, so it may not reach full output in clipping. So I will recommend 6Vdc power supply to OPA1632, unless you are using less than 40V for TAS5630 PVDD.
With 5 or 6 Vdc power supply to OPA1632, its DC bias point will be 2.5 or 3 Vdc, and this is still higher than DC bias at input of TAS5630, even with PVDD ~50V (there, input bias is near 2Vdc). So the polarity of the input caps does not change.
Steve, is there any reason not to design for X7R surface-mount ceramic (non-polar) input capacitors? They are available in 1206 and 1210 sizes and seem reasonably priced.
X7R caps contribute to THD at low frequencies. the TAS5630 is high performing enough that you see a difference between ceramic and electrolytic. So, we use electrolytic on the EVM. if you're not as concerned with THD, then ceramics are fine.
Audio Applications Engineering Manager
Dallas, TX USA
Thanks for reminding me of the distortion differences. Can you reference any objective distortion comparisons between 10uF X7R caps and tantalum caps at low frequency? The only similar comparison I have seen is at http://industrial.panasonic.com/ww/i_e/21088/smd-film-capacitor_e/smd-film-capacitor_e/data/02.html. It shows that 1uF X7R caps have less distortion than 1uF tantalum caps at about 400Hz or less. Above 400Hz, the tantalum caps are better. 50 to 400Hz is the frequency range that I am interested in, but I don't know how different the results would be for 10uF caps and TAS5630 input loads in PBTL mode.
Another thing I wonder about is leakage. I am pretty much stuck with using 16V 1206-size caps for now. Tantalum leakage rating (for Kemet T491A106K016AT) is equivalent to about 8Megohms at 20 degrees C. 10uF X7R leakage rating can be much better (100Megohms for AVX, 50Megohms for Kemet, but only 5Megohms for Murata, for examples). With about 4VDC of bias, the AVX X7R caps could be expected to have up to about 0.50-0.04=0.46uA less leakage than these tantalum caps. That could lower the TAS5630 output voltages by about 0.23VDC at room temperature. DC output voltages of all of the several EVM's I have, are a little less than half of their 48VDC supply. Lower input capacitor leakage should raise their DC outputs closer to half of the power supply voltage, which might allow slightly higher symmetrical output voltage swings.
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