The data sheet for the PGA2311 descibes serial port timing requirements but does not elaborate on when data received by the serial port is transfered to the attenuation registers. Does this occur on the negation (rising edge) of Chip Select.
Also, I wish to share the 3wire SPI communication path with multiple SPI devices and am concerned about potential impact of SPI activity on the PGA2311's S/N floor. Is activity on SCLK and SDI masked within the chip by the negated (high) state of Chip Select in order to minimize noise and crosstalk of the digital portion of the chip to the analog section.
Hello Guenther,
The control data needs to be provided as a 16 bit word, clocked into the SDI on the rising edge on SCLK; I verified on the EVM that the data is transferred to the Gain/Attenuation registers on the rising edge of CS. You may also find more information on the post below:
http://e2e.ti.com/support/amplifiers/audio_amplifiers/f/6/t/62.aspx
The device provides separate pins for the digital and analog voltage supplies, therefore there should be very good isolation between the analog and digital circuitry inside the device. Typically, the most critical issue is to route in the board layout the sensitive analog signals in one side of the board with their return path, and the noisy digital signals on the other side with their return path. Keep all the analog precision away from the digital signals and noise sources. The datasheet provides some board layout recommendations on page 12.
Best Regards,
Luis
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