using the evaluation kit tas5342ddv6evm with TAS5508 I managed to set volumes, EQ's etc. but I've questions about Interchannel delay setting :
- The delays correspond to cycles of the high-speed internal clock, DCLK [TAS5508C datasheet]. But what is DCLK and it's frequency?
-Trying to set and measure delays between channels I could not recognize an impact. I measure the acoustic signal and estimate to be able to detect delay changes down to 0.2ms. Is the maximum interchannel delay <~ 0.2ms or is my register setting procedure not correct? With TAS5508GUI V4 a muted channels, write delay values to the registers 0x1B and following and then unmuted channels.
Any help appreciated as setting Interchannel delays is vital for evaluation/application.
The ICD (Inter Channel Delay) basically controls the h-bridge timing and is used to optimize THD levels. I can't find the optimal ICD settings right now, but let me check around and see if I can locate them.
Audio Applications Engineering Manager
Dallas, TX USA
thanks for your reply! So the purpose of this delays is not what I thought.
Would be nice to let us know the optimal Inter Channel Delay values for the Digital Power Amplifier Stage TAS5342A which is on the Kit tas5342ddv6evm
- or to confirm that the TAS5508C defaults are ok for low THD.
Sorry for the delay. Are you still working on this?
yes I do.
D clock is 196.6 MHz. As Don mentioned, it is used for improving harmonic distortion and cross-talk between adjacent channels. The default values on the chip work best on our characterization board. We don't have a set of values for the evaluation board. The values vary with different layout but in general default values work best.
Texas Instruments, Inc.
1) How much different impact to THD between best and worst setting of ICD ?
2) I checked the waveform of channel 1-4, It seem to be always BD modulation when set to 2.1 mode even when config is AD. (TAS5711). Is it correct?
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