We just completed a 50V power supply designed to charge a 26.4mF cap bank and used this to then power a TAS5630DKD eval kit. Our application only calls for short output pulses (underwater transducer) with a focus on power conservation. The power supply charges the caps, then the caps are connected to the TAS5630, the pulse is output, and then the caps are disconnected from both the TAS5630 and the power supply. A high current P-FET is currently used to connect the cap bank to the banana jack inputs on the TAS5630. It has been working great so far; the caps hold their charge for several minutes. The TAS5630 is in PBTL mode and a matching transformer is used to present a 3 ohm load. We need at least 200W output power but we want to design towards the max of the chip, 400W. Our next goal is to build a single board solution; power supply, cap bank, and a TAS5630BPHD on one PCB to try to make it as light and compact as possible.
My main question is: What is the best way to combine our cap bank with the bulk caps on the TAS5630 circuit?
I currently have qty 12, 2200uF 63V caps as the cap bank; they take up a lot of space so I would like to combine these with the 4 1000uF caps on the TAS5630. It also seems wasteful to re-charge the 4 1000uF caps for every pulse. My first thought would be to just use a flooded plane to connect all of the PVDD_X pins to the drain of a low Rds MOSFET. The cap bank would then be located just outside the heat sink, using another flood to connect all of the caps to the source of the MOSFET.
The EVM reference layout deliberately separates the connection from the +50V supply so that each PVDD_X pin pair draws current from its own 1000uF cap instead of just having a flooded plane. To replicate this layout I could use 4 MOSFETs, one for each PVDD_X pin pair, and then fan-out to groups of 3 2200uF caps, but that would result in more components and a more complicated layout.
How critical is it to have these separated supply traces? Is this necessary or was it routed in that fashion since it is only a 2-layer board and the output traces had to run in between? I have no problem moving to a 4-layer design if needed to have a dedicated PVDD plane. Is the Rds of the MOSFET going to be the main problem? I wanted to get an opinion from TI before I made things too complicated or missed a detail that results in poor performance and a re-design.
Wow, I thought for sure I responded to your post earlier. Well, I guess I did --> in my mind...
Anyway, we separate the two channels to improve cross-talk. If you tie them together, you will lose a few dB of crosstalk... if you don't care about that, then go for it.
As for your idea of moving the bulk decoupling caps to the other side of your mosfet switch, I see no issue in that, AS LONG as you have ceramic decoupling tight to the part itself. As you probably know, the inductance in a high-power class-D is critical, so please use care...
Why don't you just use our RESET-z pin for power-savings? This drops the supply current to 870 uA..
Audio Applications Engineering Manager
Dallas, TX USA
Thank you, you answered all of my questions. I will make sure the 2.2uF caps take priority in the layout near the input power pins.
I'll take a 2nd look if we can use the RESET pin instead. We are tying to be as power greedy as possible since we are running off of battery packs that have to last for more than a year.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.